cpu/ppc4xx/speed.c

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <ppc_asm.tmpl>
  26 #include <ppc4xx.h>
  27 #include <asm/processor.h>
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 #define ONE_BILLION        1000000000
  32 #ifdef DEBUG
  33 #define DEBUGF(fmt,args...) printf(fmt ,##args)
  34 #else
  35 #define DEBUGF(fmt,args...)
  36 #endif
  37
  38 #if defined(CONFIG_405GP) || defined(CONFIG_405CR)
  39
  40 void get_sys_info (PPC405_SYS_INFO * sysInfo)
  41 {
  42         unsigned long pllmr;
  43         unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
  44         uint pvr = get_pvr();
  45         unsigned long psr;
  46         unsigned long m;
  47
  48         /*
  49          * Read PLL Mode register
  50          */
  51         pllmr = mfdcr (pllmd);
  52
  53         /*
  54          * Read Pin Strapping register
  55          */
  56         psr = mfdcr (strap);
  57
  58         /*
  59          * Determine FWD_DIV.
  60          */
  61         sysInfo->pllFwdDiv = 8 - ((pllmr & PLLMR_FWD_DIV_MASK) >> 29);
  62
  63         /*
  64          * Determine FBK_DIV.
  65          */
  66         sysInfo->pllFbkDiv = ((pllmr & PLLMR_FB_DIV_MASK) >> 25);
  67         if (sysInfo->pllFbkDiv == 0) {
  68                 sysInfo->pllFbkDiv = 16;
  69         }
  70
  71         /*
  72          * Determine PLB_DIV.
  73          */
  74         sysInfo->pllPlbDiv = ((pllmr & PLLMR_CPU_TO_PLB_MASK) >> 17) + 1;
  75
  76         /*
  77          * Determine PCI_DIV.
  78          */
  79         sysInfo->pllPciDiv = ((pllmr & PLLMR_PCI_TO_PLB_MASK) >> 13) + 1;
  80
  81         /*
  82          * Determine EXTBUS_DIV.
  83          */
  84         sysInfo->pllExtBusDiv = ((pllmr & PLLMR_EXB_TO_PLB_MASK) >> 11) + 2;
  85
  86         /*
  87          * Determine OPB_DIV.
  88          */
  89         sysInfo->pllOpbDiv = ((pllmr & PLLMR_OPB_TO_PLB_MASK) >> 15) + 1;
  90
  91         /*
  92          * Check if PPC405GPr used (mask minor revision field)
  93          */
  94         if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
  95                 /*
  96                  * Determine FWD_DIV B (only PPC405GPr with new mode strapping).
  97                  */
  98                 sysInfo->pllFwdDivB = 8 - (pllmr & PLLMR_FWDB_DIV_MASK);
  99
 100                 /*
 101                  * Determine factor m depending on PLL feedback clock source
 102                  */
 103                 if (!(psr & PSR_PCI_ASYNC_EN)) {
 104                         if (psr & PSR_NEW_MODE_EN) {
 105                                 /*
 106                                  * sync pci clock used as feedback (new mode)
 107                                  */
 108                                 m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllPciDiv;
 109                         } else {
 110                                 /*
 111                                  * sync pci clock used as feedback (legacy mode)
 112                                  */
 113                                 m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllPciDiv;
 114                         }
 115                 } else if (psr & PSR_NEW_MODE_EN) {
 116                         if (psr & PSR_PERCLK_SYNC_MODE_EN) {
 117                                 /*
 118                                  * PerClk used as feedback (new mode)
 119                                  */
 120                                 m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllExtBusDiv;
 121                         } else {
 122                                 /*
 123                                  * CPU clock used as feedback (new mode)
 124                                  */
 125                                 m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv;
 126                         }
 127                 } else if (sysInfo->pllExtBusDiv == sysInfo->pllFbkDiv) {
 128                         /*
 129                          * PerClk used as feedback (legacy mode)
 130                          */
 131                         m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllExtBusDiv;
 132                 } else {
 133                         /*
 134                          * PLB clock used as feedback (legacy mode)
 135                          */
 136                         m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv;
 137                 }
 138
 139                 sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
 140                         (unsigned long long)sysClkPeriodPs;
 141                 sysInfo->freqProcessor = sysInfo->freqVCOHz / sysInfo->pllFwdDiv;
 142                 sysInfo->freqPLB = sysInfo->freqVCOHz / (sysInfo->pllFwdDivB * sysInfo->pllPlbDiv);
 143         } else {
 144                 /*
 145                  * Check pllFwdDiv to see if running in bypass mode where the CPU speed
 146                  * is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO
 147                  * to make sure it is within the proper range.
 148                  *    spec:    VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV
 149                  * Note freqVCO is calculated in Mhz to avoid errors introduced by rounding.
 150                  */
 151                 if (sysInfo->pllFwdDiv == 1) {
 152                         sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ;
 153                         sysInfo->freqPLB = CONFIG_SYS_CLK_FREQ / sysInfo->pllPlbDiv;
 154                 } else {
 155                         sysInfo->freqVCOHz = ( 1000000000000LL *
 156                                                (unsigned long long)sysInfo->pllFwdDiv *
 157                                                (unsigned long long)sysInfo->pllFbkDiv *
 158                                                (unsigned long long)sysInfo->pllPlbDiv
 159                                 ) / (unsigned long long)sysClkPeriodPs;
 160                         sysInfo->freqPLB = (ONE_BILLION / ((sysClkPeriodPs * 10) /
 161                                                            sysInfo->pllFbkDiv)) * 10000;
 162                         sysInfo->freqProcessor = sysInfo->freqPLB * sysInfo->pllPlbDiv;
 163                 }
 164         }
 165 }
 166
 167
 168 /********************************************
 169  * get_OPB_freq
 170  * return OPB bus freq in Hz
 171  *********************************************/
 172 ulong get_OPB_freq (void)
 173 {
 174         ulong val = 0;
 175
 176         PPC405_SYS_INFO sys_info;
 177
 178         get_sys_info (&sys_info);
 179         val = sys_info.freqPLB / sys_info.pllOpbDiv;
 180
 181         return val;
 182 }
 183
 184
 185 /********************************************
 186  * get_PCI_freq
 187  * return PCI bus freq in Hz
 188  *********************************************/
 189 ulong get_PCI_freq (void)
 190 {
 191         ulong val;
 192         PPC405_SYS_INFO sys_info;
 193
 194         get_sys_info (&sys_info);
 195         val = sys_info.freqPLB / sys_info.pllPciDiv;
 196         return val;
 197 }
 198
 199
 200 #elif defined(CONFIG_440)
 201
 202 #if  defined(CONFIG_440EP) || defined(CONFIG_440GR)
 203 void get_sys_info (sys_info_t *sysInfo)
 204 {
 205         unsigned long temp;
 206         unsigned long reg;
 207         unsigned long lfdiv;
 208         unsigned long m;
 209         unsigned long prbdv0;
 210         /*
 211           WARNING: ASSUMES the following:
 212           ENG=1
 213           PRADV0=1
 214           PRBDV0=1
 215         */
 216
 217         /* Decode CPR0_PLLD0 for divisors */
 218         mfclk(clk_plld, reg);
 219         temp = (reg & PLLD_FWDVA_MASK) >> 16;
 220         sysInfo->pllFwdDivA = temp ? temp : 16;
 221         temp = (reg & PLLD_FWDVB_MASK) >> 8;
 222         sysInfo->pllFwdDivB = temp ? temp: 8 ;
 223         temp = (reg & PLLD_FBDV_MASK) >> 24;
 224         sysInfo->pllFbkDiv = temp ? temp : 32;
 225         lfdiv = reg & PLLD_LFBDV_MASK;
 226
 227         mfclk(clk_opbd, reg);
 228         temp = (reg & OPBDDV_MASK) >> 24;
 229         sysInfo->pllOpbDiv = temp ? temp : 4;
 230
 231         mfclk(clk_perd, reg);
 232         temp = (reg & PERDV_MASK) >> 24;
 233         sysInfo->pllExtBusDiv = temp ? temp : 8;
 234
 235         mfclk(clk_primbd, reg);
 236         temp = (reg & PRBDV_MASK) >> 24;
 237         prbdv0 = temp ? temp : 8;
 238
 239         mfclk(clk_spcid, reg);
 240         temp = (reg & SPCID_MASK) >> 24;
 241         sysInfo->pllPciDiv = temp ? temp : 4;
 242
 243         /* Calculate 'M' based on feedback source */
 244         mfsdr(sdr_sdstp0, reg);
 245         temp = (reg & PLLSYS0_SEL_MASK) >> 27;
 246         if (temp == 0) { /* PLL output */
 247                 /* Figure which pll to use */
 248                 mfclk(clk_pllc, reg);
 249                 temp = (reg & PLLC_SRC_MASK) >> 29;
 250                 if (!temp) /* PLLOUTA */
 251                         m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
 252                 else       /* PLLOUTB */
 253                         m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivB;
 254         }
 255         else if (temp == 1) /* CPU output */
 256                 m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
 257         else /* PerClk */
 258                 m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
 259
 260         /* Now calculate the individual clocks */
 261         sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
 262         sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
 263         sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
 264         sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
 265         sysInfo->freqEPB = sysInfo->freqPLB/sysInfo->pllExtBusDiv;
 266         sysInfo->freqPCI = sysInfo->freqPLB/sysInfo->pllPciDiv;
 267
 268         /* Figure which timer source to use */
 269         if (mfspr(ccr1) & 0x0080) { /* External Clock, assume same as SYS_CLK */
 270                 temp = sysInfo->freqProcessor / 2;  /* Max extern clock speed */
 271                 if (CONFIG_SYS_CLK_FREQ > temp)
 272                         sysInfo->freqTmrClk = temp;
 273                 else
 274                         sysInfo->freqTmrClk = CONFIG_SYS_CLK_FREQ;
 275         }
 276         else  /* Internal clock */
 277                 sysInfo->freqTmrClk = sysInfo->freqProcessor;
 278 }
 279 /********************************************
 280  * get_PCI_freq
 281  * return PCI bus freq in Hz
 282  *********************************************/
 283 ulong get_PCI_freq (void)
 284 {
 285         sys_info_t sys_info;
 286         get_sys_info (&sys_info);
 287         return sys_info.freqPCI;
 288 }
 289
 290 #elif !defined(CONFIG_440GX) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
 291 void get_sys_info (sys_info_t * sysInfo)
 292 {
 293         unsigned long strp0;
 294         unsigned long temp;
 295         unsigned long m;
 296
 297         /* Extract configured divisors */
 298         strp0 = mfdcr( cpc0_strp0 );
 299         sysInfo->pllFwdDivA = 8 - ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 15);
 300         sysInfo->pllFwdDivB = 8 - ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 12);
 301         temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 18;
 302         sysInfo->pllFbkDiv = temp ? temp : 16;
 303         sysInfo->pllOpbDiv = 1 + ((strp0 & PLLSYS0_OPB_DIV_MASK) >> 10);
 304         sysInfo->pllExtBusDiv = 1 + ((strp0 & PLLSYS0_EPB_DIV_MASK) >> 8);
 305
 306         /* Calculate 'M' based on feedback source */
 307         if( strp0 & PLLSYS0_EXTSL_MASK )
 308                 m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
 309         else
 310                 m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
 311
 312         /* Now calculate the individual clocks */
 313         sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
 314         sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
 315         sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB;
 316         if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */
 317                 sysInfo->freqPLB >>= 1;
 318         sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
 319         sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
 320
 321 }
 322 #else
 323 void get_sys_info (sys_info_t * sysInfo)
 324 {
 325         unsigned long strp0;
 326         unsigned long strp1;
 327         unsigned long temp;
 328         unsigned long temp1;
 329         unsigned long lfdiv;
 330         unsigned long m;
 331         unsigned long prbdv0;
 332
 333 #if defined(CONFIG_440SPE)
 334         unsigned long sys_freq;
 335         unsigned long sys_per=0;
 336         unsigned long msr;
 337         unsigned long pci_clock_per;
 338         unsigned long sdr_ddrpll;
 339
 340         /*-------------------------------------------------------------------------+
 341          | Get the system clock period.
 342          +-------------------------------------------------------------------------*/
 343         sys_per = determine_sysper();
 344
 345         msr = (mfmsr () & ~(MSR_EE));   /* disable interrupts */
 346
 347         /*-------------------------------------------------------------------------+
 348          | Calculate the system clock speed from the period.
 349          +-------------------------------------------------------------------------*/
 350         sys_freq=(ONE_BILLION/sys_per)*1000;
 351 #endif
 352
 353         /* Extract configured divisors */
 354         mfsdr( sdr_sdstp0,strp0 );
 355         mfsdr( sdr_sdstp1,strp1 );
 356
 357         temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 8);
 358         sysInfo->pllFwdDivA = temp ? temp : 16 ;
 359         temp = ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 5);
 360         sysInfo->pllFwdDivB = temp ? temp: 8 ;
 361         temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 12;
 362         sysInfo->pllFbkDiv = temp ? temp : 32;
 363         temp = (strp0 & PLLSYS0_OPB_DIV_MASK);
 364         sysInfo->pllOpbDiv = temp ? temp : 4;
 365         temp = (strp1 & PLLSYS1_PERCLK_DIV_MASK) >> 24;
 366         sysInfo->pllExtBusDiv = temp ? temp : 4;
 367         prbdv0 = (strp0 >> 2) & 0x7;
 368
 369         /* Calculate 'M' based on feedback source */
 370         temp = (strp0 & PLLSYS0_SEL_MASK) >> 27;
 371         temp1 = (strp1 & PLLSYS1_LF_DIV_MASK) >> 26;
 372         lfdiv = temp1 ? temp1 : 64;
 373         if (temp == 0) { /* PLL output */
 374                 /* Figure which pll to use */
 375                 temp = (strp0 & PLLSYS0_SRC_MASK) >> 30;
 376                 if (!temp)
 377                         m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
 378                 else
 379                         m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivB;
 380         }
 381         else if (temp == 1) /* CPU output */
 382                 m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
 383         else /* PerClk */
 384                 m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
 385
 386         /* Now calculate the individual clocks */
 387 #if defined(CONFIG_440SPE)
 388         sysInfo->freqVCOMhz = (m * sys_freq) ;
 389 #else
 390         sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
 391 #endif
 392         sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
 393         sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
 394         sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
 395         sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
 396
 397 #if defined(CONFIG_440SPE)
 398         /* Determine PCI Clock Period */
 399         pci_clock_per = determine_pci_clock_per();
 400         sysInfo->freqPCI = (ONE_BILLION/pci_clock_per) * 1000;
 401         mfsdr(sdr_ddr0, sdr_ddrpll);
 402         sysInfo->freqDDR = ((sysInfo->freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
 403 #endif
 404
 405
 406 }
 407
 408 #endif
 409
 410 #if defined(CONFIG_440SPE)
 411 unsigned long determine_sysper(void)
 412 {
 413         unsigned int fpga_clocking_reg;
 414         unsigned int master_clock_selection;
 415         unsigned long master_clock_per = 0;
 416         unsigned long fb_div_selection;
 417         unsigned int vco_div_reg_value;
 418         unsigned long vco_div_selection;
 419         unsigned long sys_per = 0;
 420         int extClkVal;
 421
 422         /*-------------------------------------------------------------------------+
 423          | Read FPGA reg 0 and reg 1 to get FPGA reg information
 424          +-------------------------------------------------------------------------*/
 425         fpga_clocking_reg = in16(FPGA_REG16);
 426
 427
 428         /* Determine Master Clock Source Selection */
 429         master_clock_selection = fpga_clocking_reg & FPGA_REG16_MASTER_CLK_MASK;
 430
 431         switch(master_clock_selection) {
 432                 case FPGA_REG16_MASTER_CLK_66_66:
 433                         master_clock_per = PERIOD_66_66MHZ;
 434                         break;
 435                 case FPGA_REG16_MASTER_CLK_50:
 436                         master_clock_per = PERIOD_50_00MHZ;
 437                         break;
 438                 case FPGA_REG16_MASTER_CLK_33_33:
 439                         master_clock_per = PERIOD_33_33MHZ;
 440                         break;
 441                 case FPGA_REG16_MASTER_CLK_25:
 442                         master_clock_per = PERIOD_25_00MHZ;
 443                         break;
 444                 case FPGA_REG16_MASTER_CLK_EXT:
 445                         if ((extClkVal==EXTCLK_33_33)
 446                                         && (extClkVal==EXTCLK_50)
 447                                         && (extClkVal==EXTCLK_66_66)
 448                                         && (extClkVal==EXTCLK_83)) {
 449                                 /* calculate master clock period from external clock value */
 450                                 master_clock_per=(ONE_BILLION/extClkVal) * 1000;
 451                         } else {
 452                                 /* Unsupported */
 453                                 DEBUGF ("%s[%d] *** master clock selection failed ***\n", __FUNCTION__,__LINE__);
 454                                 hang();
 455                         }
 456                         break;
 457                 default:
 458                         /* Unsupported */
 459                         DEBUGF ("%s[%d] *** master clock selection failed ***\n", __FUNCTION__,__LINE__);
 460                         hang();
 461                         break;
 462         }
 463
 464         /* Determine FB divisors values */
 465         if ((fpga_clocking_reg & FPGA_REG16_FB1_DIV_MASK) == FPGA_REG16_FB1_DIV_LOW) {
 466                 if ((fpga_clocking_reg & FPGA_REG16_FB2_DIV_MASK) == FPGA_REG16_FB2_DIV_LOW)
 467                         fb_div_selection = FPGA_FB_DIV_6;
 468                 else
 469                         fb_div_selection = FPGA_FB_DIV_12;
 470         } else {
 471                 if ((fpga_clocking_reg & FPGA_REG16_FB2_DIV_MASK) == FPGA_REG16_FB2_DIV_LOW)
 472                         fb_div_selection = FPGA_FB_DIV_10;
 473                 else
 474                         fb_div_selection = FPGA_FB_DIV_20;
 475         }
 476
 477         /* Determine VCO divisors values */
 478         vco_div_reg_value = fpga_clocking_reg & FPGA_REG16_VCO_DIV_MASK;
 479
 480         switch(vco_div_reg_value) {
 481                 case FPGA_REG16_VCO_DIV_4:
 482                         vco_div_selection = FPGA_VCO_DIV_4;
 483                         break;
 484                 case FPGA_REG16_VCO_DIV_6:
 485                         vco_div_selection = FPGA_VCO_DIV_6;
 486                         break;
 487                 case FPGA_REG16_VCO_DIV_8:
 488                         vco_div_selection = FPGA_VCO_DIV_8;
 489                         break;
 490                 case FPGA_REG16_VCO_DIV_10:
 491                 default:
 492                         vco_div_selection = FPGA_VCO_DIV_10;
 493                         break;
 494         }
 495
 496         if (master_clock_selection == FPGA_REG16_MASTER_CLK_EXT) {
 497                 switch(master_clock_per) {
 498                         case PERIOD_25_00MHZ:
 499                                 if (fb_div_selection == FPGA_FB_DIV_12) {
 500                                         if (vco_div_selection == FPGA_VCO_DIV_4)
 501                                                 sys_per = PERIOD_75_00MHZ;
 502                                         if (vco_div_selection == FPGA_VCO_DIV_6)
 503                                                 sys_per = PERIOD_50_00MHZ;
 504                                 }
 505                                 break;
 506                         case PERIOD_33_33MHZ:
 507                                 if (fb_div_selection == FPGA_FB_DIV_6) {
 508                                         if (vco_div_selection == FPGA_VCO_DIV_4)
 509                                                 sys_per = PERIOD_50_00MHZ;
 510                                         if (vco_div_selection == FPGA_VCO_DIV_6)
 511                                                 sys_per = PERIOD_33_33MHZ;
 512                                 }
 513                                 if (fb_div_selection == FPGA_FB_DIV_10) {
 514                                         if (vco_div_selection == FPGA_VCO_DIV_4)
 515                                                 sys_per = PERIOD_83_33MHZ;
 516                                         if (vco_div_selection == FPGA_VCO_DIV_10)
 517                                                 sys_per = PERIOD_33_33MHZ;
 518                                 }
 519                                 if (fb_div_selection == FPGA_FB_DIV_12) {
 520                                         if (vco_div_selection == FPGA_VCO_DIV_4)
 521                                                 sys_per = PERIOD_100_00MHZ;
 522                                         if (vco_div_selection == FPGA_VCO_DIV_6)
 523                                                 sys_per = PERIOD_66_66MHZ;
 524                                         if (vco_div_selection == FPGA_VCO_DIV_8)
 525                                                 sys_per = PERIOD_50_00MHZ;
 526                                 }
 527                                 break;
 528                         case PERIOD_50_00MHZ:
 529                                 if (fb_div_selection == FPGA_FB_DIV_6) {
 530                                         if (vco_div_selection == FPGA_VCO_DIV_4)
 531                                                 sys_per = PERIOD_75_00MHZ;
 532                                         if (vco_div_selection == FPGA_VCO_DIV_6)
 533                                                 sys_per = PERIOD_50_00MHZ;
 534                                 }
 535                                 if (fb_div_selection == FPGA_FB_DIV_10) {
 536                                         if (vco_div_selection == FPGA_VCO_DIV_6)
 537                                                 sys_per = PERIOD_83_33MHZ;
 538                                         if (vco_div_selection == FPGA_VCO_DIV_10)
 539                                                 sys_per = PERIOD_50_00MHZ;
 540                                 }
 541                                 if (fb_div_selection == FPGA_FB_DIV_12) {
 542                                         if (vco_div_selection == FPGA_VCO_DIV_6)
 543                                                 sys_per = PERIOD_100_00MHZ;
 544                                         if (vco_div_selection == FPGA_VCO_DIV_8)
 545                                                 sys_per = PERIOD_75_00MHZ;
 546                                 }
 547                                 break;
 548                         case PERIOD_66_66MHZ:
 549                                 if (fb_div_selection == FPGA_FB_DIV_6) {
 550                                         if (vco_div_selection == FPGA_VCO_DIV_4)
 551                                                 sys_per = PERIOD_100_00MHZ;
 552                                         if (vco_div_selection == FPGA_VCO_DIV_6)
 553                                                 sys_per = PERIOD_66_66MHZ;
 554                                         if (vco_div_selection == FPGA_VCO_DIV_8)
 555                                                 sys_per = PERIOD_50_00MHZ;
 556                                 }
 557                                 if (fb_div_selection == FPGA_FB_DIV_10) {
 558                                         if (vco_div_selection == FPGA_VCO_DIV_8)
 559                                                 sys_per = PERIOD_83_33MHZ;
 560                                         if (vco_div_selection == FPGA_VCO_DIV_10)
 561                                                 sys_per = PERIOD_66_66MHZ;
 562                                 }
 563                                 if (fb_div_selection == FPGA_FB_DIV_12) {
 564                                         if (vco_div_selection == FPGA_VCO_DIV_8)
 565                                                 sys_per = PERIOD_100_00MHZ;
 566                                 }
 567                                 break;
 568                         default:
 569                                 break;
 570                 }
 571
 572                 if (sys_per == 0) {
 573                         /* Other combinations are not supported */
 574                         DEBUGF ("%s[%d] *** sys period compute failed ***\n", __FUNCTION__,__LINE__);
 575                         hang();
 576                 }
 577         } else {
 578                 /* calcul system clock without cheking */
 579                 /* if engineering option clock no check is selected */
 580                 /* sys_per = master_clock_per * vco_div_selection / fb_div_selection */
 581                 sys_per = (master_clock_per/fb_div_selection) * vco_div_selection;
 582         }
 583
 584         return(sys_per);
 585
 586 }
 587
 588 /*-------------------------------------------------------------------------+
 589 | determine_pci_clock_per.
 590 +-------------------------------------------------------------------------*/
 591 unsigned long determine_pci_clock_per(void)
 592 {
 593         unsigned long pci_clock_selection,  pci_period;
 594
 595         /*-------------------------------------------------------------------------+
 596          | Read FPGA reg 6 to get PCI 0 FPGA reg information
 597          +-------------------------------------------------------------------------*/
 598         pci_clock_selection = in16(FPGA_REG16); /* was reg6 averifier */
 599
 600
 601         pci_clock_selection = pci_clock_selection & FPGA_REG16_PCI0_CLK_MASK;
 602
 603         switch (pci_clock_selection) {
 604                 case FPGA_REG16_PCI0_CLK_133_33:
 605                         pci_period = PERIOD_133_33MHZ;
 606                         break;
 607                 case FPGA_REG16_PCI0_CLK_100:
 608                         pci_period = PERIOD_100_00MHZ;
 609                         break;
 610                 case FPGA_REG16_PCI0_CLK_66_66:
 611                         pci_period = PERIOD_66_66MHZ;
 612                         break;
 613                 default:
 614                         pci_period = PERIOD_33_33MHZ;;
 615                         break;
 616         }
 617
 618         return(pci_period);
 619 }
 620 #endif
 621
 622 ulong get_OPB_freq (void)
 623 {
 624
 625         sys_info_t sys_info;
 626         get_sys_info (&sys_info);
 627         return sys_info.freqOPB;
 628 }
 629
 630 #elif defined(CONFIG_XILINX_ML300)
 631 extern void get_sys_info (sys_info_t * sysInfo);
 632 extern ulong get_PCI_freq (void);
 633
 634 #elif defined(CONFIG_AP1000)
 635 void get_sys_info (sys_info_t * sysInfo) {
 636         sysInfo->freqProcessor = 240 * 1000 * 1000;
 637         sysInfo->freqPLB = 80 * 1000 * 1000;
 638         sysInfo->freqPCI = 33 * 1000 * 1000;
 639 }
 640
 641 #elif defined(CONFIG_405)
 642
 643 void get_sys_info (sys_info_t * sysInfo) {
 644
 645         sysInfo->freqVCOMhz=3125000;
 646         sysInfo->freqProcessor=12*1000*1000;
 647         sysInfo->freqPLB=50*1000*1000;
 648         sysInfo->freqPCI=66*1000*1000;
 649
 650 }
 651
 652 #elif defined(CONFIG_405EP)
 653 void get_sys_info (PPC405_SYS_INFO * sysInfo)
 654 {
 655         unsigned long pllmr0;
 656         unsigned long pllmr1;
 657         unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
 658         unsigned long m;
 659         unsigned long pllmr0_ccdv;
 660
 661         /*
 662          * Read PLL Mode registers
 663          */
 664         pllmr0 = mfdcr (cpc0_pllmr0);
 665         pllmr1 = mfdcr (cpc0_pllmr1);
 666
 667         /*
 668          * Determine forward divider A
 669          */
 670         sysInfo->pllFwdDiv = 8 - ((pllmr1 & PLLMR1_FWDVA_MASK) >> 16);
 671
 672         /*
 673          * Determine forward divider B (should be equal to A)
 674          */
 675         sysInfo->pllFwdDivB = 8 - ((pllmr1 & PLLMR1_FWDVB_MASK) >> 12);
 676
 677         /*
 678          * Determine FBK_DIV.
 679          */
 680         sysInfo->pllFbkDiv = ((pllmr1 & PLLMR1_FBMUL_MASK) >> 20);
 681         if (sysInfo->pllFbkDiv == 0) {
 682                 sysInfo->pllFbkDiv = 16;
 683         }
 684
 685         /*
 686          * Determine PLB_DIV.
 687          */
 688         sysInfo->pllPlbDiv = ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) >> 16) + 1;
 689
 690         /*
 691          * Determine PCI_DIV.
 692          */
 693         sysInfo->pllPciDiv = (pllmr0 & PLLMR0_PCI_TO_PLB_MASK) + 1;
 694
 695         /*
 696          * Determine EXTBUS_DIV.
 697          */
 698         sysInfo->pllExtBusDiv = ((pllmr0 & PLLMR0_EXB_TO_PLB_MASK) >> 8) + 2;
 699
 700         /*
 701          * Determine OPB_DIV.
 702          */
 703         sysInfo->pllOpbDiv = ((pllmr0 & PLLMR0_OPB_TO_PLB_MASK) >> 12) + 1;
 704
 705         /*
 706          * Determine the M factor
 707          */
 708         m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB;
 709
 710         /*
 711          * Determine VCO clock frequency
 712          */
 713         sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
 714                 (unsigned long long)sysClkPeriodPs;
 715
 716         /*
 717          * Determine CPU clock frequency
 718          */
 719         pllmr0_ccdv = ((pllmr0 & PLLMR0_CPU_DIV_MASK) >> 20) + 1;
 720         if (pllmr1 & PLLMR1_SSCS_MASK) {
 721                 /*
 722                  * This is true if FWDVA == FWDVB:
 723                  * sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv)
 724                  *      / pllmr0_ccdv;
 725                  */
 726                 sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv * sysInfo->pllFwdDivB)
 727                         / sysInfo->pllFwdDiv / pllmr0_ccdv;
 728         } else {
 729                 sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ / pllmr0_ccdv;
 730         }
 731
 732         /*
 733          * Determine PLB clock frequency
 734          */
 735         sysInfo->freqPLB = sysInfo->freqProcessor / sysInfo->pllPlbDiv;
 736 }
 737
 738
 739 /********************************************
 740  * get_OPB_freq
 741  * return OPB bus freq in Hz
 742  *********************************************/
 743 ulong get_OPB_freq (void)
 744 {
 745         ulong val = 0;
 746
 747         PPC405_SYS_INFO sys_info;
 748
 749         get_sys_info (&sys_info);
 750         val = sys_info.freqPLB / sys_info.pllOpbDiv;
 751
 752         return val;
 753 }
 754
 755
 756 /********************************************
 757  * get_PCI_freq
 758  * return PCI bus freq in Hz
 759  *********************************************/
 760 ulong get_PCI_freq (void)
 761 {
 762         ulong val;
 763         PPC405_SYS_INFO sys_info;
 764
 765         get_sys_info (&sys_info);
 766         val = sys_info.freqPLB / sys_info.pllPciDiv;
 767         return val;
 768 }
 769
 770 #endif
 771
 772 int get_clocks (void)
 773 {
 774 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405) || defined(CONFIG_405EP)
 775         sys_info_t sys_info;
 776
 777         get_sys_info (&sys_info);
 778         gd->cpu_clk = sys_info.freqProcessor;
 779         gd->bus_clk = sys_info.freqPLB;
 780
 781 #endif  /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */
 782
 783 #ifdef CONFIG_IOP480
 784         gd->cpu_clk = 66000000;
 785         gd->bus_clk = 66000000;
 786 #endif
 787         return (0);
 788 }
 789
 790
 791 /********************************************
 792  * get_bus_freq
 793  * return PLB bus freq in Hz
 794  *********************************************/
 795 ulong get_bus_freq (ulong dummy)
 796 {
 797         ulong val;
 798
 799 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_440) || defined(CONFIG_405EP)
 800         sys_info_t sys_info;
 801
 802         get_sys_info (&sys_info);
 803         val = sys_info.freqPLB;
 804
 805 #elif defined(CONFIG_IOP480)
 806
 807         val = 66;
 808
 809 #else
 810 # error get_bus_freq() not implemented
 811 #endif
 812
 813         return val;
 814 }