cpu/ppc4xx/speed.c

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <ppc_asm.tmpl>
  26 #include <ppc4xx.h>
  27 #include <asm/processor.h>
  28
  29 /* ------------------------------------------------------------------------- */
  30
  31 #define ONE_BILLION        1000000000
  32
  33
  34 #if defined(CONFIG_405GP) || defined(CONFIG_405CR)
  35
  36 void get_sys_info (PPC405_SYS_INFO * sysInfo)
  37 {
  38         unsigned long pllmr;
  39         unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
  40         uint pvr = get_pvr();
  41         unsigned long psr;
  42         unsigned long m;
  43
  44         /*
  45          * Read PLL Mode register
  46          */
  47         pllmr = mfdcr (pllmd);
  48
  49         /*
  50          * Read Pin Strapping register
  51          */
  52         psr = mfdcr (strap);
  53
  54         /*
  55          * Determine FWD_DIV.
  56          */
  57         sysInfo->pllFwdDiv = 8 - ((pllmr & PLLMR_FWD_DIV_MASK) >> 29);
  58
  59         /*
  60          * Determine FBK_DIV.
  61          */
  62         sysInfo->pllFbkDiv = ((pllmr & PLLMR_FB_DIV_MASK) >> 25);
  63         if (sysInfo->pllFbkDiv == 0) {
  64                 sysInfo->pllFbkDiv = 16;
  65         }
  66
  67         /*
  68          * Determine PLB_DIV.
  69          */
  70         sysInfo->pllPlbDiv = ((pllmr & PLLMR_CPU_TO_PLB_MASK) >> 17) + 1;
  71
  72         /*
  73          * Determine PCI_DIV.
  74          */
  75         sysInfo->pllPciDiv = ((pllmr & PLLMR_PCI_TO_PLB_MASK) >> 13) + 1;
  76
  77         /*
  78          * Determine EXTBUS_DIV.
  79          */
  80         sysInfo->pllExtBusDiv = ((pllmr & PLLMR_EXB_TO_PLB_MASK) >> 11) + 2;
  81
  82         /*
  83          * Determine OPB_DIV.
  84          */
  85         sysInfo->pllOpbDiv = ((pllmr & PLLMR_OPB_TO_PLB_MASK) >> 15) + 1;
  86
  87         /*
  88          * Check if PPC405GPr used (mask minor revision field)
  89          */
  90         if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
  91                 /*
  92                  * Determine FWD_DIV B (only PPC405GPr with new mode strapping).
  93                  */
  94                 sysInfo->pllFwdDivB = 8 - (pllmr & PLLMR_FWDB_DIV_MASK);
  95
  96                 /*
  97                  * Determine factor m depending on PLL feedback clock source
  98                  */
  99                 if (!(psr & PSR_PCI_ASYNC_EN)) {
 100                         if (psr & PSR_NEW_MODE_EN) {
 101                                 /*
 102                                  * sync pci clock used as feedback (new mode)
 103                                  */
 104                                 m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllPciDiv;
 105                         } else {
 106                                 /*
 107                                  * sync pci clock used as feedback (legacy mode)
 108                                  */
 109                                 m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllPciDiv;
 110                         }
 111                 } else if (psr & PSR_NEW_MODE_EN) {
 112                         if (psr & PSR_PERCLK_SYNC_MODE_EN) {
 113                                 /*
 114                                  * PerClk used as feedback (new mode)
 115                                  */
 116                                 m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllExtBusDiv;
 117                         } else {
 118                                 /*
 119                                  * CPU clock used as feedback (new mode)
 120                                  */
 121                                 m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv;
 122                         }
 123                 } else if (sysInfo->pllExtBusDiv == sysInfo->pllFbkDiv) {
 124                         /*
 125                          * PerClk used as feedback (legacy mode)
 126                          */
 127                         m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllExtBusDiv;
 128                 } else {
 129                         /*
 130                          * PLB clock used as feedback (legacy mode)
 131                          */
 132                         m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv;
 133                 }
 134
 135                 sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
 136                         (unsigned long long)sysClkPeriodPs;
 137                 sysInfo->freqProcessor = sysInfo->freqVCOHz / sysInfo->pllFwdDiv;
 138                 sysInfo->freqPLB = sysInfo->freqVCOHz / (sysInfo->pllFwdDivB * sysInfo->pllPlbDiv);
 139         } else {
 140                 /*
 141                  * Check pllFwdDiv to see if running in bypass mode where the CPU speed
 142                  * is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO
 143                  * to make sure it is within the proper range.
 144                  *    spec:    VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV
 145                  * Note freqVCO is calculated in Mhz to avoid errors introduced by rounding.
 146                  */
 147                 if (sysInfo->pllFwdDiv == 1) {
 148                         sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ;
 149                         sysInfo->freqPLB = CONFIG_SYS_CLK_FREQ / sysInfo->pllPlbDiv;
 150                 } else {
 151                         sysInfo->freqVCOHz = ( 1000000000000LL *
 152                                                (unsigned long long)sysInfo->pllFwdDiv *
 153                                                (unsigned long long)sysInfo->pllFbkDiv *
 154                                                (unsigned long long)sysInfo->pllPlbDiv
 155                                 ) / (unsigned long long)sysClkPeriodPs;
 156                         sysInfo->freqPLB = (ONE_BILLION / ((sysClkPeriodPs * 10) /
 157                                                            sysInfo->pllFbkDiv)) * 10000;
 158                         sysInfo->freqProcessor = sysInfo->freqPLB * sysInfo->pllPlbDiv;
 159                 }
 160         }
 161 }
 162
 163
 164 /********************************************
 165  * get_OPB_freq
 166  * return OPB bus freq in Hz
 167  *********************************************/
 168 ulong get_OPB_freq (void)
 169 {
 170         ulong val = 0;
 171
 172         PPC405_SYS_INFO sys_info;
 173
 174         get_sys_info (&sys_info);
 175         val = sys_info.freqPLB / sys_info.pllOpbDiv;
 176
 177         return val;
 178 }
 179
 180
 181 /********************************************
 182  * get_PCI_freq
 183  * return PCI bus freq in Hz
 184  *********************************************/
 185 ulong get_PCI_freq (void)
 186 {
 187         ulong val;
 188         PPC405_SYS_INFO sys_info;
 189
 190         get_sys_info (&sys_info);
 191         val = sys_info.freqPLB / sys_info.pllPciDiv;
 192         return val;
 193 }
 194
 195
 196 #elif defined(CONFIG_440)
 197
 198 #if  defined(CONFIG_440EP) || defined(CONFIG_440GR)
 199 void get_sys_info (sys_info_t *sysInfo)
 200 {
 201         unsigned long temp;
 202         unsigned long reg;
 203         unsigned long lfdiv;
 204         unsigned long m;
 205         unsigned long prbdv0;
 206         /*
 207           WARNING: ASSUMES the following:
 208           ENG=1
 209           PRADV0=1
 210           PRBDV0=1
 211         */
 212
 213         /* Decode CPR0_PLLD0 for divisors */
 214         mfclk(clk_plld, reg);
 215         temp = (reg & PLLD_FWDVA_MASK) >> 16;
 216         sysInfo->pllFwdDivA = temp ? temp : 16;
 217         temp = (reg & PLLD_FWDVB_MASK) >> 8;
 218         sysInfo->pllFwdDivB = temp ? temp: 8 ;
 219         temp = (reg & PLLD_FBDV_MASK) >> 24;
 220         sysInfo->pllFbkDiv = temp ? temp : 32;
 221         lfdiv = reg & PLLD_LFBDV_MASK;
 222
 223         mfclk(clk_opbd, reg);
 224         temp = (reg & OPBDDV_MASK) >> 24;
 225         sysInfo->pllOpbDiv = temp ? temp : 4;
 226
 227         mfclk(clk_perd, reg);
 228         temp = (reg & PERDV_MASK) >> 24;
 229         sysInfo->pllExtBusDiv = temp ? temp : 8;
 230
 231         mfclk(clk_primbd, reg);
 232         temp = (reg & PRBDV_MASK) >> 24;
 233         prbdv0 = temp ? temp : 8;
 234
 235         mfclk(clk_spcid, reg);
 236         temp = (reg & SPCID_MASK) >> 24;
 237         sysInfo->pllPciDiv = temp ? temp : 4;
 238
 239         /* Calculate 'M' based on feedback source */
 240         mfsdr(sdr_sdstp0, reg);
 241         temp = (reg & PLLSYS0_SEL_MASK) >> 27;
 242         if (temp == 0) { /* PLL output */
 243                 /* Figure which pll to use */
 244                 mfclk(clk_pllc, reg);
 245                 temp = (reg & PLLC_SRC_MASK) >> 29;
 246                 if (!temp) /* PLLOUTA */
 247                         m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
 248                 else       /* PLLOUTB */
 249                         m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivB;
 250         }
 251         else if (temp == 1) /* CPU output */
 252                 m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
 253         else /* PerClk */
 254                 m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
 255
 256         /* Now calculate the individual clocks */
 257         sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
 258         sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
 259         sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
 260         sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
 261         sysInfo->freqEPB = sysInfo->freqPLB/sysInfo->pllExtBusDiv;
 262         sysInfo->freqPCI = sysInfo->freqPLB/sysInfo->pllPciDiv;
 263
 264         /* Figure which timer source to use */
 265         if (mfspr(ccr1) & 0x0080) { /* External Clock, assume same as SYS_CLK */
 266                 temp = sysInfo->freqProcessor / 2;  /* Max extern clock speed */
 267                 if (CONFIG_SYS_CLK_FREQ > temp)
 268                         sysInfo->freqTmrClk = temp;
 269                 else
 270                         sysInfo->freqTmrClk = CONFIG_SYS_CLK_FREQ;
 271         }
 272         else  /* Internal clock */
 273                 sysInfo->freqTmrClk = sysInfo->freqProcessor;
 274 }
 275 /********************************************
 276  * get_PCI_freq
 277  * return PCI bus freq in Hz
 278  *********************************************/
 279 ulong get_PCI_freq (void)
 280 {
 281         sys_info_t sys_info;
 282         get_sys_info (&sys_info);
 283         return sys_info.freqPCI;
 284 }
 285
 286 #elif !defined(CONFIG_440GX)
 287 void get_sys_info (sys_info_t * sysInfo)
 288 {
 289         unsigned long strp0;
 290         unsigned long temp;
 291         unsigned long m;
 292
 293         /* Extract configured divisors */
 294         strp0 = mfdcr( cpc0_strp0 );
 295         sysInfo->pllFwdDivA = 8 - ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 15);
 296         sysInfo->pllFwdDivB = 8 - ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 12);
 297         temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 18;
 298         sysInfo->pllFbkDiv = temp ? temp : 16;
 299         sysInfo->pllOpbDiv = 1 + ((strp0 & PLLSYS0_OPB_DIV_MASK) >> 10);
 300         sysInfo->pllExtBusDiv = 1 + ((strp0 & PLLSYS0_EPB_DIV_MASK) >> 8);
 301
 302         /* Calculate 'M' based on feedback source */
 303         if( strp0 & PLLSYS0_EXTSL_MASK )
 304                 m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
 305         else
 306                 m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
 307
 308         /* Now calculate the individual clocks */
 309         sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
 310         sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
 311         sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB;
 312         if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */
 313                 sysInfo->freqPLB >>= 1;
 314         sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
 315         sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
 316
 317 }
 318 #else
 319 void get_sys_info (sys_info_t * sysInfo)
 320 {
 321         unsigned long strp0;
 322         unsigned long strp1;
 323         unsigned long temp;
 324         unsigned long temp1;
 325         unsigned long lfdiv;
 326         unsigned long m;
 327         unsigned long prbdv0;
 328
 329         /* Extract configured divisors */
 330         mfsdr( sdr_sdstp0,strp0 );
 331         mfsdr( sdr_sdstp1,strp1 );
 332
 333         temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 8);
 334         sysInfo->pllFwdDivA = temp ? temp : 16 ;
 335         temp = ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 5);
 336         sysInfo->pllFwdDivB = temp ? temp: 8 ;
 337         temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 12;
 338         sysInfo->pllFbkDiv = temp ? temp : 32;
 339         temp = (strp0 & PLLSYS0_OPB_DIV_MASK);
 340         sysInfo->pllOpbDiv = temp ? temp : 4;
 341         temp = (strp1 & PLLSYS1_PERCLK_DIV_MASK) >> 24;
 342         sysInfo->pllExtBusDiv = temp ? temp : 4;
 343         prbdv0 = (strp0 >> 2) & 0x7;
 344
 345         /* Calculate 'M' based on feedback source */
 346         temp = (strp0 & PLLSYS0_SEL_MASK) >> 27;
 347         temp1 = (strp1 & PLLSYS1_LF_DIV_MASK) >> 26;
 348         lfdiv = temp1 ? temp1 : 64;
 349         if (temp == 0) { /* PLL output */
 350                 /* Figure which pll to use */
 351                 temp = (strp0 & PLLSYS0_SRC_MASK) >> 30;
 352                 if (!temp)
 353                         m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
 354                 else
 355                         m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivB;
 356         }
 357         else if (temp == 1) /* CPU output */
 358                 m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
 359         else /* PerClk */
 360                 m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
 361
 362         /* Now calculate the individual clocks */
 363         sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
 364         sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
 365         sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
 366         sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
 367         sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
 368
 369 }
 370 #endif
 371
 372 ulong get_OPB_freq (void)
 373 {
 374
 375         sys_info_t sys_info;
 376         get_sys_info (&sys_info);
 377         return sys_info.freqOPB;
 378 }
 379
 380 #elif defined(CONFIG_XILINX_ML300)
 381 extern void get_sys_info (sys_info_t * sysInfo);
 382 extern ulong get_PCI_freq (void);
 383
 384 #elif defined(CONFIG_405)
 385
 386 void get_sys_info (sys_info_t * sysInfo) {
 387
 388         sysInfo->freqVCOMhz=3125000;
 389         sysInfo->freqProcessor=12*1000*1000;
 390         sysInfo->freqPLB=50*1000*1000;
 391         sysInfo->freqPCI=66*1000*1000;
 392
 393 }
 394
 395 #elif defined(CONFIG_405EP)
 396 void get_sys_info (PPC405_SYS_INFO * sysInfo)
 397 {
 398         unsigned long pllmr0;
 399         unsigned long pllmr1;
 400         unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
 401         unsigned long m;
 402         unsigned long pllmr0_ccdv;
 403
 404         /*
 405          * Read PLL Mode registers
 406          */
 407         pllmr0 = mfdcr (cpc0_pllmr0);
 408         pllmr1 = mfdcr (cpc0_pllmr1);
 409
 410         /*
 411          * Determine forward divider A
 412          */
 413         sysInfo->pllFwdDiv = 8 - ((pllmr1 & PLLMR1_FWDVA_MASK) >> 16);
 414
 415         /*
 416          * Determine forward divider B (should be equal to A)
 417          */
 418         sysInfo->pllFwdDivB = 8 - ((pllmr1 & PLLMR1_FWDVB_MASK) >> 12);
 419
 420         /*
 421          * Determine FBK_DIV.
 422          */
 423         sysInfo->pllFbkDiv = ((pllmr1 & PLLMR1_FBMUL_MASK) >> 20);
 424         if (sysInfo->pllFbkDiv == 0) {
 425                 sysInfo->pllFbkDiv = 16;
 426         }
 427
 428         /*
 429          * Determine PLB_DIV.
 430          */
 431         sysInfo->pllPlbDiv = ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) >> 16) + 1;
 432
 433         /*
 434          * Determine PCI_DIV.
 435          */
 436         sysInfo->pllPciDiv = (pllmr0 & PLLMR0_PCI_TO_PLB_MASK) + 1;
 437
 438         /*
 439          * Determine EXTBUS_DIV.
 440          */
 441         sysInfo->pllExtBusDiv = ((pllmr0 & PLLMR0_EXB_TO_PLB_MASK) >> 8) + 2;
 442
 443         /*
 444          * Determine OPB_DIV.
 445          */
 446         sysInfo->pllOpbDiv = ((pllmr0 & PLLMR0_OPB_TO_PLB_MASK) >> 12) + 1;
 447
 448         /*
 449          * Determine the M factor
 450          */
 451         m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB;
 452
 453         /*
 454          * Determine VCO clock frequency
 455          */
 456         sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
 457                 (unsigned long long)sysClkPeriodPs;
 458
 459         /*
 460          * Determine CPU clock frequency
 461          */
 462         pllmr0_ccdv = ((pllmr0 & PLLMR0_CPU_DIV_MASK) >> 20) + 1;
 463         if (pllmr1 & PLLMR1_SSCS_MASK) {
 464                 /*
 465                  * This is true if FWDVA == FWDVB:
 466                  * sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv)
 467                  *      / pllmr0_ccdv;
 468                  */
 469                 sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv * sysInfo->pllFwdDivB)
 470                         / sysInfo->pllFwdDiv / pllmr0_ccdv;
 471         } else {
 472                 sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ / pllmr0_ccdv;
 473         }
 474
 475         /*
 476          * Determine PLB clock frequency
 477          */
 478         sysInfo->freqPLB = sysInfo->freqProcessor / sysInfo->pllPlbDiv;
 479 }
 480
 481
 482 /********************************************
 483  * get_OPB_freq
 484  * return OPB bus freq in Hz
 485  *********************************************/
 486 ulong get_OPB_freq (void)
 487 {
 488         ulong val = 0;
 489
 490         PPC405_SYS_INFO sys_info;
 491
 492         get_sys_info (&sys_info);
 493         val = sys_info.freqPLB / sys_info.pllOpbDiv;
 494
 495         return val;
 496 }
 497
 498
 499 /********************************************
 500  * get_PCI_freq
 501  * return PCI bus freq in Hz
 502  *********************************************/
 503 ulong get_PCI_freq (void)
 504 {
 505         ulong val;
 506         PPC405_SYS_INFO sys_info;
 507
 508         get_sys_info (&sys_info);
 509         val = sys_info.freqPLB / sys_info.pllPciDiv;
 510         return val;
 511 }
 512
 513 #endif
 514
 515 int get_clocks (void)
 516 {
 517 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405) || defined(CONFIG_405EP)
 518         DECLARE_GLOBAL_DATA_PTR;
 519
 520         sys_info_t sys_info;
 521
 522         get_sys_info (&sys_info);
 523         gd->cpu_clk = sys_info.freqProcessor;
 524         gd->bus_clk = sys_info.freqPLB;
 525
 526 #endif  /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */
 527
 528 #ifdef CONFIG_IOP480
 529         DECLARE_GLOBAL_DATA_PTR;
 530
 531         gd->cpu_clk = 66000000;
 532         gd->bus_clk = 66000000;
 533 #endif
 534         return (0);
 535 }
 536
 537
 538 /********************************************
 539  * get_bus_freq
 540  * return PLB bus freq in Hz
 541  *********************************************/
 542 ulong get_bus_freq (ulong dummy)
 543 {
 544         ulong val;
 545
 546 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_440) || defined(CONFIG_405EP)
 547         sys_info_t sys_info;
 548
 549         get_sys_info (&sys_info);
 550         val = sys_info.freqPLB;
 551
 552 #elif defined(CONFIG_IOP480)
 553
 554         val = 66;
 555
 556 #else
 557 # error get_bus_freq() not implemented
 558 #endif
 559
 560         return val;
 561 }