cpu/ppc4xx/speed.c

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <ppc_asm.tmpl>
  26 #include <ppc4xx.h>
  27 #include <asm/processor.h>
  28
  29 /* ------------------------------------------------------------------------- */
  30
  31 #define ONE_BILLION        1000000000
  32
  33
  34 #if defined(CONFIG_405GP) || defined(CONFIG_405CR)
  35
  36 void get_sys_info (PPC405_SYS_INFO * sysInfo)
  37 {
  38         unsigned long pllmr;
  39         unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
  40         uint pvr = get_pvr();
  41         unsigned long psr;
  42         unsigned long m;
  43
  44         /*
  45          * Read PLL Mode register
  46          */
  47         pllmr = mfdcr (pllmd);
  48
  49         /*
  50          * Read Pin Strapping register
  51          */
  52         psr = mfdcr (strap);
  53
  54         /*
  55          * Determine FWD_DIV.
  56          */
  57         sysInfo->pllFwdDiv = 8 - ((pllmr & PLLMR_FWD_DIV_MASK) >> 29);
  58
  59         /*
  60          * Determine FBK_DIV.
  61          */
  62         sysInfo->pllFbkDiv = ((pllmr & PLLMR_FB_DIV_MASK) >> 25);
  63         if (sysInfo->pllFbkDiv == 0) {
  64                 sysInfo->pllFbkDiv = 16;
  65         }
  66
  67         /*
  68          * Determine PLB_DIV.
  69          */
  70         sysInfo->pllPlbDiv = ((pllmr & PLLMR_CPU_TO_PLB_MASK) >> 17) + 1;
  71
  72         /*
  73          * Determine PCI_DIV.
  74          */
  75         sysInfo->pllPciDiv = ((pllmr & PLLMR_PCI_TO_PLB_MASK) >> 13) + 1;
  76
  77         /*
  78          * Determine EXTBUS_DIV.
  79          */
  80         sysInfo->pllExtBusDiv = ((pllmr & PLLMR_EXB_TO_PLB_MASK) >> 11) + 2;
  81
  82         /*
  83          * Determine OPB_DIV.
  84          */
  85         sysInfo->pllOpbDiv = ((pllmr & PLLMR_OPB_TO_PLB_MASK) >> 15) + 1;
  86
  87         /*
  88          * Check if PPC405GPr used (mask minor revision field)
  89          */
  90         if ((pvr & 0xfffffff0) == (PVR_405GPR_RB & 0xfffffff0)) {
  91                 /*
  92                  * Determine FWD_DIV B (only PPC405GPr with new mode strapping).
  93                  */
  94                 sysInfo->pllFwdDivB = 8 - (pllmr & PLLMR_FWDB_DIV_MASK);
  95
  96                 /*
  97                  * Determine factor m depending on PLL feedback clock source
  98                  */
  99                 if (!(psr & PSR_PCI_ASYNC_EN)) {
 100                         if (psr & PSR_NEW_MODE_EN) {
 101                                 /*
 102                                  * sync pci clock used as feedback (new mode)
 103                                  */
 104                                 m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllPciDiv;
 105                         } else {
 106                                 /*
 107                                  * sync pci clock used as feedback (legacy mode)
 108                                  */
 109                                 m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllPciDiv;
 110                         }
 111                 } else if (psr & PSR_NEW_MODE_EN) {
 112                         if (psr & PSR_PERCLK_SYNC_MODE_EN) {
 113                                 /*
 114                                  * PerClk used as feedback (new mode)
 115                                  */
 116                                 m = 1 * sysInfo->pllFwdDivB * 2 * sysInfo->pllExtBusDiv;
 117                         } else {
 118                                 /*
 119                                  * CPU clock used as feedback (new mode)
 120                                  */
 121                                 m = sysInfo->pllFbkDiv * sysInfo->pllFwdDiv;
 122                         }
 123                 } else if (sysInfo->pllExtBusDiv == sysInfo->pllFbkDiv) {
 124                         /*
 125                          * PerClk used as feedback (legacy mode)
 126                          */
 127                         m = 1 * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv * sysInfo->pllExtBusDiv;
 128                 } else {
 129                         /*
 130                          * PLB clock used as feedback (legacy mode)
 131                          */
 132                         m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB * sysInfo->pllPlbDiv;
 133                 }
 134
 135                 sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
 136                         (unsigned long long)sysClkPeriodPs;
 137                 sysInfo->freqProcessor = sysInfo->freqVCOHz / sysInfo->pllFwdDiv;
 138                 sysInfo->freqPLB = sysInfo->freqVCOHz / (sysInfo->pllFwdDivB * sysInfo->pllPlbDiv);
 139         } else {
 140                 /*
 141                  * Check pllFwdDiv to see if running in bypass mode where the CPU speed
 142                  * is equal to the 405GP SYS_CLK_FREQ. If not in bypass mode, check VCO
 143                  * to make sure it is within the proper range.
 144                  *    spec:    VCO = SYS_CLOCK x FBKDIV x PLBDIV x FWDDIV
 145                  * Note freqVCO is calculated in Mhz to avoid errors introduced by rounding.
 146                  */
 147                 if (sysInfo->pllFwdDiv == 1) {
 148                         sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ;
 149                         sysInfo->freqPLB = CONFIG_SYS_CLK_FREQ / sysInfo->pllPlbDiv;
 150                 } else {
 151                         sysInfo->freqVCOHz = ( 1000000000000LL *
 152                                                (unsigned long long)sysInfo->pllFwdDiv *
 153                                                (unsigned long long)sysInfo->pllFbkDiv *
 154                                                (unsigned long long)sysInfo->pllPlbDiv
 155                                 ) / (unsigned long long)sysClkPeriodPs;
 156                         sysInfo->freqPLB = (ONE_BILLION / ((sysClkPeriodPs * 10) /
 157                                                            sysInfo->pllFbkDiv)) * 10000;
 158                         sysInfo->freqProcessor = sysInfo->freqPLB * sysInfo->pllPlbDiv;
 159                 }
 160         }
 161 }
 162
 163
 164 /********************************************
 165  * get_OPB_freq
 166  * return OPB bus freq in Hz
 167  *********************************************/
 168 ulong get_OPB_freq (void)
 169 {
 170         ulong val = 0;
 171
 172         PPC405_SYS_INFO sys_info;
 173
 174         get_sys_info (&sys_info);
 175         val = sys_info.freqPLB / sys_info.pllOpbDiv;
 176
 177         return val;
 178 }
 179
 180
 181 /********************************************
 182  * get_PCI_freq
 183  * return PCI bus freq in Hz
 184  *********************************************/
 185 ulong get_PCI_freq (void)
 186 {
 187         ulong val;
 188         PPC405_SYS_INFO sys_info;
 189
 190         get_sys_info (&sys_info);
 191         val = sys_info.freqPLB / sys_info.pllPciDiv;
 192         return val;
 193 }
 194
 195
 196 #elif defined(CONFIG_440)
 197 #if !defined(CONFIG_440_GX)
 198 void get_sys_info (sys_info_t * sysInfo)
 199 {
 200         unsigned long strp0;
 201         unsigned long temp;
 202         unsigned long m;
 203
 204         /* Extract configured divisors */
 205         strp0 = mfdcr( cpc0_strp0 );
 206         sysInfo->pllFwdDivA = 8 - ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 15);
 207         sysInfo->pllFwdDivB = 8 - ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 12);
 208         temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 18;
 209         sysInfo->pllFbkDiv = temp ? temp : 16;
 210         sysInfo->pllOpbDiv = 1 + ((strp0 & PLLSYS0_OPB_DIV_MASK) >> 10);
 211         sysInfo->pllExtBusDiv = 1 + ((strp0 & PLLSYS0_EPB_DIV_MASK) >> 8);
 212
 213         /* Calculate 'M' based on feedback source */
 214         if( strp0 & PLLSYS0_EXTSL_MASK )
 215                 m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
 216         else
 217                 m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
 218
 219         /* Now calculate the individual clocks */
 220         sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
 221         sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
 222         sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB;
 223     if( get_pvr() == PVR_440GP_RB ) /* Rev B divs an extra 2 -- geez! */
 224         sysInfo->freqPLB >>= 1;
 225         sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
 226         sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
 227
 228 }
 229 #else
 230 void get_sys_info (sys_info_t * sysInfo)
 231 {
 232         unsigned long strp0;
 233         unsigned long strp1;
 234         unsigned long temp;
 235         unsigned long temp1;
 236         unsigned long lfdiv;
 237         unsigned long m;
 238         unsigned long prbdv0;
 239
 240         /* Extract configured divisors */
 241         mfsdr( sdr_sdstp0,strp0 );
 242         mfsdr( sdr_sdstp1,strp1 );
 243
 244         temp = ((strp0 & PLLSYS0_FWD_DIV_A_MASK) >> 8);
 245         sysInfo->pllFwdDivA = temp ? temp : 16 ;
 246         temp = ((strp0 & PLLSYS0_FWD_DIV_B_MASK) >> 5);
 247         sysInfo->pllFwdDivB = temp ? temp: 8 ;
 248         temp = (strp0 & PLLSYS0_FB_DIV_MASK) >> 12;
 249         sysInfo->pllFbkDiv = temp ? temp : 32;
 250         temp = (strp0 & PLLSYS0_OPB_DIV_MASK);
 251         sysInfo->pllOpbDiv = temp ? temp : 4;
 252         temp = (strp1 & PLLSYS1_PERCLK_DIV_MASK) >> 24;
 253         sysInfo->pllExtBusDiv = temp ? temp : 4;
 254         prbdv0 = (strp0 >> 2) & 0x7;
 255
 256         /* Calculate 'M' based on feedback source */
 257         temp = (strp0 & PLLSYS0_SEL_MASK) >> 27;
 258         temp1 = (strp1 & PLLSYS1_LF_DIV_MASK) >> 26;
 259         lfdiv = temp1 ? temp1 : 64;
 260         if (temp == 0) { /* PLL output */
 261                 /* Figure which pll to use */
 262                 temp = (strp0 & PLLSYS0_SRC_MASK) >> 30;
 263                 if (!temp)
 264                         m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivA;
 265                 else
 266                         m = sysInfo->pllFbkDiv * lfdiv * sysInfo->pllFwdDivB;
 267         }
 268         else if (temp == 1) /* CPU output */
 269                 m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivA;
 270         else /* PerClk */
 271                 m = sysInfo->pllExtBusDiv * sysInfo->pllOpbDiv * sysInfo->pllFwdDivB;
 272
 273         /* Now calculate the individual clocks */
 274         sysInfo->freqVCOMhz = (m * CONFIG_SYS_CLK_FREQ) + (m>>1);
 275         sysInfo->freqProcessor = sysInfo->freqVCOMhz/sysInfo->pllFwdDivA;
 276         sysInfo->freqPLB = sysInfo->freqVCOMhz/sysInfo->pllFwdDivB/prbdv0;
 277         sysInfo->freqOPB = sysInfo->freqPLB/sysInfo->pllOpbDiv;
 278         sysInfo->freqEPB = sysInfo->freqOPB/sysInfo->pllExtBusDiv;
 279
 280 }
 281 #endif
 282
 283 ulong get_OPB_freq (void)
 284 {
 285
 286         sys_info_t sys_info;
 287         get_sys_info (&sys_info);
 288         return sys_info.freqOPB;
 289 }
 290
 291 #elif defined(CONFIG_XILINX_ML300)
 292 extern void get_sys_info (sys_info_t * sysInfo);
 293 extern ulong get_PCI_freq (void);
 294
 295 #elif defined(CONFIG_405)
 296
 297 void get_sys_info (sys_info_t * sysInfo) {
 298
 299         sysInfo->freqVCOMhz=3125000;
 300         sysInfo->freqProcessor=12*1000*1000;
 301         sysInfo->freqPLB=50*1000*1000;
 302         sysInfo->freqPCI=66*1000*1000;
 303
 304 }
 305
 306 #elif defined(CONFIG_405EP)
 307 void get_sys_info (PPC405_SYS_INFO * sysInfo)
 308 {
 309         unsigned long pllmr0;
 310         unsigned long pllmr1;
 311         unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ / 1000);
 312         unsigned long m;
 313         unsigned long pllmr0_ccdv;
 314
 315         /*
 316          * Read PLL Mode registers
 317          */
 318         pllmr0 = mfdcr (cpc0_pllmr0);
 319         pllmr1 = mfdcr (cpc0_pllmr1);
 320
 321         /*
 322          * Determine forward divider A
 323          */
 324         sysInfo->pllFwdDiv = 8 - ((pllmr1 & PLLMR1_FWDVA_MASK) >> 16);
 325
 326         /*
 327          * Determine forward divider B (should be equal to A)
 328          */
 329         sysInfo->pllFwdDivB = 8 - ((pllmr1 & PLLMR1_FWDVB_MASK) >> 12);
 330
 331         /*
 332          * Determine FBK_DIV.
 333          */
 334         sysInfo->pllFbkDiv = ((pllmr1 & PLLMR1_FBMUL_MASK) >> 20);
 335         if (sysInfo->pllFbkDiv == 0) {
 336                 sysInfo->pllFbkDiv = 16;
 337         }
 338
 339         /*
 340          * Determine PLB_DIV.
 341          */
 342         sysInfo->pllPlbDiv = ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) >> 16) + 1;
 343
 344         /*
 345          * Determine PCI_DIV.
 346          */
 347         sysInfo->pllPciDiv = (pllmr0 & PLLMR0_PCI_TO_PLB_MASK) + 1;
 348
 349         /*
 350          * Determine EXTBUS_DIV.
 351          */
 352         sysInfo->pllExtBusDiv = ((pllmr0 & PLLMR0_EXB_TO_PLB_MASK) >> 8) + 2;
 353
 354         /*
 355          * Determine OPB_DIV.
 356          */
 357         sysInfo->pllOpbDiv = ((pllmr0 & PLLMR0_OPB_TO_PLB_MASK) >> 12) + 1;
 358
 359         /*
 360          * Determine the M factor
 361          */
 362         m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB;
 363
 364         /*
 365          * Determine VCO clock frequency
 366          */
 367         sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) /
 368                 (unsigned long long)sysClkPeriodPs;
 369
 370         /*
 371          * Determine CPU clock frequency
 372          */
 373         pllmr0_ccdv = ((pllmr0 & PLLMR0_CPU_DIV_MASK) >> 20) + 1;
 374         if (pllmr1 & PLLMR1_SSCS_MASK) {
 375                 /*
 376                  * This is true if FWDVA == FWDVB:
 377                  * sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv)
 378                  *      / pllmr0_ccdv;
 379                  */
 380                 sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv * sysInfo->pllFwdDivB)
 381                         / sysInfo->pllFwdDiv / pllmr0_ccdv;
 382         } else {
 383                 sysInfo->freqProcessor = CONFIG_SYS_CLK_FREQ / pllmr0_ccdv;
 384         }
 385
 386         /*
 387          * Determine PLB clock frequency
 388          */
 389         sysInfo->freqPLB = sysInfo->freqProcessor / sysInfo->pllPlbDiv;
 390 }
 391
 392
 393 /********************************************
 394  * get_OPB_freq
 395  * return OPB bus freq in Hz
 396  *********************************************/
 397 ulong get_OPB_freq (void)
 398 {
 399         ulong val = 0;
 400
 401         PPC405_SYS_INFO sys_info;
 402
 403         get_sys_info (&sys_info);
 404         val = sys_info.freqPLB / sys_info.pllOpbDiv;
 405
 406         return val;
 407 }
 408
 409
 410 /********************************************
 411  * get_PCI_freq
 412  * return PCI bus freq in Hz
 413  *********************************************/
 414 ulong get_PCI_freq (void)
 415 {
 416         ulong val;
 417         PPC405_SYS_INFO sys_info;
 418
 419         get_sys_info (&sys_info);
 420         val = sys_info.freqPLB / sys_info.pllPciDiv;
 421         return val;
 422 }
 423
 424 #endif
 425
 426 int get_clocks (void)
 427 {
 428 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405) || defined(CONFIG_405EP)
 429         DECLARE_GLOBAL_DATA_PTR;
 430
 431         sys_info_t sys_info;
 432
 433         get_sys_info (&sys_info);
 434         gd->cpu_clk = sys_info.freqProcessor;
 435         gd->bus_clk = sys_info.freqPLB;
 436
 437 #endif  /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */
 438
 439 #ifdef CONFIG_IOP480
 440         DECLARE_GLOBAL_DATA_PTR;
 441
 442         gd->cpu_clk = 66000000;
 443         gd->bus_clk = 66000000;
 444 #endif
 445         return (0);
 446 }
 447
 448
 449 /********************************************
 450  * get_bus_freq
 451  * return PLB bus freq in Hz
 452  *********************************************/
 453 ulong get_bus_freq (ulong dummy)
 454 {
 455         ulong val;
 456
 457 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_440) || defined(CONFIG_405EP)
 458         sys_info_t sys_info;
 459
 460         get_sys_info (&sys_info);
 461         val = sys_info.freqPLB;
 462
 463 #elif defined(CONFIG_IOP480)
 464
 465         val = 66;
 466
 467 #else
 468 # error get_bus_freq() not implemented
 469 #endif
 470
 471         return val;
 472 }