cpu/ppc4xx/spd_sdram.c

   1 /*
   2  * (C) Copyright 2001
   3  * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
   4  *
   5  * Based on code by:
   6  *
   7  * Kenneth Johansson ,Ericsson AB.
   8  * kenneth.johansson@etx.ericsson.se
   9  *
  10  * hacked up by bill hunter. fixed so we could run before
  11  * serial_init and console_init. previous version avoided this by
  12  * running out of cache memory during serial/console init, then running
  13  * this code later.
  14  *
  15  * (C) Copyright 2002
  16  * Jun Gu, Artesyn Technology, jung@artesyncp.com
  17  * Support for IBM 440 based on OpenBIOS draminit.c from IBM.
  18  *
  19  * See file CREDITS for list of people who contributed to this
  20  * project.
  21  *
  22  * This program is free software; you can redistribute it and/or
  23  * modify it under the terms of the GNU General Public License as
  24  * published by the Free Software Foundation; either version 2 of
  25  * the License, or (at your option) any later version.
  26  *
  27  * This program is distributed in the hope that it will be useful,
  28  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  29  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  30  * GNU General Public License for more details.
  31  *
  32  * You should have received a copy of the GNU General Public License
  33  * along with this program; if not, write to the Free Software
  34  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  35  * MA 02111-1307 USA
  36  */
  37
  38 #include <common.h>
  39 #include <asm/processor.h>
  40 #include <i2c.h>
  41 #include <ppc4xx.h>
  42
  43 #ifdef CONFIG_SPD_EEPROM
  44
  45 /*
  46  * Set default values
  47  */
  48 #ifndef CFG_I2C_SPEED
  49 #define CFG_I2C_SPEED   50000
  50 #endif
  51
  52 #ifndef CFG_I2C_SLAVE
  53 #define CFG_I2C_SLAVE   0xFE
  54 #endif
  55
  56 #ifndef  CONFIG_440              /* for 405 WALNUT board */
  57
  58 #define  SDRAM0_CFG_DCE          0x80000000
  59 #define  SDRAM0_CFG_SRE          0x40000000
  60 #define  SDRAM0_CFG_PME          0x20000000
  61 #define  SDRAM0_CFG_MEMCHK       0x10000000
  62 #define  SDRAM0_CFG_REGEN        0x08000000
  63 #define  SDRAM0_CFG_ECCDD        0x00400000
  64 #define  SDRAM0_CFG_EMDULR       0x00200000
  65 #define  SDRAM0_CFG_DRW_SHIFT    (31-6)
  66 #define  SDRAM0_CFG_BRPF_SHIFT   (31-8)
  67
  68 #define  SDRAM0_TR_CASL_SHIFT    (31-8)
  69 #define  SDRAM0_TR_PTA_SHIFT     (31-13)
  70 #define  SDRAM0_TR_CTP_SHIFT     (31-15)
  71 #define  SDRAM0_TR_LDF_SHIFT     (31-17)
  72 #define  SDRAM0_TR_RFTA_SHIFT    (31-29)
  73 #define  SDRAM0_TR_RCD_SHIFT     (31-31)
  74
  75 #define  SDRAM0_RTR_SHIFT        (31-15)
  76 #define  SDRAM0_ECCCFG_SHIFT     (31-11)
  77
  78 /* SDRAM0_CFG enable macro  */
  79 #define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
  80
  81 #define SDRAM0_BXCR_SZ_MASK  0x000e0000
  82 #define SDRAM0_BXCR_AM_MASK  0x0000e000
  83
  84 #define SDRAM0_BXCR_SZ_SHIFT (31-14)
  85 #define SDRAM0_BXCR_AM_SHIFT (31-18)
  86
  87 #define SDRAM0_BXCR_SZ(x)  ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
  88 #define SDRAM0_BXCR_AM(x)  ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
  89
  90 #ifdef CONFIG_SPDDRAM_SILENT
  91 # define SPD_ERR(x) do { return 0; } while (0)
  92 #else
  93 # define SPD_ERR(x) do { printf(x); return(0); } while (0)
  94 #endif
  95
  96 #define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
  97
  98 /* function prototypes */
  99 int spd_read(uint addr);
 100
 101
 102 /*
 103  * This function is reading data from the DIMM module EEPROM over the SPD bus
 104  * and uses that to program the sdram controller.
 105  *
 106  * This works on boards that has the same schematics that the IBM walnut has.
 107  *
 108  * Input: null for default I2C spd functions or a pointer to a custom function
 109  * returning spd_data.
 110  */
 111
 112 long int spd_sdram(int(read_spd)(uint addr))
 113 {
 114         int bus_period,tmp,row,col;
 115         int total_size,bank_size,bank_code;
 116         int ecc_on;
 117         int mode;
 118         int bank_cnt;
 119
 120         int sdram0_pmit=0x07c00000;
 121         int sdram0_besr0=-1;
 122         int sdram0_besr1=-1;
 123         int sdram0_eccesr=-1;
 124         int sdram0_ecccfg;
 125
 126         int sdram0_rtr=0;
 127         int sdram0_tr=0;
 128
 129         int sdram0_b0cr;
 130         int sdram0_b1cr;
 131         int sdram0_b2cr;
 132         int sdram0_b3cr;
 133
 134         int sdram0_cfg=0;
 135
 136         int t_rp;
 137         int t_rcd;
 138         int t_ras;
 139         int t_rc;
 140         int min_cas;
 141
 142         if(read_spd == 0){
 143                 read_spd=spd_read;
 144         /*
 145          * Make sure I2C controller is initialized
 146          * before continuing.
 147          */
 148                 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 149         }
 150
 151
 152         /*
 153          * Calculate the bus period, we do it this
 154          * way to minimize stack utilization.
 155          */
 156         tmp = (mfdcr(pllmd) >> (31-6)) & 0xf;   /* get FBDV bits */
 157         tmp = CONFIG_SYS_CLK_FREQ * tmp;        /* get plb freq */
 158         bus_period = sdram_HZ_to_ns(tmp);       /* get sdram speed */
 159
 160         /* Make shure we are using SDRAM */
 161         if (read_spd(2) != 0x04){
 162           SPD_ERR("SDRAM - non SDRAM memory module found\n");
 163           }
 164
 165 /*------------------------------------------------------------------
 166   configure memory timing register
 167
 168   data from DIMM:
 169   27    IN Row Precharge Time ( t RP)
 170   29    MIN RAS to CAS Delay ( t RCD)
 171   127   Component and Clock Detail ,clk0-clk3, junction temp, CAS
 172   -------------------------------------------------------------------*/
 173
 174      /*
 175       * first figure out which cas latency mode to use
 176       * use the min supported mode
 177       */
 178
 179         tmp = read_spd(127) & 0x6;
 180      if(tmp == 0x02){              /* only cas = 2 supported */
 181           min_cas = 2;
 182 /*        t_ck = read_spd(9); */
 183 /*        t_ac = read_spd(10); */
 184           }
 185      else if (tmp == 0x04){         /* only cas = 3 supported */
 186           min_cas = 3;
 187 /*        t_ck = read_spd(9); */
 188 /*        t_ac = read_spd(10); */
 189           }
 190      else if (tmp == 0x06){         /* 2,3 supported, so use 2 */
 191           min_cas = 2;
 192 /*        t_ck = read_spd(23); */
 193 /*        t_ac = read_spd(24); */
 194           }
 195      else {
 196              SPD_ERR("SDRAM - unsupported CAS latency \n");
 197         }
 198
 199      /* get some timing values, t_rp,t_rcd,t_ras,t_rc
 200      */
 201      t_rp = read_spd(27);
 202      t_rcd = read_spd(29);
 203      t_ras = read_spd(30);
 204      t_rc = t_ras + t_rp;
 205
 206      /* The following timing calcs subtract 1 before deviding.
 207       * this has effect of using ceiling instead of floor rounding,
 208       * and also subtracting 1 to convert number to reg value
 209       */
 210      /* set up CASL */
 211      sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
 212      /* set up PTA */
 213      sdram0_tr |= (((t_rp - 1)/bus_period) & 0x3) << SDRAM0_TR_PTA_SHIFT;
 214      /* set up CTP */
 215      tmp = ((t_rc - t_rcd - t_rp -1) / bus_period) & 0x3;
 216      if(tmp<1) tmp=1;
 217      sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;
 218      /* set LDF = 2 cycles, reg value = 1 */
 219      sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;
 220      /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
 221         tmp = ( (t_rc - 1) / bus_period)-3;
 222         if(tmp<0)tmp=0;
 223         if(tmp>6)tmp=6;
 224         sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT;
 225      /* set RCD = t_rcd/bus_period*/
 226      sdram0_tr |= (((t_rcd - 1) / bus_period) &0x3) << SDRAM0_TR_RCD_SHIFT ;
 227
 228
 229 /*------------------------------------------------------------------
 230   configure RTR register
 231   -------------------------------------------------------------------*/
 232      row = read_spd(3);
 233      col = read_spd(4);
 234      tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */
 235      switch(tmp){
 236         case 0x00:
 237           tmp=15625;
 238           break;
 239         case 0x01:
 240           tmp=15625/4;
 241           break;
 242         case 0x02:
 243           tmp=15625/2;
 244           break;
 245         case 0x03:
 246           tmp=15625*2;
 247           break;
 248         case 0x04:
 249           tmp=15625*4;
 250           break;
 251         case 0x05:
 252           tmp=15625*8;
 253           break;
 254         default:
 255           SPD_ERR("SDRAM - Bad refresh period \n");
 256         }
 257         /* convert from nsec to bus cycles */
 258         tmp = tmp/bus_period;
 259         sdram0_rtr = (tmp & 0x3ff8)<<  SDRAM0_RTR_SHIFT;
 260
 261 /*------------------------------------------------------------------
 262   determine the number of banks used
 263   -------------------------------------------------------------------*/
 264         /* byte 7:6 is module data width */
 265         if(read_spd(7) != 0)
 266             SPD_ERR("SDRAM - unsupported module width\n");
 267         tmp = read_spd(6);
 268         if (tmp < 32)
 269             SPD_ERR("SDRAM - unsupported module width\n");
 270         else if (tmp < 64)
 271             bank_cnt=1;         /* one bank per sdram side */
 272         else if (tmp < 73)
 273             bank_cnt=2; /* need two banks per side */
 274         else if (tmp < 161)
 275             bank_cnt=4; /* need four banks per side */
 276         else
 277             SPD_ERR("SDRAM - unsupported module width\n");
 278
 279         /* byte 5 is the module row count (refered to as dimm "sides") */
 280         tmp = read_spd(5);
 281         if(tmp==1);
 282         else if(tmp==2) bank_cnt *=2;
 283         else if(tmp==4) bank_cnt *=4;
 284         else bank_cnt = 8;              /* 8 is an error code */
 285
 286         if(bank_cnt > 4)        /* we only have 4 banks to work with */
 287             SPD_ERR("SDRAM - unsupported module rows for this width\n");
 288
 289         /* now check for ECC ability of module. We only support ECC
 290          *   on 32 bit wide devices with 8 bit ECC.
 291          */
 292         if ( (read_spd(11)==2) && ((read_spd(6)==40) || (read_spd(14)==8)) ){
 293            sdram0_ecccfg=0xf<<SDRAM0_ECCCFG_SHIFT;
 294            ecc_on = 1;
 295         }
 296         else{
 297            sdram0_ecccfg=0;
 298            ecc_on = 0;
 299         }
 300
 301 /*------------------------------------------------------------------
 302         calculate total size
 303   -------------------------------------------------------------------*/
 304         /* calculate total size and do sanity check */
 305         tmp = read_spd(31);
 306         total_size=1<<22;       /* total_size = 4MB */
 307         /* now multiply 4M by the smallest device row density */
 308         /* note that we don't support asymetric rows */
 309         while (((tmp & 0x0001) == 0) && (tmp != 0)){
 310             total_size= total_size<<1;
 311             tmp = tmp>>1;
 312             }
 313         total_size *= read_spd(5);      /* mult by module rows (dimm sides) */
 314
 315 /*------------------------------------------------------------------
 316         map  rows * cols * banks to a mode
 317  -------------------------------------------------------------------*/
 318
 319         switch( row )
 320         {
 321         case 11:
 322                 switch ( col )
 323                 {
 324                 case 8:
 325                         mode=4; /* mode 5 */
 326                         break;
 327                 case 9:
 328                 case 10:
 329                         mode=0; /* mode 1 */
 330                         break;
 331                 default:
 332                 SPD_ERR("SDRAM - unsupported mode\n");
 333                 }
 334                 break;
 335         case 12:
 336                 switch ( col )
 337                 {
 338                 case 8:
 339                         mode=3; /* mode 4 */
 340                         break;
 341                 case 9:
 342                 case 10:
 343                         mode=1; /* mode 2 */
 344                         break;
 345                 default:
 346                 SPD_ERR("SDRAM - unsupported mode\n");
 347                 }
 348                 break;
 349         case 13:
 350                 switch ( col )
 351                 {
 352                 case 8:
 353                         mode=5; /* mode 6 */
 354                         break;
 355                 case 9:
 356                 case 10:
 357                         if (read_spd(17) ==2 )
 358                                 mode=6; /* mode 7 */
 359                         else
 360                                 mode=2; /* mode 3 */
 361                         break;
 362                 case 11:
 363                         mode=2; /* mode 3 */
 364                         break;
 365                 default:
 366                 SPD_ERR("SDRAM - unsupported mode\n");
 367                 }
 368                 break;
 369         default:
 370              SPD_ERR("SDRAM - unsupported mode\n");
 371         }
 372
 373 /*------------------------------------------------------------------
 374         using the calculated values, compute the bank
 375         config register values.
 376  -------------------------------------------------------------------*/
 377         sdram0_b1cr = 0;
 378         sdram0_b2cr = 0;
 379         sdram0_b3cr = 0;
 380
 381         /* compute the size of each bank */
 382         bank_size = total_size / bank_cnt;
 383         /* convert bank size to bank size code for ppc4xx
 384                 by takeing log2(bank_size) - 22 */
 385         tmp=bank_size;          /* start with tmp = bank_size */
 386         bank_code=0;                    /* and bank_code = 0 */
 387         while (tmp>1){          /* this takes log2 of tmp */
 388                 bank_code++;            /* and stores result in bank_code */
 389                 tmp=tmp>>1;
 390                 }                               /* bank_code is now log2(bank_size) */
 391         bank_code-=22;                          /* subtract 22 to get the code */
 392
 393         tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
 394         sdram0_b0cr = (bank_size) * 0 | tmp;
 395         if(bank_cnt>1) sdram0_b2cr = (bank_size) * 1 | tmp;
 396         if(bank_cnt>2) sdram0_b1cr = (bank_size) * 2 | tmp;
 397         if(bank_cnt>3) sdram0_b3cr = (bank_size) * 3 | tmp;
 398
 399
 400         /*
 401          *   enable sdram controller DCE=1
 402          *  enable burst read prefetch to 32 bytes BRPF=2
 403          *  leave other functions off
 404          */
 405
 406 /*------------------------------------------------------------------
 407         now that we've done our calculations, we are ready to
 408         program all the registers.
 409  -------------------------------------------------------------------*/
 410
 411
 412 #define mtsdram0(reg, data)  mtdcr(memcfga,reg);mtdcr(memcfgd,data)
 413         /* disable memcontroller so updates work */
 414         sdram0_cfg = 0;
 415         mtsdram0( mem_mcopt1, sdram0_cfg );
 416
 417         mtsdram0( mem_besra , sdram0_besr0 );
 418         mtsdram0( mem_besrb , sdram0_besr1 );
 419         mtsdram0( mem_rtr   , sdram0_rtr );
 420         mtsdram0( mem_pmit  , sdram0_pmit );
 421         mtsdram0( mem_mb0cf , sdram0_b0cr );
 422         mtsdram0( mem_mb1cf , sdram0_b1cr );
 423         mtsdram0( mem_mb2cf , sdram0_b2cr );
 424         mtsdram0( mem_mb3cf , sdram0_b3cr );
 425         mtsdram0( mem_sdtr1 , sdram0_tr );
 426         mtsdram0( mem_ecccf , sdram0_ecccfg );
 427         mtsdram0( mem_eccerr, sdram0_eccesr );
 428
 429         /* SDRAM have a power on delay,  500 micro should do */
 430         udelay(500);
 431         sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
 432         if(ecc_on) sdram0_cfg |= SDRAM0_CFG_MEMCHK;
 433         mtsdram0( mem_mcopt1, sdram0_cfg );
 434
 435
 436         /* kernel 2.4.2 from mvista has a bug with memory over 128MB */
 437 #ifdef MVISTA_MEM_BUG
 438         if (total_size > 128*1024*1024 )
 439                 total_size=128*1024*1024;
 440 #endif
 441         return (total_size);
 442 }
 443
 444 int spd_read(uint addr)
 445 {
 446         char data[2];
 447
 448         if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0)
 449                 return (int)data[0];
 450         else
 451                 return 0;
 452 }
 453
 454 #else                             /* CONFIG_440 */
 455
 456 /*-----------------------------------------------------------------------------
 457 |  Memory Controller Options 0
 458 +-----------------------------------------------------------------------------*/
 459 #define SDRAM_CFG0_DCEN           0x80000000  /* SDRAM Controller Enable      */
 460 #define SDRAM_CFG0_MCHK_MASK      0x30000000  /* Memory data errchecking mask */
 461 #define SDRAM_CFG0_MCHK_NON       0x00000000  /* No ECC generation            */
 462 #define SDRAM_CFG0_MCHK_GEN       0x20000000  /* ECC generation               */
 463 #define SDRAM_CFG0_MCHK_CHK       0x30000000  /* ECC generation and checking  */
 464 #define SDRAM_CFG0_RDEN           0x08000000  /* Registered DIMM enable       */
 465 #define SDRAM_CFG0_PMUD           0x04000000  /* Page management unit         */
 466 #define SDRAM_CFG0_DMWD_MASK      0x02000000  /* DRAM width mask              */
 467 #define SDRAM_CFG0_DMWD_32        0x00000000  /* 32 bits                      */
 468 #define SDRAM_CFG0_DMWD_64        0x02000000  /* 64 bits                      */
 469 #define SDRAM_CFG0_UIOS_MASK      0x00C00000  /* Unused IO State              */
 470 #define SDRAM_CFG0_PDP            0x00200000  /* Page deallocation policy     */
 471
 472 /*-----------------------------------------------------------------------------
 473 |  Memory Controller Options 1
 474 +-----------------------------------------------------------------------------*/
 475 #define SDRAM_CFG1_SRE            0x80000000  /* Self-Refresh Entry           */
 476 #define SDRAM_CFG1_PMEN           0x40000000  /* Power Management Enable      */
 477
 478 /*-----------------------------------------------------------------------------+
 479 |  SDRAM DEVPOT Options
 480 +-----------------------------------------------------------------------------*/
 481 #define SDRAM_DEVOPT_DLL          0x80000000
 482 #define SDRAM_DEVOPT_DS           0x40000000
 483
 484 /*-----------------------------------------------------------------------------+
 485 |  SDRAM MCSTS Options
 486 +-----------------------------------------------------------------------------*/
 487 #define SDRAM_MCSTS_MRSC          0x80000000
 488 #define SDRAM_MCSTS_SRMS          0x40000000
 489 #define SDRAM_MCSTS_CIS           0x20000000
 490
 491 /*-----------------------------------------------------------------------------
 492 |  SDRAM Refresh Timer Register
 493 +-----------------------------------------------------------------------------*/
 494 #define SDRAM_RTR_RINT_MASK       0xFFFF0000
 495 #define SDRAM_RTR_RINT_ENCODE(n)  (((n) << 16) & SDRAM_RTR_RINT_MASK)
 496 #define sdram_HZ_to_ns(hertz)     (1000000000/(hertz))
 497
 498 /*-----------------------------------------------------------------------------+
 499 |  SDRAM UABus Base Address Reg
 500 +-----------------------------------------------------------------------------*/
 501 #define SDRAM_UABBA_UBBA_MASK     0x0000000F
 502
 503 /*-----------------------------------------------------------------------------+
 504 |  Memory Bank 0-7 configuration
 505 +-----------------------------------------------------------------------------*/
 506 #define SDRAM_BXCR_SDBA_MASK      0xff800000      /* Base address             */
 507 #define SDRAM_BXCR_SDSZ_MASK      0x000e0000      /* Size                     */
 508 #define SDRAM_BXCR_SDSZ_8         0x00020000      /*   8M                     */
 509 #define SDRAM_BXCR_SDSZ_16        0x00040000      /*  16M                     */
 510 #define SDRAM_BXCR_SDSZ_32        0x00060000      /*  32M                     */
 511 #define SDRAM_BXCR_SDSZ_64        0x00080000      /*  64M                     */
 512 #define SDRAM_BXCR_SDSZ_128       0x000a0000      /* 128M                     */
 513 #define SDRAM_BXCR_SDSZ_256       0x000c0000      /* 256M                     */
 514 #define SDRAM_BXCR_SDSZ_512       0x000e0000      /* 512M                     */
 515 #define SDRAM_BXCR_SDAM_MASK      0x0000e000      /* Addressing mode          */
 516 #define SDRAM_BXCR_SDAM_1         0x00000000      /*   Mode 1                 */
 517 #define SDRAM_BXCR_SDAM_2         0x00002000      /*   Mode 2                 */
 518 #define SDRAM_BXCR_SDAM_3         0x00004000      /*   Mode 3                 */
 519 #define SDRAM_BXCR_SDAM_4         0x00006000      /*   Mode 4                 */
 520 #define SDRAM_BXCR_SDBE           0x00000001      /* Memory Bank Enable       */
 521
 522 /*-----------------------------------------------------------------------------+
 523 |  SDRAM TR0 Options
 524 +-----------------------------------------------------------------------------*/
 525 #define SDRAM_TR0_SDWR_MASK       0x80000000
 526 #define   SDRAM_TR0_SDWR_2_CLK    0x00000000
 527 #define   SDRAM_TR0_SDWR_3_CLK    0x80000000
 528 #define SDRAM_TR0_SDWD_MASK       0x40000000
 529 #define   SDRAM_TR0_SDWD_0_CLK    0x00000000
 530 #define   SDRAM_TR0_SDWD_1_CLK    0x40000000
 531 #define SDRAM_TR0_SDCL_MASK       0x01800000
 532 #define   SDRAM_TR0_SDCL_2_0_CLK  0x00800000
 533 #define   SDRAM_TR0_SDCL_2_5_CLK  0x01000000
 534 #define   SDRAM_TR0_SDCL_3_0_CLK  0x01800000
 535 #define SDRAM_TR0_SDPA_MASK       0x000C0000
 536 #define   SDRAM_TR0_SDPA_2_CLK    0x00040000
 537 #define   SDRAM_TR0_SDPA_3_CLK    0x00080000
 538 #define   SDRAM_TR0_SDPA_4_CLK    0x000C0000
 539 #define SDRAM_TR0_SDCP_MASK       0x00030000
 540 #define   SDRAM_TR0_SDCP_2_CLK    0x00000000
 541 #define   SDRAM_TR0_SDCP_3_CLK    0x00010000
 542 #define   SDRAM_TR0_SDCP_4_CLK    0x00020000
 543 #define   SDRAM_TR0_SDCP_5_CLK    0x00030000
 544 #define SDRAM_TR0_SDLD_MASK       0x0000C000
 545 #define   SDRAM_TR0_SDLD_1_CLK    0x00000000
 546 #define   SDRAM_TR0_SDLD_2_CLK    0x00004000
 547 #define SDRAM_TR0_SDRA_MASK       0x0000001C
 548 #define   SDRAM_TR0_SDRA_6_CLK    0x00000000
 549 #define   SDRAM_TR0_SDRA_7_CLK    0x00000004
 550 #define   SDRAM_TR0_SDRA_8_CLK    0x00000008
 551 #define   SDRAM_TR0_SDRA_9_CLK    0x0000000C
 552 #define   SDRAM_TR0_SDRA_10_CLK   0x00000010
 553 #define   SDRAM_TR0_SDRA_11_CLK   0x00000014
 554 #define   SDRAM_TR0_SDRA_12_CLK   0x00000018
 555 #define   SDRAM_TR0_SDRA_13_CLK   0x0000001C
 556 #define SDRAM_TR0_SDRD_MASK       0x00000003
 557 #define   SDRAM_TR0_SDRD_2_CLK    0x00000001
 558 #define   SDRAM_TR0_SDRD_3_CLK    0x00000002
 559 #define   SDRAM_TR0_SDRD_4_CLK    0x00000003
 560
 561 /*-----------------------------------------------------------------------------+
 562 |  SDRAM TR1 Options
 563 +-----------------------------------------------------------------------------*/
 564 #define SDRAM_TR1_RDSS_MASK         0xC0000000
 565 #define   SDRAM_TR1_RDSS_TR0        0x00000000
 566 #define   SDRAM_TR1_RDSS_TR1        0x40000000
 567 #define   SDRAM_TR1_RDSS_TR2        0x80000000
 568 #define   SDRAM_TR1_RDSS_TR3        0xC0000000
 569 #define SDRAM_TR1_RDSL_MASK         0x00C00000
 570 #define   SDRAM_TR1_RDSL_STAGE1     0x00000000
 571 #define   SDRAM_TR1_RDSL_STAGE2     0x00400000
 572 #define   SDRAM_TR1_RDSL_STAGE3     0x00800000
 573 #define SDRAM_TR1_RDCD_MASK         0x00000800
 574 #define   SDRAM_TR1_RDCD_RCD_0_0    0x00000000
 575 #define   SDRAM_TR1_RDCD_RCD_1_2    0x00000800
 576 #define SDRAM_TR1_RDCT_MASK         0x000001FF
 577 #define   SDRAM_TR1_RDCT_ENCODE(x)  (((x) << 0) & SDRAM_TR1_RDCT_MASK)
 578 #define   SDRAM_TR1_RDCT_DECODE(x)  (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
 579 #define   SDRAM_TR1_RDCT_MIN        0x00000000
 580 #define   SDRAM_TR1_RDCT_MAX        0x000001FF
 581
 582 /*-----------------------------------------------------------------------------+
 583 |  SDRAM WDDCTR Options
 584 +-----------------------------------------------------------------------------*/
 585 #define SDRAM_WDDCTR_WRCP_MASK       0xC0000000
 586 #define   SDRAM_WDDCTR_WRCP_0DEG     0x00000000
 587 #define   SDRAM_WDDCTR_WRCP_90DEG    0x40000000
 588 #define   SDRAM_WDDCTR_WRCP_180DEG   0x80000000
 589 #define SDRAM_WDDCTR_DCD_MASK        0x000001FF
 590
 591 /*-----------------------------------------------------------------------------+
 592 |  SDRAM CLKTR Options
 593 +-----------------------------------------------------------------------------*/
 594 #define SDRAM_CLKTR_CLKP_MASK       0xC0000000
 595 #define   SDRAM_CLKTR_CLKP_0DEG     0x00000000
 596 #define   SDRAM_CLKTR_CLKP_90DEG    0x40000000
 597 #define   SDRAM_CLKTR_CLKP_180DEG   0x80000000
 598 #define SDRAM_CLKTR_DCDT_MASK       0x000001FF
 599
 600 /*-----------------------------------------------------------------------------+
 601 |  SDRAM DLYCAL Options
 602 +-----------------------------------------------------------------------------*/
 603 #define SDRAM_DLYCAL_DLCV_MASK      0x000003FC
 604 #define   SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
 605 #define   SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
 606
 607 /*-----------------------------------------------------------------------------+
 608 |  General Definition
 609 +-----------------------------------------------------------------------------*/
 610 #define DEFAULT_SPD_ADDR1   0x53
 611 #define DEFAULT_SPD_ADDR2   0x52
 612 #define ONE_BILLION         1000000000
 613 #define MAXBANKS            4               /* at most 4 dimm banks */
 614 #define MAX_SPD_BYTES       256
 615 #define NUMHALFCYCLES       4
 616 #define NUMMEMTESTS         8
 617 #define NUMMEMWORDS         8
 618 #define MAXBXCR             4
 619 #define TRUE                1
 620 #define FALSE               0
 621
 622 const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
 623     {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 624      0xFFFFFFFF, 0xFFFFFFFF},
 625     {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 626      0x00000000, 0x00000000},
 627     {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 628      0x55555555, 0x55555555},
 629     {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 630      0xAAAAAAAA, 0xAAAAAAAA},
 631     {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 632      0x5A5A5A5A, 0x5A5A5A5A},
 633     {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 634      0xA5A5A5A5, 0xA5A5A5A5},
 635     {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
 636      0x55AA55AA, 0x55AA55AA},
 637     {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 638      0xAA55AA55, 0xAA55AA55}
 639 };
 640
 641
 642 unsigned char spd_read(uchar chip, uint addr);
 643
 644 void get_spd_info(unsigned long* dimm_populated,
 645                   unsigned char* iic0_dimm_addr,
 646                   unsigned long  num_dimm_banks);
 647
 648 void check_mem_type
 649                  (unsigned long* dimm_populated,
 650                   unsigned char* iic0_dimm_addr,
 651                   unsigned long  num_dimm_banks);
 652
 653 void check_volt_type
 654                  (unsigned long* dimm_populated,
 655                   unsigned char* iic0_dimm_addr,
 656                   unsigned long  num_dimm_banks);
 657
 658 void program_cfg0(unsigned long* dimm_populated,
 659                   unsigned char* iic0_dimm_addr,
 660                   unsigned long  num_dimm_banks);
 661
 662 void program_cfg1(unsigned long* dimm_populated,
 663                   unsigned char* iic0_dimm_addr,
 664                   unsigned long  num_dimm_banks);
 665
 666 void program_rtr (unsigned long* dimm_populated,
 667                   unsigned char* iic0_dimm_addr,
 668                   unsigned long  num_dimm_banks);
 669
 670 void program_tr0 (unsigned long* dimm_populated,
 671                   unsigned char* iic0_dimm_addr,
 672                   unsigned long  num_dimm_banks);
 673
 674 void program_tr1 (void);
 675
 676 void program_ecc (unsigned long  num_bytes);
 677
 678 unsigned
 679 long  program_bxcr(unsigned long* dimm_populated,
 680                    unsigned char* iic0_dimm_addr,
 681                    unsigned long  num_dimm_banks);
 682
 683 /*
 684  * This function is reading data from the DIMM module EEPROM over the SPD bus
 685  * and uses that to program the sdram controller.
 686  *
 687  * This works on boards that has the same schematics that the IBM walnut has.
 688  *
 689  * BUG: Don't handle ECC memory
 690  * BUG: A few values in the TR register is currently hardcoded
 691  */
 692
 693 long int spd_sdram(void) {
 694     unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 695     unsigned long dimm_populated[sizeof(iic0_dimm_addr)];
 696     unsigned long total_size;
 697     unsigned long cfg0;
 698     unsigned long mcsts;
 699     unsigned long num_dimm_banks;               /* on board dimm banks */
 700
 701     num_dimm_banks = sizeof(iic0_dimm_addr);
 702
 703         /*
 704          * Make sure I2C controller is initialized
 705          * before continuing.
 706          */
 707         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 708
 709     /*
 710      * Read the SPD information using I2C interface. Check to see if the
 711      * DIMM slots are populated.
 712      */
 713     get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 714
 715     /*
 716      * Check the memory type for the dimms plugged.
 717      */
 718     check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 719
 720     /*
 721      * Check the voltage type for the dimms plugged.
 722      */
 723     check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 724
 725     /*
 726      * program 440GP SDRAM controller options (SDRAM0_CFG0)
 727      */
 728     program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 729
 730     /*
 731      * program 440GP SDRAM controller options (SDRAM0_CFG1)
 732      */
 733     program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 734
 735     /*
 736      * program SDRAM refresh register (SDRAM0_RTR)
 737      */
 738     program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 739
 740     /*
 741      * program SDRAM Timing Register 0 (SDRAM0_TR0)
 742      */
 743     program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 744
 745     /*
 746      * program the BxCR registers to find out total sdram installed
 747      */
 748     total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
 749         num_dimm_banks);
 750
 751     /*
 752      * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
 753      */
 754     mtsdram(mem_clktr, 0x40000000);
 755
 756     /*
 757      * delay to ensure 200 usec has elapsed
 758      */
 759     udelay(400);
 760
 761     /*
 762      * enable the memory controller
 763      */
 764     mfsdram(mem_cfg0, cfg0);
 765     mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN);
 766
 767     /*
 768      * wait for SDRAM_CFG0_DC_EN to complete
 769      */
 770     while(1) {
 771         mfsdram(mem_mcsts, mcsts);
 772         if ((mcsts & SDRAM_MCSTS_MRSC) != 0) {
 773             break;
 774         }
 775     }
 776
 777     /*
 778      * program SDRAM Timing Register 1, adding some delays
 779      */
 780     program_tr1();
 781
 782     /*
 783      * if ECC is enabled, initialize parity bits
 784      */
 785
 786         return total_size;
 787 }
 788
 789 unsigned char spd_read(uchar chip, uint addr) {
 790         unsigned char data[2];
 791
 792         if (i2c_read(chip, addr, 1, data, 1) == 0)
 793                 return data[0];
 794         else
 795                 return 0;
 796 }
 797
 798 void get_spd_info(unsigned long*   dimm_populated,
 799                   unsigned char*   iic0_dimm_addr,
 800                   unsigned long    num_dimm_banks)
 801 {
 802     unsigned long dimm_num;
 803     unsigned long dimm_found;
 804     unsigned char num_of_bytes;
 805     unsigned char total_size;
 806
 807     dimm_found = FALSE;
 808     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 809         num_of_bytes = 0;
 810         total_size = 0;
 811
 812         num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 813         total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 814
 815         if ((num_of_bytes != 0) && (total_size != 0)) {
 816             dimm_populated[dimm_num] = TRUE;
 817             dimm_found = TRUE;
 818 #if 0
 819             printf("DIMM slot %lu: populated\n", dimm_num);
 820 #endif
 821         }
 822         else {
 823             dimm_populated[dimm_num] = FALSE;
 824 #if 0
 825             printf("DIMM slot %lu: Not populated\n", dimm_num);
 826 #endif
 827         }
 828     }
 829
 830     if (dimm_found == FALSE) {
 831         printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 832         hang();
 833     }
 834 }
 835
 836 void check_mem_type(unsigned long*   dimm_populated,
 837                     unsigned char*   iic0_dimm_addr,
 838                     unsigned long    num_dimm_banks)
 839 {
 840     unsigned long dimm_num;
 841     unsigned char dimm_type;
 842
 843     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 844         if (dimm_populated[dimm_num] == TRUE) {
 845             dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 846             switch (dimm_type) {
 847             case 7:
 848 #if 0
 849                 printf("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
 850 #endif
 851                 break;
 852             default:
 853                 printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
 854                     dimm_num);
 855                 printf("Only DDR SDRAM DIMMs are supported.\n");
 856                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 857                 hang();
 858                 break;
 859             }
 860         }
 861     }
 862 }
 863
 864
 865 void check_volt_type(unsigned long*   dimm_populated,
 866                      unsigned char*   iic0_dimm_addr,
 867                      unsigned long    num_dimm_banks)
 868 {
 869     unsigned long dimm_num;
 870     unsigned long voltage_type;
 871
 872     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 873         if (dimm_populated[dimm_num] == TRUE) {
 874             voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 875             if (voltage_type != 0x04) {
 876                 printf("ERROR: DIMM %lu with unsupported voltage level.\n",
 877                     dimm_num);
 878                 hang();
 879             }
 880             else {
 881 #if 0
 882                 printf("DIMM %lu voltage level supported.\n", dimm_num);
 883 #endif
 884             }
 885             break;
 886         }
 887     }
 888 }
 889
 890 void program_cfg0(unsigned long* dimm_populated,
 891                   unsigned char* iic0_dimm_addr,
 892                   unsigned long  num_dimm_banks)
 893 {
 894     unsigned long dimm_num;
 895     unsigned long cfg0;
 896     unsigned long ecc_enabled;
 897     unsigned char ecc;
 898     unsigned char attributes;
 899     unsigned long data_width;
 900     unsigned long dimm_32bit;
 901     unsigned long dimm_64bit;
 902
 903     /*
 904      * get Memory Controller Options 0 data
 905      */
 906     mfsdram(mem_cfg0, cfg0);
 907
 908     /*
 909      * clear bits
 910      */
 911     cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK |
 912               SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
 913               SDRAM_CFG0_DMWD_MASK |
 914               SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
 915
 916
 917     /*
 918      * FIXME: assume the DDR SDRAMs in both banks are the same
 919      */
 920     ecc_enabled = TRUE;
 921     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 922         if (dimm_populated[dimm_num] == TRUE) {
 923             ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
 924             if (ecc != 0x02) {
 925                 ecc_enabled = FALSE;
 926             }
 927
 928             /*
 929              * program Registered DIMM Enable
 930              */
 931             attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
 932             if ((attributes & 0x02) != 0x00) {
 933                 cfg0 |= SDRAM_CFG0_RDEN;
 934             }
 935
 936             /*
 937              * program DDR SDRAM Data Width
 938              */
 939             data_width =
 940                 (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
 941                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
 942             if (data_width == 64 || data_width == 72) {
 943                 dimm_64bit = TRUE;
 944                 cfg0 |= SDRAM_CFG0_DMWD_64;
 945             }
 946             else if (data_width == 32 || data_width == 40) {
 947                 dimm_32bit = TRUE;
 948                 cfg0 |= SDRAM_CFG0_DMWD_32;
 949             }
 950             else {
 951                 printf("WARNING: DIMM with datawidth of %lu bits.\n",
 952                     data_width);
 953                 printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
 954                 hang();
 955             }
 956             break;
 957         }
 958     }
 959
 960     /*
 961      * program Memory Data Error Checking
 962      */
 963     if (ecc_enabled == TRUE) {
 964         cfg0 |= SDRAM_CFG0_MCHK_GEN;
 965     }
 966     else {
 967         cfg0 |= SDRAM_CFG0_MCHK_NON;
 968     }
 969
 970     /*
 971      * program Page Management Unit
 972      */
 973     cfg0 |= SDRAM_CFG0_PMUD;
 974
 975     /*
 976      * program Memory Controller Options 0
 977      * Note: DCEN must be enabled after all DDR SDRAM controller
 978      * configuration registers get initialized.
 979      */
 980     mtsdram(mem_cfg0, cfg0);
 981 }
 982
 983 void program_cfg1(unsigned long* dimm_populated,
 984                   unsigned char* iic0_dimm_addr,
 985                   unsigned long  num_dimm_banks)
 986 {
 987     unsigned long cfg1;
 988     mfsdram(mem_cfg1, cfg1);
 989
 990     /*
 991      * Self-refresh exit, disable PM
 992      */
 993     cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN);
 994
 995     /*
 996      * program Memory Controller Options 1
 997      */
 998     mtsdram(mem_cfg1, cfg1);
 999 }
1000
1001 void program_rtr (unsigned long* dimm_populated,
1002                   unsigned char* iic0_dimm_addr,
1003                   unsigned long  num_dimm_banks)
1004 {
1005     unsigned long dimm_num;
1006     unsigned long bus_period_x_10;
1007     unsigned long refresh_rate = 0;
1008     unsigned char refresh_rate_type;
1009     unsigned long refresh_interval;
1010     unsigned long sdram_rtr;
1011     PPC440_SYS_INFO sys_info;
1012
1013     /*
1014      * get the board info
1015      */
1016     get_sys_info(&sys_info);
1017     bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
1018
1019
1020     for (dimm_num = 0;  dimm_num < num_dimm_banks; dimm_num++) {
1021         if (dimm_populated[dimm_num] == TRUE) {
1022             refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
1023             switch (refresh_rate_type) {
1024             case 0x00:
1025                 refresh_rate = 15625;
1026                 break;
1027             case 0x011:
1028                 refresh_rate = 15625/4;
1029                 break;
1030             case 0x02:
1031                 refresh_rate = 15625/2;
1032                 break;
1033             case 0x03:
1034                 refresh_rate = 15626*2;
1035                 break;
1036             case 0x04:
1037                 refresh_rate = 15625*4;
1038                 break;
1039             case 0x05:
1040                 refresh_rate = 15625*8;
1041                 break;
1042             default:
1043                 printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
1044                     dimm_num);
1045                 printf("Replace the DIMM module with a supported DIMM.\n");
1046                 break;
1047             }
1048
1049             break;
1050         }
1051     }
1052
1053     refresh_interval = refresh_rate * 10 / bus_period_x_10;
1054     sdram_rtr = (refresh_interval & 0x3ff8) <<  16;
1055
1056     /*
1057      * program Refresh Timer Register (SDRAM0_RTR)
1058      */
1059     mtsdram(mem_rtr, sdram_rtr);
1060 }
1061
1062 void program_tr0 (unsigned long* dimm_populated,
1063                   unsigned char* iic0_dimm_addr,
1064                   unsigned long  num_dimm_banks)
1065 {
1066     unsigned long dimm_num;
1067     unsigned long tr0;
1068     unsigned char wcsbc;
1069     unsigned char t_rp_ns;
1070     unsigned char t_rcd_ns;
1071     unsigned char t_ras_ns;
1072     unsigned long t_rp_clk;
1073     unsigned long t_ras_rcd_clk;
1074     unsigned long t_rcd_clk;
1075     unsigned long t_rfc_clk;
1076     unsigned long plb_check;
1077     unsigned char cas_bit;
1078     unsigned long cas_index;
1079     unsigned char cas_2_0_available;
1080     unsigned char cas_2_5_available;
1081     unsigned char cas_3_0_available;
1082     unsigned long cycle_time_ns_x_10[3];
1083     unsigned long tcyc_3_0_ns_x_10;
1084     unsigned long tcyc_2_5_ns_x_10;
1085     unsigned long tcyc_2_0_ns_x_10;
1086     unsigned long tcyc_reg;
1087     unsigned long bus_period_x_10;
1088     PPC440_SYS_INFO sys_info;
1089     unsigned long residue;
1090
1091     /*
1092      * get the board info
1093      */
1094     get_sys_info(&sys_info);
1095     bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
1096
1097     /*
1098      * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
1099      */
1100     mfsdram(mem_tr0, tr0);
1101     tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
1102              SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
1103              SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
1104              SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
1105
1106     /*
1107      * initialization
1108      */
1109     wcsbc = 0;
1110     t_rp_ns = 0;
1111     t_rcd_ns = 0;
1112     t_ras_ns = 0;
1113     cas_2_0_available = TRUE;
1114     cas_2_5_available = TRUE;
1115     cas_3_0_available = TRUE;
1116     tcyc_2_0_ns_x_10 = 0;
1117     tcyc_2_5_ns_x_10 = 0;
1118     tcyc_3_0_ns_x_10 = 0;
1119
1120     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1121         if (dimm_populated[dimm_num] == TRUE) {
1122             wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
1123             t_rp_ns  = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
1124             t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
1125             t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
1126             cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1127
1128             for (cas_index = 0; cas_index < 3; cas_index++) {
1129                 switch (cas_index) {
1130                 case 0:
1131                     tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1132                     break;
1133                 case 1:
1134                     tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1135                     break;
1136                 default:
1137                     tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1138                     break;
1139                 }
1140
1141                 if ((tcyc_reg & 0x0F) >= 10) {
1142                     printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
1143                         dimm_num);
1144                     hang();
1145                 }
1146
1147                 cycle_time_ns_x_10[cas_index] =
1148                     (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
1149             }
1150
1151             cas_index = 0;
1152
1153             if ((cas_bit & 0x80) != 0) {
1154                 cas_index += 3;
1155             }
1156             else if ((cas_bit & 0x40) != 0) {
1157                 cas_index += 2;
1158             }
1159             else if ((cas_bit & 0x20) != 0) {
1160                 cas_index += 1;
1161             }
1162
1163             if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
1164                 tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
1165                 cas_index++;
1166             }
1167             else {
1168                 if (cas_index != 0) {
1169                     cas_index++;
1170                 }
1171                 cas_3_0_available = FALSE;
1172             }
1173
1174             if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
1175                 tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
1176                 cas_index++;
1177             }
1178             else {
1179                 if (cas_index != 0) {
1180                     cas_index++;
1181                 }
1182                 cas_2_5_available = FALSE;
1183             }
1184
1185             if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
1186                 tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
1187                 cas_index++;
1188             }
1189             else {
1190                 if (cas_index != 0) {
1191                     cas_index++;
1192                 }
1193                 cas_2_0_available = FALSE;
1194             }
1195
1196             break;
1197         }
1198     }
1199
1200     /*
1201      * Program SD_WR and SD_WCSBC fields
1202      */
1203     tr0 |= SDRAM_TR0_SDWR_2_CLK;                /* Write Recovery: 2 CLK */
1204     switch (wcsbc) {
1205     case 0:
1206         tr0 |= SDRAM_TR0_SDWD_0_CLK;
1207         break;
1208     default:
1209         tr0 |= SDRAM_TR0_SDWD_1_CLK;
1210         break;
1211     }
1212
1213     /*
1214      * Program SD_CASL field
1215      */
1216     if ((cas_2_0_available == TRUE) &&
1217         (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
1218         tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
1219     }
1220     else if((cas_2_5_available == TRUE) &&
1221         (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
1222         tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
1223     }
1224     else if((cas_3_0_available == TRUE) &&
1225         (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
1226         tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
1227     }
1228     else {
1229         printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
1230         printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1231         printf("Make sure the PLB speed is within the supported range.\n");
1232         hang();
1233     }
1234
1235     /*
1236      * Calculate Trp in clock cycles and round up if necessary
1237      * Program SD_PTA field
1238      */
1239     t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION;
1240     plb_check = ONE_BILLION * t_rp_clk / t_rp_ns;
1241     if (sys_info.freqPLB != plb_check) {
1242         t_rp_clk++;
1243     }
1244     switch ((unsigned long)t_rp_clk) {
1245     case 0:
1246     case 1:
1247     case 2:
1248         tr0 |= SDRAM_TR0_SDPA_2_CLK;
1249         break;
1250     case 3:
1251         tr0 |= SDRAM_TR0_SDPA_3_CLK;
1252         break;
1253     default:
1254         tr0 |= SDRAM_TR0_SDPA_4_CLK;
1255         break;
1256     }
1257
1258     /*
1259      * Program SD_CTP field
1260      */
1261     t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION;
1262     plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns);
1263     if (sys_info.freqPLB != plb_check) {
1264         t_ras_rcd_clk++;
1265     }
1266     switch (t_ras_rcd_clk) {
1267     case 0:
1268     case 1:
1269     case 2:
1270       tr0 |= SDRAM_TR0_SDCP_2_CLK;
1271       break;
1272     case 3:
1273       tr0 |= SDRAM_TR0_SDCP_3_CLK;
1274       break;
1275     case 4:
1276       tr0 |= SDRAM_TR0_SDCP_4_CLK;
1277       break;
1278     default:
1279       tr0 |= SDRAM_TR0_SDCP_5_CLK;
1280       break;
1281     }
1282
1283     /*
1284      * Program SD_LDF field
1285      */
1286     tr0 |= SDRAM_TR0_SDLD_2_CLK;
1287
1288     /*
1289      * Program SD_RFTA field
1290      * FIXME tRFC hardcoded as 75 nanoseconds
1291      */
1292     t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75);
1293     residue = sys_info.freqPLB % (ONE_BILLION / 75);
1294     if (residue >= (ONE_BILLION / 150)) {
1295         t_rfc_clk++;
1296     }
1297     switch (t_rfc_clk) {
1298     case 0:
1299     case 1:
1300     case 2:
1301     case 3:
1302     case 4:
1303     case 5:
1304     case 6:
1305         tr0 |= SDRAM_TR0_SDRA_6_CLK;
1306         break;
1307     case 7:
1308         tr0 |= SDRAM_TR0_SDRA_7_CLK;
1309         break;
1310     case 8:
1311         tr0 |= SDRAM_TR0_SDRA_8_CLK;
1312         break;
1313     case 9:
1314         tr0 |= SDRAM_TR0_SDRA_9_CLK;
1315         break;
1316     case 10:
1317         tr0 |= SDRAM_TR0_SDRA_10_CLK;
1318         break;
1319     case 11:
1320         tr0 |= SDRAM_TR0_SDRA_11_CLK;
1321         break;
1322     case 12:
1323         tr0 |= SDRAM_TR0_SDRA_12_CLK;
1324         break;
1325     default:
1326         tr0 |= SDRAM_TR0_SDRA_13_CLK;
1327         break;
1328     }
1329
1330     /*
1331      * Program SD_RCD field
1332      */
1333     t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION;
1334     plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns;
1335     if (sys_info.freqPLB != plb_check) {
1336         t_rcd_clk++;
1337     }
1338     switch (t_rcd_clk) {
1339     case 0:
1340     case 1:
1341     case 2:
1342         tr0 |= SDRAM_TR0_SDRD_2_CLK;
1343         break;
1344     case 3:
1345         tr0 |= SDRAM_TR0_SDRD_3_CLK;
1346         break;
1347     default:
1348         tr0 |= SDRAM_TR0_SDRD_4_CLK;
1349         break;
1350     }
1351
1352 #if 0
1353     printf("tr0: %x\n", tr0);
1354 #endif
1355     mtsdram(mem_tr0, tr0);
1356 }
1357
1358 void program_tr1 (void)
1359 {
1360     unsigned long tr0;
1361     unsigned long tr1;
1362     unsigned long cfg0;
1363     unsigned long ecc_temp;
1364     unsigned long dlycal;
1365     unsigned long dly_val;
1366     unsigned long i, j, k;
1367     unsigned long bxcr_num;
1368     unsigned long max_pass_length;
1369     unsigned long current_pass_length;
1370     unsigned long current_fail_length;
1371     unsigned long current_start;
1372     unsigned long rdclt;
1373     unsigned long rdclt_offset;
1374     long max_start;
1375     long max_end;
1376     long rdclt_average;
1377     unsigned char window_found;
1378     unsigned char fail_found;
1379     unsigned char pass_found;
1380     unsigned long * membase;
1381     PPC440_SYS_INFO sys_info;
1382
1383     /*
1384      * get the board info
1385      */
1386     get_sys_info(&sys_info);
1387
1388     /*
1389      * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
1390      */
1391     mfsdram(mem_tr1, tr1);
1392     tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
1393              SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
1394
1395     mfsdram(mem_tr0, tr0);
1396     if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
1397        (sys_info.freqPLB > 100000000)) {
1398         tr1 |= SDRAM_TR1_RDSS_TR2;
1399         tr1 |= SDRAM_TR1_RDSL_STAGE3;
1400         tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1401     }
1402     else {
1403         tr1 |= SDRAM_TR1_RDSS_TR1;
1404         tr1 |= SDRAM_TR1_RDSL_STAGE2;
1405         tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1406     }
1407
1408     /*
1409      * save CFG0 ECC setting to a temporary variable and turn ECC off
1410      */
1411     mfsdram(mem_cfg0, cfg0);
1412     ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
1413     mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
1414
1415     /*
1416      * get the delay line calibration register value
1417      */
1418     mfsdram(mem_dlycal, dlycal);
1419     dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
1420
1421     max_pass_length = 0;
1422     max_start = 0;
1423     max_end = 0;
1424     current_pass_length = 0;
1425     current_fail_length = 0;
1426     current_start = 0;
1427     rdclt_offset = 0;
1428     window_found = FALSE;
1429     fail_found = FALSE;
1430     pass_found = FALSE;
1431 #ifdef DEBUG
1432     printf("Starting memory test ");
1433 #endif
1434     for (k = 0; k < NUMHALFCYCLES; k++) {
1435         for (rdclt = 0; rdclt < dly_val; rdclt++)  {
1436             /*
1437              * Set the timing reg for the test.
1438              */
1439             mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
1440
1441             for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
1442                 mtdcr(memcfga, mem_b0cr + (bxcr_num<<2));
1443                 if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
1444                     /* Bank is enabled */
1445                     membase = (unsigned long*)
1446                         (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
1447
1448                     /*
1449                      * Run the short memory test
1450                      */
1451                     for (i = 0; i < NUMMEMTESTS; i++) {
1452                         for (j = 0; j < NUMMEMWORDS; j++) {
1453                             membase[j] = test[i][j];
1454                             ppcDcbf((unsigned long)&(membase[j]));
1455                         }
1456
1457                         for (j = 0; j < NUMMEMWORDS; j++) {
1458                             if (membase[j] != test[i][j]) {
1459                                 ppcDcbf((unsigned long)&(membase[j]));
1460                                 break;
1461                             }
1462                             ppcDcbf((unsigned long)&(membase[j]));
1463                         }
1464
1465                         if (j < NUMMEMWORDS) {
1466                             break;
1467                         }
1468                     }
1469
1470                     /*
1471                      * see if the rdclt value passed
1472                      */
1473                     if (i < NUMMEMTESTS) {
1474                         break;
1475                     }
1476                 }
1477             }
1478
1479             if (bxcr_num == MAXBXCR) {
1480                 if (fail_found == TRUE) {
1481                     pass_found = TRUE;
1482                     if (current_pass_length == 0) {
1483                         current_start = rdclt_offset + rdclt;
1484                     }
1485
1486                     current_fail_length = 0;
1487                     current_pass_length++;
1488
1489                     if (current_pass_length > max_pass_length) {
1490                         max_pass_length = current_pass_length;
1491                         max_start = current_start;
1492                         max_end = rdclt_offset + rdclt;
1493                     }
1494                 }
1495             }
1496             else {
1497                 current_pass_length = 0;
1498                 current_fail_length++;
1499
1500                 if (current_fail_length >= (dly_val>>2)) {
1501                     if (fail_found == FALSE) {
1502                         fail_found = TRUE;
1503                     }
1504                     else if (pass_found == TRUE) {
1505                         window_found = TRUE;
1506                         break;
1507                     }
1508                 }
1509             }
1510         }
1511 #ifdef DEBUG
1512         printf(".");
1513 #endif
1514         if (window_found == TRUE) {
1515             break;
1516         }
1517
1518         tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1519         rdclt_offset += dly_val;
1520     }
1521 #ifdef DEBUG
1522     printf("\n");
1523 #endif
1524
1525     /*
1526      * make sure we find the window
1527      */
1528     if (window_found == FALSE) {
1529        printf("ERROR: Cannot determine a common read delay.\n");
1530        hang();
1531     }
1532
1533     /*
1534      * restore the orignal ECC setting
1535      */
1536     mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
1537
1538     /*
1539      * set the SDRAM TR1 RDCD value
1540      */
1541     tr1 &= ~SDRAM_TR1_RDCD_MASK;
1542     if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) {
1543         tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1544     }
1545     else {
1546         tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1547     }
1548
1549     /*
1550      * set the SDRAM TR1 RDCLT value
1551      */
1552     tr1 &= ~SDRAM_TR1_RDCT_MASK;
1553     while (max_end >= (dly_val<<1)) {
1554         max_end -= (dly_val<<1);
1555         max_start -= (dly_val<<1);
1556     }
1557
1558     rdclt_average = ((max_start + max_end) >> 1);
1559     if (rdclt_average >= 0x60)
1560         while(1);
1561
1562     if (rdclt_average < 0) {
1563         rdclt_average = 0;
1564     }
1565
1566     if (rdclt_average >= dly_val) {
1567         rdclt_average -= dly_val;
1568         tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1569     }
1570     tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
1571
1572 #if 0
1573     printf("tr1: %x\n", tr1);
1574 #endif
1575     /*
1576      * program SDRAM Timing Register 1 TR1
1577      */
1578     mtsdram(mem_tr1, tr1);
1579 }
1580
1581 unsigned long program_bxcr(unsigned long* dimm_populated,
1582                            unsigned char* iic0_dimm_addr,
1583                            unsigned long  num_dimm_banks)
1584 {
1585     unsigned long dimm_num;
1586     unsigned long bxcr_num;
1587     unsigned long bank_base_addr;
1588     unsigned long bank_size_bytes;
1589     unsigned long cr;
1590     unsigned long i;
1591     unsigned long temp;
1592     unsigned char num_row_addr;
1593     unsigned char num_col_addr;
1594     unsigned char num_banks;
1595     unsigned char bank_size_id;
1596
1597
1598     /*
1599      * Set the BxCR regs.  First, wipe out the bank config registers.
1600      */
1601     for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
1602         mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
1603         mtdcr(memcfgd, 0x00000000);
1604     }
1605
1606     /*
1607      * reset the bank_base address
1608      */
1609     bank_base_addr = CFG_SDRAM_BASE;
1610
1611     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1612         if (dimm_populated[dimm_num] == TRUE) {
1613             num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
1614             num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
1615             num_banks    = spd_read(iic0_dimm_addr[dimm_num], 5);
1616             bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
1617
1618             /*
1619              * Set the SDRAM0_BxCR regs
1620              */
1621             cr = 0;
1622             bank_size_bytes = 4 * 1024 * 1024 * bank_size_id;
1623             switch (bank_size_id) {
1624             case 0x02:
1625                 cr |= SDRAM_BXCR_SDSZ_8;
1626                 break;
1627             case 0x04:
1628                 cr |= SDRAM_BXCR_SDSZ_16;
1629                 break;
1630             case 0x08:
1631                 cr |= SDRAM_BXCR_SDSZ_32;
1632                 break;
1633             case 0x10:
1634                 cr |= SDRAM_BXCR_SDSZ_64;
1635                 break;
1636             case 0x20:
1637                 cr |= SDRAM_BXCR_SDSZ_128;
1638                 break;
1639             case 0x40:
1640                 cr |= SDRAM_BXCR_SDSZ_256;
1641                 break;
1642             case 0x80:
1643                 cr |= SDRAM_BXCR_SDSZ_512;
1644                 break;
1645             default:
1646                 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1647                     dimm_num);
1648                 printf("ERROR: Unsupported value for the banksize: %d.\n",
1649                    bank_size_id);
1650                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1651                 hang();
1652             }
1653
1654             switch (num_col_addr) {
1655             case 0x08:
1656                 cr |= SDRAM_BXCR_SDAM_1;
1657                 break;
1658             case 0x09:
1659                 cr |= SDRAM_BXCR_SDAM_2;
1660                 break;
1661             case 0x0A:
1662                 cr |= SDRAM_BXCR_SDAM_3;
1663                 break;
1664             case 0x0B:
1665                 cr |= SDRAM_BXCR_SDAM_4;
1666                 break;
1667             default:
1668                 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1669                    dimm_num);
1670                 printf("ERROR: Unsupported value for number of "
1671                    "column addresses: %d.\n", num_col_addr);
1672                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1673                 hang();
1674             }
1675
1676             /*
1677              * enable the bank
1678              */
1679             cr |= SDRAM_BXCR_SDBE;
1680
1681             /*------------------------------------------------------------------
1682             | This next section is hardware dependent and must be programmed
1683             | to match the hardware.
1684             +-----------------------------------------------------------------*/
1685             if (dimm_num == 0) {
1686                 for (i = 0; i < num_banks; i++) {
1687                     mtdcr(memcfga, mem_b0cr + (i << 2));
1688                     temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
1689                                               SDRAM_BXCR_SDSZ_MASK |
1690                                               SDRAM_BXCR_SDAM_MASK |
1691                                               SDRAM_BXCR_SDBE);
1692                     cr |= temp;
1693                     cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
1694                     mtdcr(memcfgd, cr);
1695                     bank_base_addr += bank_size_bytes;
1696                 }
1697             }
1698             else {
1699                 for (i = 0; i < num_banks; i++) {
1700                     mtdcr(memcfga, mem_b2cr + (i << 2));
1701                     temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
1702                                               SDRAM_BXCR_SDSZ_MASK |
1703                                               SDRAM_BXCR_SDAM_MASK |
1704                                               SDRAM_BXCR_SDBE);
1705                     cr |= temp;
1706                     cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
1707                     mtdcr(memcfgd, cr);
1708                     bank_base_addr += bank_size_bytes;
1709                 }
1710             }
1711         }
1712     }
1713
1714     return(bank_base_addr);
1715 }
1716
1717 void program_ecc (unsigned long  num_bytes)
1718 {
1719     unsigned long bank_base_addr;
1720     unsigned long current_address;
1721     unsigned long end_address;
1722     unsigned long address_increment;
1723     unsigned long cfg0;
1724
1725     /*
1726      * get Memory Controller Options 0 data
1727      */
1728     mfsdram(mem_cfg0, cfg0);
1729
1730     /*
1731      * reset the bank_base address
1732      */
1733     bank_base_addr = CFG_SDRAM_BASE;
1734
1735     if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) {
1736         mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
1737             SDRAM_CFG0_MCHK_GEN);
1738
1739         if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) {
1740             address_increment = 4;
1741         }
1742         else {
1743             address_increment = 8;
1744         }
1745
1746         current_address = (unsigned long)(bank_base_addr);
1747         end_address = (unsigned long)(bank_base_addr) + num_bytes;
1748
1749         while (current_address < end_address) {
1750             *((unsigned long*)current_address) = 0x00000000;
1751             current_address += address_increment;
1752         }
1753
1754         mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
1755             SDRAM_CFG0_MCHK_CHK);
1756     }
1757 }
1758
1759 #endif /* CONFIG_440 */
1760
1761 #endif /* CONFIG_SPD_EEPROM */