3 * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
7 * Kenneth Johansson ,Ericsson AB.
8 * kenneth.johansson@etx.ericsson.se
10 * hacked up by bill hunter. fixed so we could run before
11 * serial_init and console_init. previous version avoided this by
12 * running out of cache memory during serial/console init, then running
16 * Jun Gu, Artesyn Technology, jung@artesyncp.com
17 * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
20 * Stefan Roese, DENX Software Engineering, sr@denx.de.
22 * See file CREDITS for list of people who contributed to this
25 * This program is free software; you can redistribute it and/or
26 * modify it under the terms of the GNU General Public License as
27 * published by the Free Software Foundation; either version 2 of
28 * the License, or (at your option) any later version.
30 * This program is distributed in the hope that it will be useful,
31 * but WITHOUT ANY WARRANTY; without even the implied warranty of
32 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
33 * GNU General Public License for more details.
35 * You should have received a copy of the GNU General Public License
36 * along with this program; if not, write to the Free Software
37 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
42 #include <asm/processor.h>
46 #ifdef CONFIG_SPD_EEPROM
52 #define CFG_I2C_SPEED 50000
56 #define CFG_I2C_SLAVE 0xFE
59 #define ONE_BILLION 1000000000
61 #ifndef CONFIG_440 /* for 405 WALNUT/SYCAMORE/BUBINGA boards */
63 #define SDRAM0_CFG_DCE 0x80000000
64 #define SDRAM0_CFG_SRE 0x40000000
65 #define SDRAM0_CFG_PME 0x20000000
66 #define SDRAM0_CFG_MEMCHK 0x10000000
67 #define SDRAM0_CFG_REGEN 0x08000000
68 #define SDRAM0_CFG_ECCDD 0x00400000
69 #define SDRAM0_CFG_EMDULR 0x00200000
70 #define SDRAM0_CFG_DRW_SHIFT (31-6)
71 #define SDRAM0_CFG_BRPF_SHIFT (31-8)
73 #define SDRAM0_TR_CASL_SHIFT (31-8)
74 #define SDRAM0_TR_PTA_SHIFT (31-13)
75 #define SDRAM0_TR_CTP_SHIFT (31-15)
76 #define SDRAM0_TR_LDF_SHIFT (31-17)
77 #define SDRAM0_TR_RFTA_SHIFT (31-29)
78 #define SDRAM0_TR_RCD_SHIFT (31-31)
80 #define SDRAM0_RTR_SHIFT (31-15)
81 #define SDRAM0_ECCCFG_SHIFT (31-11)
83 /* SDRAM0_CFG enable macro */
84 #define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
86 #define SDRAM0_BXCR_SZ_MASK 0x000e0000
87 #define SDRAM0_BXCR_AM_MASK 0x0000e000
89 #define SDRAM0_BXCR_SZ_SHIFT (31-14)
90 #define SDRAM0_BXCR_AM_SHIFT (31-18)
92 #define SDRAM0_BXCR_SZ(x) ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
93 #define SDRAM0_BXCR_AM(x) ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
95 #ifdef CONFIG_SPDDRAM_SILENT
96 # define SPD_ERR(x) do { return 0; } while (0)
98 # define SPD_ERR(x) do { printf(x); return(0); } while (0)
101 #define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
103 /* function prototypes */
104 int spd_read(uint addr);
108 * This function is reading data from the DIMM module EEPROM over the SPD bus
109 * and uses that to program the sdram controller.
111 * This works on boards that has the same schematics that the AMCC walnut has.
113 * Input: null for default I2C spd functions or a pointer to a custom function
114 * returning spd_data.
117 long int spd_sdram(int(read_spd)(uint addr))
120 int total_size,bank_size,bank_code;
125 int sdram0_pmit=0x07c00000;
126 #ifndef CONFIG_405EP /* not on PPC405EP */
129 int sdram0_eccesr=-1;
149 PPC405_SYS_INFO sys_info;
150 unsigned long bus_period_x_10;
155 get_sys_info(&sys_info);
156 bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
161 * Make sure I2C controller is initialized
164 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
167 /* Make shure we are using SDRAM */
168 if (read_spd(2) != 0x04) {
169 SPD_ERR("SDRAM - non SDRAM memory module found\n");
172 /* ------------------------------------------------------------------
173 * configure memory timing register
176 * 27 IN Row Precharge Time ( t RP)
177 * 29 MIN RAS to CAS Delay ( t RCD)
178 * 127 Component and Clock Detail ,clk0-clk3, junction temp, CAS
179 * -------------------------------------------------------------------*/
182 * first figure out which cas latency mode to use
183 * use the min supported mode
186 tmp = read_spd(127) & 0x6;
187 if (tmp == 0x02){ /* only cas = 2 supported */
189 /* t_ck = read_spd(9); */
190 /* t_ac = read_spd(10); */
191 } else if (tmp == 0x04) { /* only cas = 3 supported */
193 /* t_ck = read_spd(9); */
194 /* t_ac = read_spd(10); */
195 } else if (tmp == 0x06) { /* 2,3 supported, so use 2 */
197 /* t_ck = read_spd(23); */
198 /* t_ac = read_spd(24); */
200 SPD_ERR("SDRAM - unsupported CAS latency \n");
203 /* get some timing values, t_rp,t_rcd,t_ras,t_rc
206 t_rcd = read_spd(29);
207 t_ras = read_spd(30);
210 /* The following timing calcs subtract 1 before deviding.
211 * this has effect of using ceiling instead of floor rounding,
212 * and also subtracting 1 to convert number to reg value
215 sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
217 sdram0_tr |= ((((t_rp - 1) * 10)/bus_period_x_10) & 0x3) << SDRAM0_TR_PTA_SHIFT;
219 tmp = (((t_rc - t_rcd - t_rp -1) * 10) / bus_period_x_10) & 0x3;
222 sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;
223 /* set LDF = 2 cycles, reg value = 1 */
224 sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;
225 /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
226 tmp = (((t_rc - 1) * 10) / bus_period_x_10) - 3;
231 sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT;
232 /* set RCD = t_rcd/bus_period*/
233 sdram0_tr |= ((((t_rcd - 1) * 10) / bus_period_x_10) &0x3) << SDRAM0_TR_RCD_SHIFT ;
236 /*------------------------------------------------------------------
237 * configure RTR register
238 * -------------------------------------------------------------------*/
241 tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */
262 SPD_ERR("SDRAM - Bad refresh period \n");
264 /* convert from nsec to bus cycles */
265 tmp = (tmp * 10) / bus_period_x_10;
266 sdram0_rtr = (tmp & 0x3ff8) << SDRAM0_RTR_SHIFT;
268 /*------------------------------------------------------------------
269 * determine the number of banks used
270 * -------------------------------------------------------------------*/
271 /* byte 7:6 is module data width */
272 if (read_spd(7) != 0)
273 SPD_ERR("SDRAM - unsupported module width\n");
276 SPD_ERR("SDRAM - unsupported module width\n");
278 bank_cnt = 1; /* one bank per sdram side */
280 bank_cnt = 2; /* need two banks per side */
282 bank_cnt = 4; /* need four banks per side */
284 SPD_ERR("SDRAM - unsupported module width\n");
286 /* byte 5 is the module row count (refered to as dimm "sides") */
295 bank_cnt = 8; /* 8 is an error code */
297 if (bank_cnt > 4) /* we only have 4 banks to work with */
298 SPD_ERR("SDRAM - unsupported module rows for this width\n");
300 /* now check for ECC ability of module. We only support ECC
301 * on 32 bit wide devices with 8 bit ECC.
303 if ((read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8)) {
304 sdram0_ecccfg = 0xf << SDRAM0_ECCCFG_SHIFT;
311 /*------------------------------------------------------------------
312 * calculate total size
313 * -------------------------------------------------------------------*/
314 /* calculate total size and do sanity check */
316 total_size = 1 << 22; /* total_size = 4MB */
317 /* now multiply 4M by the smallest device row density */
318 /* note that we don't support asymetric rows */
319 while (((tmp & 0x0001) == 0) && (tmp != 0)) {
320 total_size = total_size << 1;
323 total_size *= read_spd(5); /* mult by module rows (dimm sides) */
325 /*------------------------------------------------------------------
326 * map rows * cols * banks to a mode
327 * -------------------------------------------------------------------*/
340 SPD_ERR("SDRAM - unsupported mode\n");
353 SPD_ERR("SDRAM - unsupported mode\n");
363 if (read_spd(17) == 2)
364 mode = 6; /* mode 7 */
366 mode = 2; /* mode 3 */
369 mode = 2; /* mode 3 */
372 SPD_ERR("SDRAM - unsupported mode\n");
376 SPD_ERR("SDRAM - unsupported mode\n");
379 /*------------------------------------------------------------------
380 * using the calculated values, compute the bank
381 * config register values.
382 * -------------------------------------------------------------------*/
387 /* compute the size of each bank */
388 bank_size = total_size / bank_cnt;
389 /* convert bank size to bank size code for ppc4xx
390 by takeing log2(bank_size) - 22 */
391 tmp = bank_size; /* start with tmp = bank_size */
392 bank_code = 0; /* and bank_code = 0 */
393 while (tmp > 1) { /* this takes log2 of tmp */
394 bank_code++; /* and stores result in bank_code */
396 } /* bank_code is now log2(bank_size) */
397 bank_code -= 22; /* subtract 22 to get the code */
399 tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
400 sdram0_b0cr = (bank_size * 0) | tmp;
401 #ifndef CONFIG_405EP /* not on PPC405EP */
403 sdram0_b2cr = (bank_size * 1) | tmp;
405 sdram0_b1cr = (bank_size * 2) | tmp;
407 sdram0_b3cr = (bank_size * 3) | tmp;
409 /* PPC405EP chip only supports two SDRAM banks */
411 sdram0_b1cr = (bank_size * 1) | tmp;
413 total_size = 2 * bank_size;
417 * enable sdram controller DCE=1
418 * enable burst read prefetch to 32 bytes BRPF=2
419 * leave other functions off
422 /*------------------------------------------------------------------
423 * now that we've done our calculations, we are ready to
424 * program all the registers.
425 * -------------------------------------------------------------------*/
427 #define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data)
428 /* disable memcontroller so updates work */
429 mtsdram0( mem_mcopt1, 0 );
431 #ifndef CONFIG_405EP /* not on PPC405EP */
432 mtsdram0( mem_besra , sdram0_besr0 );
433 mtsdram0( mem_besrb , sdram0_besr1 );
434 mtsdram0( mem_ecccf , sdram0_ecccfg );
435 mtsdram0( mem_eccerr, sdram0_eccesr );
437 mtsdram0( mem_rtr , sdram0_rtr );
438 mtsdram0( mem_pmit , sdram0_pmit );
439 mtsdram0( mem_mb0cf , sdram0_b0cr );
440 mtsdram0( mem_mb1cf , sdram0_b1cr );
441 #ifndef CONFIG_405EP /* not on PPC405EP */
442 mtsdram0( mem_mb2cf , sdram0_b2cr );
443 mtsdram0( mem_mb3cf , sdram0_b3cr );
445 mtsdram0( mem_sdtr1 , sdram0_tr );
447 /* SDRAM have a power on delay, 500 micro should do */
449 sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
451 sdram0_cfg |= SDRAM0_CFG_MEMCHK;
452 mtsdram0(mem_mcopt1, sdram0_cfg);
457 int spd_read(uint addr)
461 if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0)
467 #else /* CONFIG_440 */
469 /*-----------------------------------------------------------------------------
470 | Memory Controller Options 0
471 +-----------------------------------------------------------------------------*/
472 #define SDRAM_CFG0_DCEN 0x80000000 /* SDRAM Controller Enable */
473 #define SDRAM_CFG0_MCHK_MASK 0x30000000 /* Memory data errchecking mask */
474 #define SDRAM_CFG0_MCHK_NON 0x00000000 /* No ECC generation */
475 #define SDRAM_CFG0_MCHK_GEN 0x20000000 /* ECC generation */
476 #define SDRAM_CFG0_MCHK_CHK 0x30000000 /* ECC generation and checking */
477 #define SDRAM_CFG0_RDEN 0x08000000 /* Registered DIMM enable */
478 #define SDRAM_CFG0_PMUD 0x04000000 /* Page management unit */
479 #define SDRAM_CFG0_DMWD_MASK 0x02000000 /* DRAM width mask */
480 #define SDRAM_CFG0_DMWD_32 0x00000000 /* 32 bits */
481 #define SDRAM_CFG0_DMWD_64 0x02000000 /* 64 bits */
482 #define SDRAM_CFG0_UIOS_MASK 0x00C00000 /* Unused IO State */
483 #define SDRAM_CFG0_PDP 0x00200000 /* Page deallocation policy */
485 /*-----------------------------------------------------------------------------
486 | Memory Controller Options 1
487 +-----------------------------------------------------------------------------*/
488 #define SDRAM_CFG1_SRE 0x80000000 /* Self-Refresh Entry */
489 #define SDRAM_CFG1_PMEN 0x40000000 /* Power Management Enable */
491 /*-----------------------------------------------------------------------------+
492 | SDRAM DEVPOT Options
493 +-----------------------------------------------------------------------------*/
494 #define SDRAM_DEVOPT_DLL 0x80000000
495 #define SDRAM_DEVOPT_DS 0x40000000
497 /*-----------------------------------------------------------------------------+
498 | SDRAM MCSTS Options
499 +-----------------------------------------------------------------------------*/
500 #define SDRAM_MCSTS_MRSC 0x80000000
501 #define SDRAM_MCSTS_SRMS 0x40000000
502 #define SDRAM_MCSTS_CIS 0x20000000
504 /*-----------------------------------------------------------------------------
505 | SDRAM Refresh Timer Register
506 +-----------------------------------------------------------------------------*/
507 #define SDRAM_RTR_RINT_MASK 0xFFFF0000
508 #define SDRAM_RTR_RINT_ENCODE(n) (((n) << 16) & SDRAM_RTR_RINT_MASK)
509 #define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
511 /*-----------------------------------------------------------------------------+
512 | SDRAM UABus Base Address Reg
513 +-----------------------------------------------------------------------------*/
514 #define SDRAM_UABBA_UBBA_MASK 0x0000000F
516 /*-----------------------------------------------------------------------------+
517 | Memory Bank 0-7 configuration
518 +-----------------------------------------------------------------------------*/
519 #define SDRAM_BXCR_SDBA_MASK 0xff800000 /* Base address */
520 #define SDRAM_BXCR_SDSZ_MASK 0x000e0000 /* Size */
521 #define SDRAM_BXCR_SDSZ_8 0x00020000 /* 8M */
522 #define SDRAM_BXCR_SDSZ_16 0x00040000 /* 16M */
523 #define SDRAM_BXCR_SDSZ_32 0x00060000 /* 32M */
524 #define SDRAM_BXCR_SDSZ_64 0x00080000 /* 64M */
525 #define SDRAM_BXCR_SDSZ_128 0x000a0000 /* 128M */
526 #define SDRAM_BXCR_SDSZ_256 0x000c0000 /* 256M */
527 #define SDRAM_BXCR_SDSZ_512 0x000e0000 /* 512M */
528 #define SDRAM_BXCR_SDAM_MASK 0x0000e000 /* Addressing mode */
529 #define SDRAM_BXCR_SDAM_1 0x00000000 /* Mode 1 */
530 #define SDRAM_BXCR_SDAM_2 0x00002000 /* Mode 2 */
531 #define SDRAM_BXCR_SDAM_3 0x00004000 /* Mode 3 */
532 #define SDRAM_BXCR_SDAM_4 0x00006000 /* Mode 4 */
533 #define SDRAM_BXCR_SDBE 0x00000001 /* Memory Bank Enable */
535 /*-----------------------------------------------------------------------------+
537 +-----------------------------------------------------------------------------*/
538 #define SDRAM_TR0_SDWR_MASK 0x80000000
539 #define SDRAM_TR0_SDWR_2_CLK 0x00000000
540 #define SDRAM_TR0_SDWR_3_CLK 0x80000000
541 #define SDRAM_TR0_SDWD_MASK 0x40000000
542 #define SDRAM_TR0_SDWD_0_CLK 0x00000000
543 #define SDRAM_TR0_SDWD_1_CLK 0x40000000
544 #define SDRAM_TR0_SDCL_MASK 0x01800000
545 #define SDRAM_TR0_SDCL_2_0_CLK 0x00800000
546 #define SDRAM_TR0_SDCL_2_5_CLK 0x01000000
547 #define SDRAM_TR0_SDCL_3_0_CLK 0x01800000
548 #define SDRAM_TR0_SDPA_MASK 0x000C0000
549 #define SDRAM_TR0_SDPA_2_CLK 0x00040000
550 #define SDRAM_TR0_SDPA_3_CLK 0x00080000
551 #define SDRAM_TR0_SDPA_4_CLK 0x000C0000
552 #define SDRAM_TR0_SDCP_MASK 0x00030000
553 #define SDRAM_TR0_SDCP_2_CLK 0x00000000
554 #define SDRAM_TR0_SDCP_3_CLK 0x00010000
555 #define SDRAM_TR0_SDCP_4_CLK 0x00020000
556 #define SDRAM_TR0_SDCP_5_CLK 0x00030000
557 #define SDRAM_TR0_SDLD_MASK 0x0000C000
558 #define SDRAM_TR0_SDLD_1_CLK 0x00000000
559 #define SDRAM_TR0_SDLD_2_CLK 0x00004000
560 #define SDRAM_TR0_SDRA_MASK 0x0000001C
561 #define SDRAM_TR0_SDRA_6_CLK 0x00000000
562 #define SDRAM_TR0_SDRA_7_CLK 0x00000004
563 #define SDRAM_TR0_SDRA_8_CLK 0x00000008
564 #define SDRAM_TR0_SDRA_9_CLK 0x0000000C
565 #define SDRAM_TR0_SDRA_10_CLK 0x00000010
566 #define SDRAM_TR0_SDRA_11_CLK 0x00000014
567 #define SDRAM_TR0_SDRA_12_CLK 0x00000018
568 #define SDRAM_TR0_SDRA_13_CLK 0x0000001C
569 #define SDRAM_TR0_SDRD_MASK 0x00000003
570 #define SDRAM_TR0_SDRD_2_CLK 0x00000001
571 #define SDRAM_TR0_SDRD_3_CLK 0x00000002
572 #define SDRAM_TR0_SDRD_4_CLK 0x00000003
574 /*-----------------------------------------------------------------------------+
576 +-----------------------------------------------------------------------------*/
577 #define SDRAM_TR1_RDSS_MASK 0xC0000000
578 #define SDRAM_TR1_RDSS_TR0 0x00000000
579 #define SDRAM_TR1_RDSS_TR1 0x40000000
580 #define SDRAM_TR1_RDSS_TR2 0x80000000
581 #define SDRAM_TR1_RDSS_TR3 0xC0000000
582 #define SDRAM_TR1_RDSL_MASK 0x00C00000
583 #define SDRAM_TR1_RDSL_STAGE1 0x00000000
584 #define SDRAM_TR1_RDSL_STAGE2 0x00400000
585 #define SDRAM_TR1_RDSL_STAGE3 0x00800000
586 #define SDRAM_TR1_RDCD_MASK 0x00000800
587 #define SDRAM_TR1_RDCD_RCD_0_0 0x00000000
588 #define SDRAM_TR1_RDCD_RCD_1_2 0x00000800
589 #define SDRAM_TR1_RDCT_MASK 0x000001FF
590 #define SDRAM_TR1_RDCT_ENCODE(x) (((x) << 0) & SDRAM_TR1_RDCT_MASK)
591 #define SDRAM_TR1_RDCT_DECODE(x) (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
592 #define SDRAM_TR1_RDCT_MIN 0x00000000
593 #define SDRAM_TR1_RDCT_MAX 0x000001FF
595 /*-----------------------------------------------------------------------------+
596 | SDRAM WDDCTR Options
597 +-----------------------------------------------------------------------------*/
598 #define SDRAM_WDDCTR_WRCP_MASK 0xC0000000
599 #define SDRAM_WDDCTR_WRCP_0DEG 0x00000000
600 #define SDRAM_WDDCTR_WRCP_90DEG 0x40000000
601 #define SDRAM_WDDCTR_WRCP_180DEG 0x80000000
602 #define SDRAM_WDDCTR_DCD_MASK 0x000001FF
604 /*-----------------------------------------------------------------------------+
605 | SDRAM CLKTR Options
606 +-----------------------------------------------------------------------------*/
607 #define SDRAM_CLKTR_CLKP_MASK 0xC0000000
608 #define SDRAM_CLKTR_CLKP_0DEG 0x00000000
609 #define SDRAM_CLKTR_CLKP_90DEG 0x40000000
610 #define SDRAM_CLKTR_CLKP_180DEG 0x80000000
611 #define SDRAM_CLKTR_DCDT_MASK 0x000001FF
613 /*-----------------------------------------------------------------------------+
614 | SDRAM DLYCAL Options
615 +-----------------------------------------------------------------------------*/
616 #define SDRAM_DLYCAL_DLCV_MASK 0x000003FC
617 #define SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
618 #define SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
620 /*-----------------------------------------------------------------------------+
622 +-----------------------------------------------------------------------------*/
623 #define DEFAULT_SPD_ADDR1 0x53
624 #define DEFAULT_SPD_ADDR2 0x52
625 #define MAXBANKS 4 /* at most 4 dimm banks */
626 #define MAX_SPD_BYTES 256
627 #define NUMHALFCYCLES 4
628 #define NUMMEMTESTS 8
629 #define NUMMEMWORDS 8
634 const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
635 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
636 0xFFFFFFFF, 0xFFFFFFFF},
637 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
638 0x00000000, 0x00000000},
639 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
640 0x55555555, 0x55555555},
641 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
642 0xAAAAAAAA, 0xAAAAAAAA},
643 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
644 0x5A5A5A5A, 0x5A5A5A5A},
645 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
646 0xA5A5A5A5, 0xA5A5A5A5},
647 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
648 0x55AA55AA, 0x55AA55AA},
649 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
650 0xAA55AA55, 0xAA55AA55}
654 unsigned char spd_read(uchar chip, uint addr);
656 void get_spd_info(unsigned long* dimm_populated,
657 unsigned char* iic0_dimm_addr,
658 unsigned long num_dimm_banks);
661 (unsigned long* dimm_populated,
662 unsigned char* iic0_dimm_addr,
663 unsigned long num_dimm_banks);
666 (unsigned long* dimm_populated,
667 unsigned char* iic0_dimm_addr,
668 unsigned long num_dimm_banks);
670 void program_cfg0(unsigned long* dimm_populated,
671 unsigned char* iic0_dimm_addr,
672 unsigned long num_dimm_banks);
674 void program_cfg1(unsigned long* dimm_populated,
675 unsigned char* iic0_dimm_addr,
676 unsigned long num_dimm_banks);
678 void program_rtr (unsigned long* dimm_populated,
679 unsigned char* iic0_dimm_addr,
680 unsigned long num_dimm_banks);
682 void program_tr0 (unsigned long* dimm_populated,
683 unsigned char* iic0_dimm_addr,
684 unsigned long num_dimm_banks);
686 void program_tr1 (void);
688 void program_ecc (unsigned long num_bytes);
691 long program_bxcr(unsigned long* dimm_populated,
692 unsigned char* iic0_dimm_addr,
693 unsigned long num_dimm_banks);
696 * This function is reading data from the DIMM module EEPROM over the SPD bus
697 * and uses that to program the sdram controller.
699 * This works on boards that has the same schematics that the AMCC walnut has.
701 * BUG: Don't handle ECC memory
702 * BUG: A few values in the TR register is currently hardcoded
705 long int spd_sdram(void) {
706 unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
707 unsigned long dimm_populated[sizeof(iic0_dimm_addr)];
708 unsigned long total_size;
711 unsigned long num_dimm_banks; /* on board dimm banks */
713 num_dimm_banks = sizeof(iic0_dimm_addr);
716 * Make sure I2C controller is initialized
719 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
722 * Read the SPD information using I2C interface. Check to see if the
723 * DIMM slots are populated.
725 get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
728 * Check the memory type for the dimms plugged.
730 check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
733 * Check the voltage type for the dimms plugged.
735 check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
737 #if defined(CONFIG_440GX)
739 * Soft-reset SDRAM controller.
741 mtsdr(sdr_srst, SDR0_SRST_DMC);
742 mtsdr(sdr_srst, 0x00000000);
746 * program 440GP SDRAM controller options (SDRAM0_CFG0)
748 program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
751 * program 440GP SDRAM controller options (SDRAM0_CFG1)
753 program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
756 * program SDRAM refresh register (SDRAM0_RTR)
758 program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
761 * program SDRAM Timing Register 0 (SDRAM0_TR0)
763 program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
766 * program the BxCR registers to find out total sdram installed
768 total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
772 * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
774 mtsdram(mem_clktr, 0x40000000);
777 * delay to ensure 200 usec has elapsed
782 * enable the memory controller
784 mfsdram(mem_cfg0, cfg0);
785 mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN);
788 * wait for SDRAM_CFG0_DC_EN to complete
791 mfsdram(mem_mcsts, mcsts);
792 if ((mcsts & SDRAM_MCSTS_MRSC) != 0) {
798 * program SDRAM Timing Register 1, adding some delays
803 * if ECC is enabled, initialize parity bits
809 unsigned char spd_read(uchar chip, uint addr) {
810 unsigned char data[2];
812 if (i2c_probe(chip) == 0) {
813 if (i2c_read(chip, addr, 1, data, 1) == 0) {
821 void get_spd_info(unsigned long* dimm_populated,
822 unsigned char* iic0_dimm_addr,
823 unsigned long num_dimm_banks)
825 unsigned long dimm_num;
826 unsigned long dimm_found;
827 unsigned char num_of_bytes;
828 unsigned char total_size;
831 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
835 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
836 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
838 if ((num_of_bytes != 0) && (total_size != 0)) {
839 dimm_populated[dimm_num] = TRUE;
842 printf("DIMM slot %lu: populated\n", dimm_num);
845 dimm_populated[dimm_num] = FALSE;
847 printf("DIMM slot %lu: Not populated\n", dimm_num);
852 #ifndef CONFIG_BAMBOO /* bamboo has onboard DDR _and_ DDR DIMM's */
853 if (dimm_found == FALSE) {
854 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
857 #endif /* CONFIG_BAMBOO */
860 void check_mem_type(unsigned long* dimm_populated,
861 unsigned char* iic0_dimm_addr,
862 unsigned long num_dimm_banks)
864 unsigned long dimm_num;
865 unsigned char dimm_type;
867 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
868 if (dimm_populated[dimm_num] == TRUE) {
869 dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
873 printf("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
877 printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
879 printf("Only DDR SDRAM DIMMs are supported.\n");
880 printf("Replace the DIMM module with a supported DIMM.\n\n");
889 void check_volt_type(unsigned long* dimm_populated,
890 unsigned char* iic0_dimm_addr,
891 unsigned long num_dimm_banks)
893 unsigned long dimm_num;
894 unsigned long voltage_type;
896 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
897 if (dimm_populated[dimm_num] == TRUE) {
898 voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
899 if (voltage_type != 0x04) {
900 printf("ERROR: DIMM %lu with unsupported voltage level.\n",
905 printf("DIMM %lu voltage level supported.\n", dimm_num);
913 void program_cfg0(unsigned long* dimm_populated,
914 unsigned char* iic0_dimm_addr,
915 unsigned long num_dimm_banks)
917 unsigned long dimm_num;
919 unsigned long ecc_enabled;
921 unsigned char attributes;
922 unsigned long data_width;
923 unsigned long dimm_32bit;
924 unsigned long dimm_64bit;
927 * get Memory Controller Options 0 data
929 mfsdram(mem_cfg0, cfg0);
934 cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK |
935 SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
936 SDRAM_CFG0_DMWD_MASK |
937 SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
941 * FIXME: assume the DDR SDRAMs in both banks are the same
944 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
945 if (dimm_populated[dimm_num] == TRUE) {
946 ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
952 * program Registered DIMM Enable
954 attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
955 if ((attributes & 0x02) != 0x00) {
956 cfg0 |= SDRAM_CFG0_RDEN;
960 * program DDR SDRAM Data Width
963 (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
964 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
965 if (data_width == 64 || data_width == 72) {
967 cfg0 |= SDRAM_CFG0_DMWD_64;
968 } else if (data_width == 32 || data_width == 40) {
970 cfg0 |= SDRAM_CFG0_DMWD_32;
972 printf("WARNING: DIMM with datawidth of %lu bits.\n",
974 printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
982 * program Memory Data Error Checking
984 if (ecc_enabled == TRUE) {
985 cfg0 |= SDRAM_CFG0_MCHK_GEN;
987 cfg0 |= SDRAM_CFG0_MCHK_NON;
991 * program Page Management Unit
993 cfg0 |= SDRAM_CFG0_PMUD;
996 * program Memory Controller Options 0
997 * Note: DCEN must be enabled after all DDR SDRAM controller
998 * configuration registers get initialized.
1000 mtsdram(mem_cfg0, cfg0);
1003 void program_cfg1(unsigned long* dimm_populated,
1004 unsigned char* iic0_dimm_addr,
1005 unsigned long num_dimm_banks)
1008 mfsdram(mem_cfg1, cfg1);
1011 * Self-refresh exit, disable PM
1013 cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN);
1016 * program Memory Controller Options 1
1018 mtsdram(mem_cfg1, cfg1);
1021 void program_rtr (unsigned long* dimm_populated,
1022 unsigned char* iic0_dimm_addr,
1023 unsigned long num_dimm_banks)
1025 unsigned long dimm_num;
1026 unsigned long bus_period_x_10;
1027 unsigned long refresh_rate = 0;
1028 unsigned char refresh_rate_type;
1029 unsigned long refresh_interval;
1030 unsigned long sdram_rtr;
1031 PPC440_SYS_INFO sys_info;
1034 * get the board info
1036 get_sys_info(&sys_info);
1037 bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
1040 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1041 if (dimm_populated[dimm_num] == TRUE) {
1042 refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
1043 switch (refresh_rate_type) {
1045 refresh_rate = 15625;
1048 refresh_rate = 15625/4;
1051 refresh_rate = 15625/2;
1054 refresh_rate = 15626*2;
1057 refresh_rate = 15625*4;
1060 refresh_rate = 15625*8;
1063 printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
1065 printf("Replace the DIMM module with a supported DIMM.\n");
1073 refresh_interval = refresh_rate * 10 / bus_period_x_10;
1074 sdram_rtr = (refresh_interval & 0x3ff8) << 16;
1077 * program Refresh Timer Register (SDRAM0_RTR)
1079 mtsdram(mem_rtr, sdram_rtr);
1082 void program_tr0 (unsigned long* dimm_populated,
1083 unsigned char* iic0_dimm_addr,
1084 unsigned long num_dimm_banks)
1086 unsigned long dimm_num;
1088 unsigned char wcsbc;
1089 unsigned char t_rp_ns;
1090 unsigned char t_rcd_ns;
1091 unsigned char t_ras_ns;
1092 unsigned long t_rp_clk;
1093 unsigned long t_ras_rcd_clk;
1094 unsigned long t_rcd_clk;
1095 unsigned long t_rfc_clk;
1096 unsigned long plb_check;
1097 unsigned char cas_bit;
1098 unsigned long cas_index;
1099 unsigned char cas_2_0_available;
1100 unsigned char cas_2_5_available;
1101 unsigned char cas_3_0_available;
1102 unsigned long cycle_time_ns_x_10[3];
1103 unsigned long tcyc_3_0_ns_x_10;
1104 unsigned long tcyc_2_5_ns_x_10;
1105 unsigned long tcyc_2_0_ns_x_10;
1106 unsigned long tcyc_reg;
1107 unsigned long bus_period_x_10;
1108 PPC440_SYS_INFO sys_info;
1109 unsigned long residue;
1112 * get the board info
1114 get_sys_info(&sys_info);
1115 bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
1118 * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
1120 mfsdram(mem_tr0, tr0);
1121 tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
1122 SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
1123 SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
1124 SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
1133 cas_2_0_available = TRUE;
1134 cas_2_5_available = TRUE;
1135 cas_3_0_available = TRUE;
1136 tcyc_2_0_ns_x_10 = 0;
1137 tcyc_2_5_ns_x_10 = 0;
1138 tcyc_3_0_ns_x_10 = 0;
1140 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1141 if (dimm_populated[dimm_num] == TRUE) {
1142 wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
1143 t_rp_ns = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
1144 t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
1145 t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
1146 cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1148 for (cas_index = 0; cas_index < 3; cas_index++) {
1149 switch (cas_index) {
1151 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1154 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1157 tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1161 if ((tcyc_reg & 0x0F) >= 10) {
1162 printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
1167 cycle_time_ns_x_10[cas_index] =
1168 (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
1173 if ((cas_bit & 0x80) != 0) {
1175 } else if ((cas_bit & 0x40) != 0) {
1177 } else if ((cas_bit & 0x20) != 0) {
1181 if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
1182 tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
1185 if (cas_index != 0) {
1188 cas_3_0_available = FALSE;
1191 if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
1192 tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
1195 if (cas_index != 0) {
1198 cas_2_5_available = FALSE;
1201 if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
1202 tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
1205 if (cas_index != 0) {
1208 cas_2_0_available = FALSE;
1216 * Program SD_WR and SD_WCSBC fields
1218 tr0 |= SDRAM_TR0_SDWR_2_CLK; /* Write Recovery: 2 CLK */
1221 tr0 |= SDRAM_TR0_SDWD_0_CLK;
1224 tr0 |= SDRAM_TR0_SDWD_1_CLK;
1229 * Program SD_CASL field
1231 if ((cas_2_0_available == TRUE) &&
1232 (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
1233 tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
1234 } else if ((cas_2_5_available == TRUE) &&
1235 (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
1236 tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
1237 } else if ((cas_3_0_available == TRUE) &&
1238 (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
1239 tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
1241 printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
1242 printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1243 printf("Make sure the PLB speed is within the supported range.\n");
1248 * Calculate Trp in clock cycles and round up if necessary
1249 * Program SD_PTA field
1251 t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION;
1252 plb_check = ONE_BILLION * t_rp_clk / t_rp_ns;
1253 if (sys_info.freqPLB != plb_check) {
1256 switch ((unsigned long)t_rp_clk) {
1260 tr0 |= SDRAM_TR0_SDPA_2_CLK;
1263 tr0 |= SDRAM_TR0_SDPA_3_CLK;
1266 tr0 |= SDRAM_TR0_SDPA_4_CLK;
1271 * Program SD_CTP field
1273 t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION;
1274 plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns);
1275 if (sys_info.freqPLB != plb_check) {
1278 switch (t_ras_rcd_clk) {
1282 tr0 |= SDRAM_TR0_SDCP_2_CLK;
1285 tr0 |= SDRAM_TR0_SDCP_3_CLK;
1288 tr0 |= SDRAM_TR0_SDCP_4_CLK;
1291 tr0 |= SDRAM_TR0_SDCP_5_CLK;
1296 * Program SD_LDF field
1298 tr0 |= SDRAM_TR0_SDLD_2_CLK;
1301 * Program SD_RFTA field
1302 * FIXME tRFC hardcoded as 75 nanoseconds
1304 t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75);
1305 residue = sys_info.freqPLB % (ONE_BILLION / 75);
1306 if (residue >= (ONE_BILLION / 150)) {
1309 switch (t_rfc_clk) {
1317 tr0 |= SDRAM_TR0_SDRA_6_CLK;
1320 tr0 |= SDRAM_TR0_SDRA_7_CLK;
1323 tr0 |= SDRAM_TR0_SDRA_8_CLK;
1326 tr0 |= SDRAM_TR0_SDRA_9_CLK;
1329 tr0 |= SDRAM_TR0_SDRA_10_CLK;
1332 tr0 |= SDRAM_TR0_SDRA_11_CLK;
1335 tr0 |= SDRAM_TR0_SDRA_12_CLK;
1338 tr0 |= SDRAM_TR0_SDRA_13_CLK;
1343 * Program SD_RCD field
1345 t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION;
1346 plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns;
1347 if (sys_info.freqPLB != plb_check) {
1350 switch (t_rcd_clk) {
1354 tr0 |= SDRAM_TR0_SDRD_2_CLK;
1357 tr0 |= SDRAM_TR0_SDRD_3_CLK;
1360 tr0 |= SDRAM_TR0_SDRD_4_CLK;
1365 printf("tr0: %x\n", tr0);
1367 mtsdram(mem_tr0, tr0);
1370 void program_tr1 (void)
1375 unsigned long ecc_temp;
1376 unsigned long dlycal;
1377 unsigned long dly_val;
1378 unsigned long i, j, k;
1379 unsigned long bxcr_num;
1380 unsigned long max_pass_length;
1381 unsigned long current_pass_length;
1382 unsigned long current_fail_length;
1383 unsigned long current_start;
1384 unsigned long rdclt;
1385 unsigned long rdclt_offset;
1389 unsigned char window_found;
1390 unsigned char fail_found;
1391 unsigned char pass_found;
1392 unsigned long * membase;
1393 PPC440_SYS_INFO sys_info;
1396 * get the board info
1398 get_sys_info(&sys_info);
1401 * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
1403 mfsdram(mem_tr1, tr1);
1404 tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
1405 SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
1407 mfsdram(mem_tr0, tr0);
1408 if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
1409 (sys_info.freqPLB > 100000000)) {
1410 tr1 |= SDRAM_TR1_RDSS_TR2;
1411 tr1 |= SDRAM_TR1_RDSL_STAGE3;
1412 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1414 tr1 |= SDRAM_TR1_RDSS_TR1;
1415 tr1 |= SDRAM_TR1_RDSL_STAGE2;
1416 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1420 * save CFG0 ECC setting to a temporary variable and turn ECC off
1422 mfsdram(mem_cfg0, cfg0);
1423 ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
1424 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
1427 * get the delay line calibration register value
1429 mfsdram(mem_dlycal, dlycal);
1430 dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
1432 max_pass_length = 0;
1435 current_pass_length = 0;
1436 current_fail_length = 0;
1439 window_found = FALSE;
1443 printf("Starting memory test ");
1445 for (k = 0; k < NUMHALFCYCLES; k++) {
1446 for (rdclt = 0; rdclt < dly_val; rdclt++) {
1448 * Set the timing reg for the test.
1450 mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
1452 for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
1453 mtdcr(memcfga, mem_b0cr + (bxcr_num<<2));
1454 if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
1455 /* Bank is enabled */
1456 membase = (unsigned long*)
1457 (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
1460 * Run the short memory test
1462 for (i = 0; i < NUMMEMTESTS; i++) {
1463 for (j = 0; j < NUMMEMWORDS; j++) {
1464 membase[j] = test[i][j];
1465 ppcDcbf((unsigned long)&(membase[j]));
1468 for (j = 0; j < NUMMEMWORDS; j++) {
1469 if (membase[j] != test[i][j]) {
1470 ppcDcbf((unsigned long)&(membase[j]));
1473 ppcDcbf((unsigned long)&(membase[j]));
1476 if (j < NUMMEMWORDS) {
1482 * see if the rdclt value passed
1484 if (i < NUMMEMTESTS) {
1490 if (bxcr_num == MAXBXCR) {
1491 if (fail_found == TRUE) {
1493 if (current_pass_length == 0) {
1494 current_start = rdclt_offset + rdclt;
1497 current_fail_length = 0;
1498 current_pass_length++;
1500 if (current_pass_length > max_pass_length) {
1501 max_pass_length = current_pass_length;
1502 max_start = current_start;
1503 max_end = rdclt_offset + rdclt;
1507 current_pass_length = 0;
1508 current_fail_length++;
1510 if (current_fail_length >= (dly_val>>2)) {
1511 if (fail_found == FALSE) {
1513 } else if (pass_found == TRUE) {
1514 window_found = TRUE;
1523 if (window_found == TRUE) {
1527 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1528 rdclt_offset += dly_val;
1535 * make sure we find the window
1537 if (window_found == FALSE) {
1538 printf("ERROR: Cannot determine a common read delay.\n");
1543 * restore the orignal ECC setting
1545 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
1548 * set the SDRAM TR1 RDCD value
1550 tr1 &= ~SDRAM_TR1_RDCD_MASK;
1551 if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) {
1552 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1554 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1558 * set the SDRAM TR1 RDCLT value
1560 tr1 &= ~SDRAM_TR1_RDCT_MASK;
1561 while (max_end >= (dly_val << 1)) {
1562 max_end -= (dly_val << 1);
1563 max_start -= (dly_val << 1);
1566 rdclt_average = ((max_start + max_end) >> 1);
1567 if (rdclt_average >= 0x60)
1571 if (rdclt_average < 0) {
1575 if (rdclt_average >= dly_val) {
1576 rdclt_average -= dly_val;
1577 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1579 tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
1582 printf("tr1: %x\n", tr1);
1585 * program SDRAM Timing Register 1 TR1
1587 mtsdram(mem_tr1, tr1);
1590 unsigned long program_bxcr(unsigned long* dimm_populated,
1591 unsigned char* iic0_dimm_addr,
1592 unsigned long num_dimm_banks)
1594 unsigned long dimm_num;
1595 unsigned long bank_base_addr;
1596 unsigned long bank_size_bytes;
1600 unsigned char num_row_addr;
1601 unsigned char num_col_addr;
1602 unsigned char num_banks;
1603 unsigned char bank_size_id;
1605 #ifndef CONFIG_BAMBOO
1606 unsigned long bxcr_num;
1609 * Set the BxCR regs. First, wipe out the bank config registers.
1611 for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
1612 mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
1613 mtdcr(memcfgd, 0x00000000);
1618 * reset the bank_base address
1620 #ifndef CONFIG_BAMBOO
1621 bank_base_addr = CFG_SDRAM_BASE;
1623 bank_base_addr = CFG_SDRAM_ONBOARD_SIZE;
1626 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1627 if (dimm_populated[dimm_num] == TRUE) {
1628 num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
1629 num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
1630 num_banks = spd_read(iic0_dimm_addr[dimm_num], 5);
1631 bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
1634 * Set the SDRAM0_BxCR regs
1637 bank_size_bytes = 4 * 1024 * 1024 * bank_size_id;
1638 switch (bank_size_id) {
1640 cr |= SDRAM_BXCR_SDSZ_8;
1643 cr |= SDRAM_BXCR_SDSZ_16;
1646 cr |= SDRAM_BXCR_SDSZ_32;
1649 cr |= SDRAM_BXCR_SDSZ_64;
1652 cr |= SDRAM_BXCR_SDSZ_128;
1655 cr |= SDRAM_BXCR_SDSZ_256;
1658 cr |= SDRAM_BXCR_SDSZ_512;
1661 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1663 printf("ERROR: Unsupported value for the banksize: %d.\n",
1665 printf("Replace the DIMM module with a supported DIMM.\n\n");
1669 switch (num_col_addr) {
1671 cr |= SDRAM_BXCR_SDAM_1;
1674 cr |= SDRAM_BXCR_SDAM_2;
1677 cr |= SDRAM_BXCR_SDAM_3;
1680 cr |= SDRAM_BXCR_SDAM_4;
1683 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1685 printf("ERROR: Unsupported value for number of "
1686 "column addresses: %d.\n", num_col_addr);
1687 printf("Replace the DIMM module with a supported DIMM.\n\n");
1694 cr |= SDRAM_BXCR_SDBE;
1696 /*------------------------------------------------------------------
1697 | This next section is hardware dependent and must be programmed
1698 | to match the hardware.
1699 +-----------------------------------------------------------------*/
1700 if (dimm_num == 0) {
1701 for (i = 0; i < num_banks; i++) {
1702 #ifndef CONFIG_BAMBOO
1703 mtdcr(memcfga, mem_b0cr + (i << 2));
1705 mtdcr(memcfga, mem_b1cr + (i << 2));
1707 temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
1708 SDRAM_BXCR_SDSZ_MASK |
1709 SDRAM_BXCR_SDAM_MASK |
1712 cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
1714 bank_base_addr += bank_size_bytes;
1717 for (i = 0; i < num_banks; i++) {
1718 #ifndef CONFIG_BAMBOO
1719 mtdcr(memcfga, mem_b2cr + (i << 2));
1721 mtdcr(memcfga, mem_b3cr + (i << 2));
1723 temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
1724 SDRAM_BXCR_SDSZ_MASK |
1725 SDRAM_BXCR_SDAM_MASK |
1728 cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
1730 bank_base_addr += bank_size_bytes;
1736 return(bank_base_addr);
1739 void program_ecc (unsigned long num_bytes)
1741 unsigned long bank_base_addr;
1742 unsigned long current_address;
1743 unsigned long end_address;
1744 unsigned long address_increment;
1748 * get Memory Controller Options 0 data
1750 mfsdram(mem_cfg0, cfg0);
1753 * reset the bank_base address
1755 bank_base_addr = CFG_SDRAM_BASE;
1757 if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) {
1758 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
1759 SDRAM_CFG0_MCHK_GEN);
1761 if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) {
1762 address_increment = 4;
1764 address_increment = 8;
1767 current_address = (unsigned long)(bank_base_addr);
1768 end_address = (unsigned long)(bank_base_addr) + num_bytes;
1770 while (current_address < end_address) {
1771 *((unsigned long*)current_address) = 0x00000000;
1772 current_address += address_increment;
1775 mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
1776 SDRAM_CFG0_MCHK_CHK);
1780 #endif /* CONFIG_440 */
1782 #endif /* CONFIG_SPD_EEPROM */