cpu/ppc4xx/spd_sdram.c

   1 /*
   2  * (C) Copyright 2001
   3  * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
   4  *
   5  * Based on code by:
   6  *
   7  * Kenneth Johansson ,Ericsson AB.
   8  * kenneth.johansson@etx.ericsson.se
   9  *
  10  * hacked up by bill hunter. fixed so we could run before
  11  * serial_init and console_init. previous version avoided this by
  12  * running out of cache memory during serial/console init, then running
  13  * this code later.
  14  *
  15  * (C) Copyright 2002
  16  * Jun Gu, Artesyn Technology, jung@artesyncp.com
  17  * Support for IBM 440 based on OpenBIOS draminit.c from IBM.
  18  *
  19  * See file CREDITS for list of people who contributed to this
  20  * project.
  21  *
  22  * This program is free software; you can redistribute it and/or
  23  * modify it under the terms of the GNU General Public License as
  24  * published by the Free Software Foundation; either version 2 of
  25  * the License, or (at your option) any later version.
  26  *
  27  * This program is distributed in the hope that it will be useful,
  28  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  29  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  30  * GNU General Public License for more details.
  31  *
  32  * You should have received a copy of the GNU General Public License
  33  * along with this program; if not, write to the Free Software
  34  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  35  * MA 02111-1307 USA
  36  */
  37
  38 #include <common.h>
  39 #include <asm/processor.h>
  40 #include <i2c.h>
  41 #include <ppc4xx.h>
  42
  43 #ifdef CONFIG_SPD_EEPROM
  44
  45 /*
  46  * Set default values
  47  */
  48 #ifndef CFG_I2C_SPEED
  49 #define CFG_I2C_SPEED   50000
  50 #endif
  51
  52 #ifndef CFG_I2C_SLAVE
  53 #define CFG_I2C_SLAVE   0xFE
  54 #endif
  55
  56 #ifndef  CONFIG_440              /* for 405 WALNUT board */
  57
  58 #define  SDRAM0_CFG_DCE          0x80000000
  59 #define  SDRAM0_CFG_SRE          0x40000000
  60 #define  SDRAM0_CFG_PME          0x20000000
  61 #define  SDRAM0_CFG_MEMCHK       0x10000000
  62 #define  SDRAM0_CFG_REGEN        0x08000000
  63 #define  SDRAM0_CFG_ECCDD        0x00400000
  64 #define  SDRAM0_CFG_EMDULR       0x00200000
  65 #define  SDRAM0_CFG_DRW_SHIFT    (31-6)
  66 #define  SDRAM0_CFG_BRPF_SHIFT   (31-8)
  67
  68 #define  SDRAM0_TR_CASL_SHIFT    (31-8)
  69 #define  SDRAM0_TR_PTA_SHIFT     (31-13)
  70 #define  SDRAM0_TR_CTP_SHIFT     (31-15)
  71 #define  SDRAM0_TR_LDF_SHIFT     (31-17)
  72 #define  SDRAM0_TR_RFTA_SHIFT    (31-29)
  73 #define  SDRAM0_TR_RCD_SHIFT     (31-31)
  74
  75 #define  SDRAM0_RTR_SHIFT        (31-15)
  76 #define  SDRAM0_ECCCFG_SHIFT     (31-11)
  77
  78 /* SDRAM0_CFG enable macro  */
  79 #define SDRAM0_CFG_BRPF(x) ( ( x & 0x3)<< SDRAM0_CFG_BRPF_SHIFT )
  80
  81 #define SDRAM0_BXCR_SZ_MASK  0x000e0000
  82 #define SDRAM0_BXCR_AM_MASK  0x0000e000
  83
  84 #define SDRAM0_BXCR_SZ_SHIFT (31-14)
  85 #define SDRAM0_BXCR_AM_SHIFT (31-18)
  86
  87 #define SDRAM0_BXCR_SZ(x)  ( (( x << SDRAM0_BXCR_SZ_SHIFT) & SDRAM0_BXCR_SZ_MASK) )
  88 #define SDRAM0_BXCR_AM(x)  ( (( x << SDRAM0_BXCR_AM_SHIFT) & SDRAM0_BXCR_AM_MASK) )
  89
  90 #ifdef CONFIG_SPDDRAM_SILENT
  91 # define SPD_ERR(x) do { return 0; } while (0)
  92 #else
  93 # define SPD_ERR(x) do { printf(x); return(0); } while (0)
  94 #endif
  95
  96 #define sdram_HZ_to_ns(hertz) (1000000000/(hertz))
  97
  98 /* function prototypes */
  99 int spd_read(uint addr);
 100
 101
 102 /*
 103  * This function is reading data from the DIMM module EEPROM over the SPD bus
 104  * and uses that to program the sdram controller.
 105  *
 106  * This works on boards that has the same schematics that the IBM walnut has.
 107  *
 108  * Input: null for default I2C spd functions or a pointer to a custom function
 109  * returning spd_data.
 110  */
 111
 112 long int spd_sdram(int(read_spd)(uint addr))
 113 {
 114         int bus_period,tmp,row,col;
 115         int total_size,bank_size,bank_code;
 116         int ecc_on;
 117         int mode;
 118         int bank_cnt;
 119
 120         int sdram0_pmit=0x07c00000;
 121 #ifndef CONFIG_405EP /* not on PPC405EP */
 122         int sdram0_besr0=-1;
 123         int sdram0_besr1=-1;
 124         int sdram0_eccesr=-1;
 125 #endif
 126         int sdram0_ecccfg;
 127
 128         int sdram0_rtr=0;
 129         int sdram0_tr=0;
 130
 131         int sdram0_b0cr;
 132         int sdram0_b1cr;
 133         int sdram0_b2cr;
 134         int sdram0_b3cr;
 135
 136         int sdram0_cfg=0;
 137
 138         int t_rp;
 139         int t_rcd;
 140         int t_ras;
 141         int t_rc;
 142         int min_cas;
 143
 144         if(read_spd == 0){
 145                 read_spd=spd_read;
 146         /*
 147          * Make sure I2C controller is initialized
 148          * before continuing.
 149          */
 150                 i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 151         }
 152
 153
 154         /*
 155          * Calculate the bus period, we do it this
 156          * way to minimize stack utilization.
 157          */
 158 #ifndef CONFIG_405EP
 159         tmp = (mfdcr(pllmd) >> (31-6)) & 0xf;   /* get FBDV bits */
 160         tmp = CONFIG_SYS_CLK_FREQ * tmp;        /* get plb freq */
 161 #else
 162         {
 163                 unsigned long freqCPU;
 164                 unsigned long pllmr0;
 165                 unsigned long pllmr1;
 166                 unsigned long pllFbkDiv;
 167                 unsigned long pllPlbDiv;
 168                 unsigned long pllmr0_ccdv;
 169
 170                 /*
 171                  * Read PLL Mode registers
 172                  */
 173                 pllmr0 = mfdcr (cpc0_pllmr0);
 174                 pllmr1 = mfdcr (cpc0_pllmr1);
 175
 176                 pllFbkDiv = ((pllmr1 & PLLMR1_FBMUL_MASK) >> 20);
 177                 if (pllFbkDiv == 0) {
 178                         pllFbkDiv = 16;
 179                 }
 180                 pllPlbDiv = ((pllmr0 & PLLMR0_CPU_TO_PLB_MASK) >> 16) + 1;
 181
 182                 /*
 183                  * Determine CPU clock frequency
 184                  */
 185                 pllmr0_ccdv = ((pllmr0 & PLLMR0_CPU_DIV_MASK) >> 20) + 1;
 186                 if (pllmr1 & PLLMR1_SSCS_MASK) {
 187                         freqCPU = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / pllmr0_ccdv;
 188                 } else {
 189                         freqCPU = CONFIG_SYS_CLK_FREQ / pllmr0_ccdv;
 190                 }
 191
 192                 /*
 193                  * Determine PLB clock frequency
 194                  */
 195                 tmp = freqCPU / pllPlbDiv;
 196         }
 197 #endif
 198         bus_period = sdram_HZ_to_ns(tmp);       /* get sdram speed */
 199
 200         /* Make shure we are using SDRAM */
 201         if (read_spd(2) != 0x04){
 202           SPD_ERR("SDRAM - non SDRAM memory module found\n");
 203           }
 204
 205 /*------------------------------------------------------------------
 206   configure memory timing register
 207
 208   data from DIMM:
 209   27    IN Row Precharge Time ( t RP)
 210   29    MIN RAS to CAS Delay ( t RCD)
 211   127   Component and Clock Detail ,clk0-clk3, junction temp, CAS
 212   -------------------------------------------------------------------*/
 213
 214      /*
 215       * first figure out which cas latency mode to use
 216       * use the min supported mode
 217       */
 218
 219         tmp = read_spd(127) & 0x6;
 220      if(tmp == 0x02){              /* only cas = 2 supported */
 221           min_cas = 2;
 222 /*        t_ck = read_spd(9); */
 223 /*        t_ac = read_spd(10); */
 224           }
 225      else if (tmp == 0x04){         /* only cas = 3 supported */
 226           min_cas = 3;
 227 /*        t_ck = read_spd(9); */
 228 /*        t_ac = read_spd(10); */
 229           }
 230      else if (tmp == 0x06){         /* 2,3 supported, so use 2 */
 231           min_cas = 2;
 232 /*        t_ck = read_spd(23); */
 233 /*        t_ac = read_spd(24); */
 234           }
 235      else {
 236              SPD_ERR("SDRAM - unsupported CAS latency \n");
 237         }
 238
 239      /* get some timing values, t_rp,t_rcd,t_ras,t_rc
 240      */
 241      t_rp = read_spd(27);
 242      t_rcd = read_spd(29);
 243      t_ras = read_spd(30);
 244      t_rc = t_ras + t_rp;
 245
 246      /* The following timing calcs subtract 1 before deviding.
 247       * this has effect of using ceiling instead of floor rounding,
 248       * and also subtracting 1 to convert number to reg value
 249       */
 250      /* set up CASL */
 251      sdram0_tr = (min_cas - 1) << SDRAM0_TR_CASL_SHIFT;
 252      /* set up PTA */
 253      sdram0_tr |= (((t_rp - 1)/bus_period) & 0x3) << SDRAM0_TR_PTA_SHIFT;
 254      /* set up CTP */
 255      tmp = ((t_rc - t_rcd - t_rp -1) / bus_period) & 0x3;
 256      if(tmp<1) tmp=1;
 257      sdram0_tr |= tmp << SDRAM0_TR_CTP_SHIFT;
 258      /* set LDF = 2 cycles, reg value = 1 */
 259      sdram0_tr |= 1 << SDRAM0_TR_LDF_SHIFT;
 260      /* set RFTA = t_rfc/bus_period, use t_rfc = t_rc */
 261         tmp = ( (t_rc - 1) / bus_period)-3;
 262         if(tmp<0)tmp=0;
 263         if(tmp>6)tmp=6;
 264         sdram0_tr |= tmp << SDRAM0_TR_RFTA_SHIFT;
 265      /* set RCD = t_rcd/bus_period*/
 266      sdram0_tr |= (((t_rcd - 1) / bus_period) &0x3) << SDRAM0_TR_RCD_SHIFT ;
 267
 268
 269 /*------------------------------------------------------------------
 270   configure RTR register
 271   -------------------------------------------------------------------*/
 272      row = read_spd(3);
 273      col = read_spd(4);
 274      tmp = read_spd(12) & 0x7f ; /* refresh type less self refresh bit */
 275      switch(tmp){
 276         case 0x00:
 277           tmp=15625;
 278           break;
 279         case 0x01:
 280           tmp=15625/4;
 281           break;
 282         case 0x02:
 283           tmp=15625/2;
 284           break;
 285         case 0x03:
 286           tmp=15625*2;
 287           break;
 288         case 0x04:
 289           tmp=15625*4;
 290           break;
 291         case 0x05:
 292           tmp=15625*8;
 293           break;
 294         default:
 295           SPD_ERR("SDRAM - Bad refresh period \n");
 296         }
 297         /* convert from nsec to bus cycles */
 298         tmp = tmp/bus_period;
 299         sdram0_rtr = (tmp & 0x3ff8)<<  SDRAM0_RTR_SHIFT;
 300
 301 /*------------------------------------------------------------------
 302   determine the number of banks used
 303   -------------------------------------------------------------------*/
 304         /* byte 7:6 is module data width */
 305         if(read_spd(7) != 0)
 306             SPD_ERR("SDRAM - unsupported module width\n");
 307         tmp = read_spd(6);
 308         if (tmp < 32)
 309             SPD_ERR("SDRAM - unsupported module width\n");
 310         else if (tmp < 64)
 311             bank_cnt=1;         /* one bank per sdram side */
 312         else if (tmp < 73)
 313             bank_cnt=2; /* need two banks per side */
 314         else if (tmp < 161)
 315             bank_cnt=4; /* need four banks per side */
 316         else
 317             SPD_ERR("SDRAM - unsupported module width\n");
 318
 319         /* byte 5 is the module row count (refered to as dimm "sides") */
 320         tmp = read_spd(5);
 321         if(tmp==1);
 322         else if(tmp==2) bank_cnt *=2;
 323         else if(tmp==4) bank_cnt *=4;
 324         else bank_cnt = 8;              /* 8 is an error code */
 325
 326         if(bank_cnt > 4)        /* we only have 4 banks to work with */
 327             SPD_ERR("SDRAM - unsupported module rows for this width\n");
 328
 329         /* now check for ECC ability of module. We only support ECC
 330          *   on 32 bit wide devices with 8 bit ECC.
 331          */
 332         if ( (read_spd(11)==2) && (read_spd(6)==40) && (read_spd(14)==8) ){
 333            sdram0_ecccfg=0xf<<SDRAM0_ECCCFG_SHIFT;
 334            ecc_on = 1;
 335         }
 336         else{
 337            sdram0_ecccfg=0;
 338            ecc_on = 0;
 339         }
 340
 341 /*------------------------------------------------------------------
 342         calculate total size
 343   -------------------------------------------------------------------*/
 344         /* calculate total size and do sanity check */
 345         tmp = read_spd(31);
 346         total_size=1<<22;       /* total_size = 4MB */
 347         /* now multiply 4M by the smallest device row density */
 348         /* note that we don't support asymetric rows */
 349         while (((tmp & 0x0001) == 0) && (tmp != 0)){
 350             total_size= total_size<<1;
 351             tmp = tmp>>1;
 352             }
 353         total_size *= read_spd(5);      /* mult by module rows (dimm sides) */
 354
 355 /*------------------------------------------------------------------
 356         map  rows * cols * banks to a mode
 357  -------------------------------------------------------------------*/
 358
 359         switch( row )
 360         {
 361         case 11:
 362                 switch ( col )
 363                 {
 364                 case 8:
 365                         mode=4; /* mode 5 */
 366                         break;
 367                 case 9:
 368                 case 10:
 369                         mode=0; /* mode 1 */
 370                         break;
 371                 default:
 372                 SPD_ERR("SDRAM - unsupported mode\n");
 373                 }
 374                 break;
 375         case 12:
 376                 switch ( col )
 377                 {
 378                 case 8:
 379                         mode=3; /* mode 4 */
 380                         break;
 381                 case 9:
 382                 case 10:
 383                         mode=1; /* mode 2 */
 384                         break;
 385                 default:
 386                 SPD_ERR("SDRAM - unsupported mode\n");
 387                 }
 388                 break;
 389         case 13:
 390                 switch ( col )
 391                 {
 392                 case 8:
 393                         mode=5; /* mode 6 */
 394                         break;
 395                 case 9:
 396                 case 10:
 397                         if (read_spd(17) ==2 )
 398                                 mode=6; /* mode 7 */
 399                         else
 400                                 mode=2; /* mode 3 */
 401                         break;
 402                 case 11:
 403                         mode=2; /* mode 3 */
 404                         break;
 405                 default:
 406                 SPD_ERR("SDRAM - unsupported mode\n");
 407                 }
 408                 break;
 409         default:
 410              SPD_ERR("SDRAM - unsupported mode\n");
 411         }
 412
 413 /*------------------------------------------------------------------
 414         using the calculated values, compute the bank
 415         config register values.
 416  -------------------------------------------------------------------*/
 417         sdram0_b1cr = 0;
 418         sdram0_b2cr = 0;
 419         sdram0_b3cr = 0;
 420
 421         /* compute the size of each bank */
 422         bank_size = total_size / bank_cnt;
 423         /* convert bank size to bank size code for ppc4xx
 424                 by takeing log2(bank_size) - 22 */
 425         tmp=bank_size;          /* start with tmp = bank_size */
 426         bank_code=0;                    /* and bank_code = 0 */
 427         while (tmp>1){          /* this takes log2 of tmp */
 428                 bank_code++;            /* and stores result in bank_code */
 429                 tmp=tmp>>1;
 430                 }                               /* bank_code is now log2(bank_size) */
 431         bank_code-=22;                          /* subtract 22 to get the code */
 432
 433         tmp = SDRAM0_BXCR_SZ(bank_code) | SDRAM0_BXCR_AM(mode) | 1;
 434         sdram0_b0cr = (bank_size) * 0 | tmp;
 435 #ifndef CONFIG_405EP /* not on PPC405EP */
 436         if(bank_cnt>1) sdram0_b2cr = (bank_size) * 1 | tmp;
 437         if(bank_cnt>2) sdram0_b1cr = (bank_size) * 2 | tmp;
 438         if(bank_cnt>3) sdram0_b3cr = (bank_size) * 3 | tmp;
 439 #else
 440         /* PPC405EP chip only supports two SDRAM banks */
 441         if(bank_cnt>1) sdram0_b1cr = (bank_size) * 1 | tmp;
 442         if(bank_cnt>2) total_size -= (bank_size) * (bank_cnt - 2);
 443 #endif
 444
 445
 446         /*
 447          *   enable sdram controller DCE=1
 448          *  enable burst read prefetch to 32 bytes BRPF=2
 449          *  leave other functions off
 450          */
 451
 452 /*------------------------------------------------------------------
 453         now that we've done our calculations, we are ready to
 454         program all the registers.
 455  -------------------------------------------------------------------*/
 456
 457
 458 #define mtsdram0(reg, data)  mtdcr(memcfga,reg);mtdcr(memcfgd,data)
 459         /* disable memcontroller so updates work */
 460         sdram0_cfg = 0;
 461         mtsdram0( mem_mcopt1, sdram0_cfg );
 462
 463 #ifndef CONFIG_405EP /* not on PPC405EP */
 464         mtsdram0( mem_besra , sdram0_besr0 );
 465         mtsdram0( mem_besrb , sdram0_besr1 );
 466         mtsdram0( mem_ecccf , sdram0_ecccfg );
 467         mtsdram0( mem_eccerr, sdram0_eccesr );
 468 #endif
 469         mtsdram0( mem_rtr   , sdram0_rtr );
 470         mtsdram0( mem_pmit  , sdram0_pmit );
 471         mtsdram0( mem_mb0cf , sdram0_b0cr );
 472         mtsdram0( mem_mb1cf , sdram0_b1cr );
 473 #ifndef CONFIG_405EP /* not on PPC405EP */
 474         mtsdram0( mem_mb2cf , sdram0_b2cr );
 475         mtsdram0( mem_mb3cf , sdram0_b3cr );
 476 #endif
 477         mtsdram0( mem_sdtr1 , sdram0_tr );
 478
 479         /* SDRAM have a power on delay,  500 micro should do */
 480         udelay(500);
 481         sdram0_cfg = SDRAM0_CFG_DCE | SDRAM0_CFG_BRPF(1) | SDRAM0_CFG_ECCDD | SDRAM0_CFG_EMDULR;
 482         if(ecc_on) sdram0_cfg |= SDRAM0_CFG_MEMCHK;
 483         mtsdram0( mem_mcopt1, sdram0_cfg );
 484
 485
 486         /* kernel 2.4.2 from mvista has a bug with memory over 128MB */
 487 #ifdef MVISTA_MEM_BUG
 488         if (total_size > 128*1024*1024 )
 489                 total_size=128*1024*1024;
 490 #endif
 491         return (total_size);
 492 }
 493
 494 int spd_read(uint addr)
 495 {
 496         char data[2];
 497
 498         if (i2c_read(SPD_EEPROM_ADDRESS, addr, 1, data, 1) == 0)
 499                 return (int)data[0];
 500         else
 501                 return 0;
 502 }
 503
 504 #else                             /* CONFIG_440 */
 505
 506 /*-----------------------------------------------------------------------------
 507 |  Memory Controller Options 0
 508 +-----------------------------------------------------------------------------*/
 509 #define SDRAM_CFG0_DCEN           0x80000000  /* SDRAM Controller Enable      */
 510 #define SDRAM_CFG0_MCHK_MASK      0x30000000  /* Memory data errchecking mask */
 511 #define SDRAM_CFG0_MCHK_NON       0x00000000  /* No ECC generation            */
 512 #define SDRAM_CFG0_MCHK_GEN       0x20000000  /* ECC generation               */
 513 #define SDRAM_CFG0_MCHK_CHK       0x30000000  /* ECC generation and checking  */
 514 #define SDRAM_CFG0_RDEN           0x08000000  /* Registered DIMM enable       */
 515 #define SDRAM_CFG0_PMUD           0x04000000  /* Page management unit         */
 516 #define SDRAM_CFG0_DMWD_MASK      0x02000000  /* DRAM width mask              */
 517 #define SDRAM_CFG0_DMWD_32        0x00000000  /* 32 bits                      */
 518 #define SDRAM_CFG0_DMWD_64        0x02000000  /* 64 bits                      */
 519 #define SDRAM_CFG0_UIOS_MASK      0x00C00000  /* Unused IO State              */
 520 #define SDRAM_CFG0_PDP            0x00200000  /* Page deallocation policy     */
 521
 522 /*-----------------------------------------------------------------------------
 523 |  Memory Controller Options 1
 524 +-----------------------------------------------------------------------------*/
 525 #define SDRAM_CFG1_SRE            0x80000000  /* Self-Refresh Entry           */
 526 #define SDRAM_CFG1_PMEN           0x40000000  /* Power Management Enable      */
 527
 528 /*-----------------------------------------------------------------------------+
 529 |  SDRAM DEVPOT Options
 530 +-----------------------------------------------------------------------------*/
 531 #define SDRAM_DEVOPT_DLL          0x80000000
 532 #define SDRAM_DEVOPT_DS           0x40000000
 533
 534 /*-----------------------------------------------------------------------------+
 535 |  SDRAM MCSTS Options
 536 +-----------------------------------------------------------------------------*/
 537 #define SDRAM_MCSTS_MRSC          0x80000000
 538 #define SDRAM_MCSTS_SRMS          0x40000000
 539 #define SDRAM_MCSTS_CIS           0x20000000
 540
 541 /*-----------------------------------------------------------------------------
 542 |  SDRAM Refresh Timer Register
 543 +-----------------------------------------------------------------------------*/
 544 #define SDRAM_RTR_RINT_MASK       0xFFFF0000
 545 #define SDRAM_RTR_RINT_ENCODE(n)  (((n) << 16) & SDRAM_RTR_RINT_MASK)
 546 #define sdram_HZ_to_ns(hertz)     (1000000000/(hertz))
 547
 548 /*-----------------------------------------------------------------------------+
 549 |  SDRAM UABus Base Address Reg
 550 +-----------------------------------------------------------------------------*/
 551 #define SDRAM_UABBA_UBBA_MASK     0x0000000F
 552
 553 /*-----------------------------------------------------------------------------+
 554 |  Memory Bank 0-7 configuration
 555 +-----------------------------------------------------------------------------*/
 556 #define SDRAM_BXCR_SDBA_MASK      0xff800000      /* Base address             */
 557 #define SDRAM_BXCR_SDSZ_MASK      0x000e0000      /* Size                     */
 558 #define SDRAM_BXCR_SDSZ_8         0x00020000      /*   8M                     */
 559 #define SDRAM_BXCR_SDSZ_16        0x00040000      /*  16M                     */
 560 #define SDRAM_BXCR_SDSZ_32        0x00060000      /*  32M                     */
 561 #define SDRAM_BXCR_SDSZ_64        0x00080000      /*  64M                     */
 562 #define SDRAM_BXCR_SDSZ_128       0x000a0000      /* 128M                     */
 563 #define SDRAM_BXCR_SDSZ_256       0x000c0000      /* 256M                     */
 564 #define SDRAM_BXCR_SDSZ_512       0x000e0000      /* 512M                     */
 565 #define SDRAM_BXCR_SDAM_MASK      0x0000e000      /* Addressing mode          */
 566 #define SDRAM_BXCR_SDAM_1         0x00000000      /*   Mode 1                 */
 567 #define SDRAM_BXCR_SDAM_2         0x00002000      /*   Mode 2                 */
 568 #define SDRAM_BXCR_SDAM_3         0x00004000      /*   Mode 3                 */
 569 #define SDRAM_BXCR_SDAM_4         0x00006000      /*   Mode 4                 */
 570 #define SDRAM_BXCR_SDBE           0x00000001      /* Memory Bank Enable       */
 571
 572 /*-----------------------------------------------------------------------------+
 573 |  SDRAM TR0 Options
 574 +-----------------------------------------------------------------------------*/
 575 #define SDRAM_TR0_SDWR_MASK       0x80000000
 576 #define   SDRAM_TR0_SDWR_2_CLK    0x00000000
 577 #define   SDRAM_TR0_SDWR_3_CLK    0x80000000
 578 #define SDRAM_TR0_SDWD_MASK       0x40000000
 579 #define   SDRAM_TR0_SDWD_0_CLK    0x00000000
 580 #define   SDRAM_TR0_SDWD_1_CLK    0x40000000
 581 #define SDRAM_TR0_SDCL_MASK       0x01800000
 582 #define   SDRAM_TR0_SDCL_2_0_CLK  0x00800000
 583 #define   SDRAM_TR0_SDCL_2_5_CLK  0x01000000
 584 #define   SDRAM_TR0_SDCL_3_0_CLK  0x01800000
 585 #define SDRAM_TR0_SDPA_MASK       0x000C0000
 586 #define   SDRAM_TR0_SDPA_2_CLK    0x00040000
 587 #define   SDRAM_TR0_SDPA_3_CLK    0x00080000
 588 #define   SDRAM_TR0_SDPA_4_CLK    0x000C0000
 589 #define SDRAM_TR0_SDCP_MASK       0x00030000
 590 #define   SDRAM_TR0_SDCP_2_CLK    0x00000000
 591 #define   SDRAM_TR0_SDCP_3_CLK    0x00010000
 592 #define   SDRAM_TR0_SDCP_4_CLK    0x00020000
 593 #define   SDRAM_TR0_SDCP_5_CLK    0x00030000
 594 #define SDRAM_TR0_SDLD_MASK       0x0000C000
 595 #define   SDRAM_TR0_SDLD_1_CLK    0x00000000
 596 #define   SDRAM_TR0_SDLD_2_CLK    0x00004000
 597 #define SDRAM_TR0_SDRA_MASK       0x0000001C
 598 #define   SDRAM_TR0_SDRA_6_CLK    0x00000000
 599 #define   SDRAM_TR0_SDRA_7_CLK    0x00000004
 600 #define   SDRAM_TR0_SDRA_8_CLK    0x00000008
 601 #define   SDRAM_TR0_SDRA_9_CLK    0x0000000C
 602 #define   SDRAM_TR0_SDRA_10_CLK   0x00000010
 603 #define   SDRAM_TR0_SDRA_11_CLK   0x00000014
 604 #define   SDRAM_TR0_SDRA_12_CLK   0x00000018
 605 #define   SDRAM_TR0_SDRA_13_CLK   0x0000001C
 606 #define SDRAM_TR0_SDRD_MASK       0x00000003
 607 #define   SDRAM_TR0_SDRD_2_CLK    0x00000001
 608 #define   SDRAM_TR0_SDRD_3_CLK    0x00000002
 609 #define   SDRAM_TR0_SDRD_4_CLK    0x00000003
 610
 611 /*-----------------------------------------------------------------------------+
 612 |  SDRAM TR1 Options
 613 +-----------------------------------------------------------------------------*/
 614 #define SDRAM_TR1_RDSS_MASK         0xC0000000
 615 #define   SDRAM_TR1_RDSS_TR0        0x00000000
 616 #define   SDRAM_TR1_RDSS_TR1        0x40000000
 617 #define   SDRAM_TR1_RDSS_TR2        0x80000000
 618 #define   SDRAM_TR1_RDSS_TR3        0xC0000000
 619 #define SDRAM_TR1_RDSL_MASK         0x00C00000
 620 #define   SDRAM_TR1_RDSL_STAGE1     0x00000000
 621 #define   SDRAM_TR1_RDSL_STAGE2     0x00400000
 622 #define   SDRAM_TR1_RDSL_STAGE3     0x00800000
 623 #define SDRAM_TR1_RDCD_MASK         0x00000800
 624 #define   SDRAM_TR1_RDCD_RCD_0_0    0x00000000
 625 #define   SDRAM_TR1_RDCD_RCD_1_2    0x00000800
 626 #define SDRAM_TR1_RDCT_MASK         0x000001FF
 627 #define   SDRAM_TR1_RDCT_ENCODE(x)  (((x) << 0) & SDRAM_TR1_RDCT_MASK)
 628 #define   SDRAM_TR1_RDCT_DECODE(x)  (((x) & SDRAM_TR1_RDCT_MASK) >> 0)
 629 #define   SDRAM_TR1_RDCT_MIN        0x00000000
 630 #define   SDRAM_TR1_RDCT_MAX        0x000001FF
 631
 632 /*-----------------------------------------------------------------------------+
 633 |  SDRAM WDDCTR Options
 634 +-----------------------------------------------------------------------------*/
 635 #define SDRAM_WDDCTR_WRCP_MASK       0xC0000000
 636 #define   SDRAM_WDDCTR_WRCP_0DEG     0x00000000
 637 #define   SDRAM_WDDCTR_WRCP_90DEG    0x40000000
 638 #define   SDRAM_WDDCTR_WRCP_180DEG   0x80000000
 639 #define SDRAM_WDDCTR_DCD_MASK        0x000001FF
 640
 641 /*-----------------------------------------------------------------------------+
 642 |  SDRAM CLKTR Options
 643 +-----------------------------------------------------------------------------*/
 644 #define SDRAM_CLKTR_CLKP_MASK       0xC0000000
 645 #define   SDRAM_CLKTR_CLKP_0DEG     0x00000000
 646 #define   SDRAM_CLKTR_CLKP_90DEG    0x40000000
 647 #define   SDRAM_CLKTR_CLKP_180DEG   0x80000000
 648 #define SDRAM_CLKTR_DCDT_MASK       0x000001FF
 649
 650 /*-----------------------------------------------------------------------------+
 651 |  SDRAM DLYCAL Options
 652 +-----------------------------------------------------------------------------*/
 653 #define SDRAM_DLYCAL_DLCV_MASK      0x000003FC
 654 #define   SDRAM_DLYCAL_DLCV_ENCODE(x) (((x)<<2) & SDRAM_DLYCAL_DLCV_MASK)
 655 #define   SDRAM_DLYCAL_DLCV_DECODE(x) (((x) & SDRAM_DLYCAL_DLCV_MASK)>>2)
 656
 657 /*-----------------------------------------------------------------------------+
 658 |  General Definition
 659 +-----------------------------------------------------------------------------*/
 660 #define DEFAULT_SPD_ADDR1   0x53
 661 #define DEFAULT_SPD_ADDR2   0x52
 662 #define ONE_BILLION         1000000000
 663 #define MAXBANKS            4               /* at most 4 dimm banks */
 664 #define MAX_SPD_BYTES       256
 665 #define NUMHALFCYCLES       4
 666 #define NUMMEMTESTS         8
 667 #define NUMMEMWORDS         8
 668 #define MAXBXCR             4
 669 #define TRUE                1
 670 #define FALSE               0
 671
 672 const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
 673     {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 674      0xFFFFFFFF, 0xFFFFFFFF},
 675     {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 676      0x00000000, 0x00000000},
 677     {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 678      0x55555555, 0x55555555},
 679     {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 680      0xAAAAAAAA, 0xAAAAAAAA},
 681     {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 682      0x5A5A5A5A, 0x5A5A5A5A},
 683     {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 684      0xA5A5A5A5, 0xA5A5A5A5},
 685     {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
 686      0x55AA55AA, 0x55AA55AA},
 687     {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 688      0xAA55AA55, 0xAA55AA55}
 689 };
 690
 691
 692 unsigned char spd_read(uchar chip, uint addr);
 693
 694 void get_spd_info(unsigned long* dimm_populated,
 695                   unsigned char* iic0_dimm_addr,
 696                   unsigned long  num_dimm_banks);
 697
 698 void check_mem_type
 699                  (unsigned long* dimm_populated,
 700                   unsigned char* iic0_dimm_addr,
 701                   unsigned long  num_dimm_banks);
 702
 703 void check_volt_type
 704                  (unsigned long* dimm_populated,
 705                   unsigned char* iic0_dimm_addr,
 706                   unsigned long  num_dimm_banks);
 707
 708 void program_cfg0(unsigned long* dimm_populated,
 709                   unsigned char* iic0_dimm_addr,
 710                   unsigned long  num_dimm_banks);
 711
 712 void program_cfg1(unsigned long* dimm_populated,
 713                   unsigned char* iic0_dimm_addr,
 714                   unsigned long  num_dimm_banks);
 715
 716 void program_rtr (unsigned long* dimm_populated,
 717                   unsigned char* iic0_dimm_addr,
 718                   unsigned long  num_dimm_banks);
 719
 720 void program_tr0 (unsigned long* dimm_populated,
 721                   unsigned char* iic0_dimm_addr,
 722                   unsigned long  num_dimm_banks);
 723
 724 void program_tr1 (void);
 725
 726 void program_ecc (unsigned long  num_bytes);
 727
 728 unsigned
 729 long  program_bxcr(unsigned long* dimm_populated,
 730                    unsigned char* iic0_dimm_addr,
 731                    unsigned long  num_dimm_banks);
 732
 733 /*
 734  * This function is reading data from the DIMM module EEPROM over the SPD bus
 735  * and uses that to program the sdram controller.
 736  *
 737  * This works on boards that has the same schematics that the IBM walnut has.
 738  *
 739  * BUG: Don't handle ECC memory
 740  * BUG: A few values in the TR register is currently hardcoded
 741  */
 742
 743 long int spd_sdram(void) {
 744     unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 745     unsigned long dimm_populated[sizeof(iic0_dimm_addr)];
 746     unsigned long total_size;
 747     unsigned long cfg0;
 748     unsigned long mcsts;
 749     unsigned long num_dimm_banks;               /* on board dimm banks */
 750
 751     num_dimm_banks = sizeof(iic0_dimm_addr);
 752
 753         /*
 754          * Make sure I2C controller is initialized
 755          * before continuing.
 756          */
 757         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 758
 759     /*
 760      * Read the SPD information using I2C interface. Check to see if the
 761      * DIMM slots are populated.
 762      */
 763     get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 764
 765     /*
 766      * Check the memory type for the dimms plugged.
 767      */
 768     check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 769
 770     /*
 771      * Check the voltage type for the dimms plugged.
 772      */
 773     check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 774
 775 #if defined(CONFIG_440_GX)
 776     /*
 777      * Soft-reset SDRAM controller.
 778      */
 779     mtsdr(sdr_srst, SDR0_SRST_DMC);
 780     mtsdr(sdr_srst, 0x00000000);
 781 #endif
 782
 783     /*
 784      * program 440GP SDRAM controller options (SDRAM0_CFG0)
 785      */
 786     program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 787
 788     /*
 789      * program 440GP SDRAM controller options (SDRAM0_CFG1)
 790      */
 791     program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 792
 793     /*
 794      * program SDRAM refresh register (SDRAM0_RTR)
 795      */
 796     program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 797
 798     /*
 799      * program SDRAM Timing Register 0 (SDRAM0_TR0)
 800      */
 801     program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 802
 803     /*
 804      * program the BxCR registers to find out total sdram installed
 805      */
 806     total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
 807         num_dimm_banks);
 808
 809     /*
 810      * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
 811      */
 812     mtsdram(mem_clktr, 0x40000000);
 813
 814     /*
 815      * delay to ensure 200 usec has elapsed
 816      */
 817     udelay(400);
 818
 819     /*
 820      * enable the memory controller
 821      */
 822     mfsdram(mem_cfg0, cfg0);
 823     mtsdram(mem_cfg0, cfg0 | SDRAM_CFG0_DCEN);
 824
 825     /*
 826      * wait for SDRAM_CFG0_DC_EN to complete
 827      */
 828     while(1) {
 829         mfsdram(mem_mcsts, mcsts);
 830         if ((mcsts & SDRAM_MCSTS_MRSC) != 0) {
 831             break;
 832         }
 833     }
 834
 835     /*
 836      * program SDRAM Timing Register 1, adding some delays
 837      */
 838     program_tr1();
 839
 840     /*
 841      * if ECC is enabled, initialize parity bits
 842      */
 843
 844         return total_size;
 845 }
 846
 847 unsigned char spd_read(uchar chip, uint addr) {
 848         unsigned char data[2];
 849
 850         if (i2c_read(chip, addr, 1, data, 1) == 0)
 851                 return data[0];
 852         else
 853                 return 0;
 854 }
 855
 856 void get_spd_info(unsigned long*   dimm_populated,
 857                   unsigned char*   iic0_dimm_addr,
 858                   unsigned long    num_dimm_banks)
 859 {
 860     unsigned long dimm_num;
 861     unsigned long dimm_found;
 862     unsigned char num_of_bytes;
 863     unsigned char total_size;
 864
 865     dimm_found = FALSE;
 866     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 867         num_of_bytes = 0;
 868         total_size = 0;
 869
 870         num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 871         total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 872
 873         if ((num_of_bytes != 0) && (total_size != 0)) {
 874             dimm_populated[dimm_num] = TRUE;
 875             dimm_found = TRUE;
 876 #if 0
 877             printf("DIMM slot %lu: populated\n", dimm_num);
 878 #endif
 879         }
 880         else {
 881             dimm_populated[dimm_num] = FALSE;
 882 #if 0
 883             printf("DIMM slot %lu: Not populated\n", dimm_num);
 884 #endif
 885         }
 886     }
 887
 888     if (dimm_found == FALSE) {
 889         printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 890         hang();
 891     }
 892 }
 893
 894 void check_mem_type(unsigned long*   dimm_populated,
 895                     unsigned char*   iic0_dimm_addr,
 896                     unsigned long    num_dimm_banks)
 897 {
 898     unsigned long dimm_num;
 899     unsigned char dimm_type;
 900
 901     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 902         if (dimm_populated[dimm_num] == TRUE) {
 903             dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 904             switch (dimm_type) {
 905             case 7:
 906 #if 0
 907                 printf("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
 908 #endif
 909                 break;
 910             default:
 911                 printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
 912                     dimm_num);
 913                 printf("Only DDR SDRAM DIMMs are supported.\n");
 914                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 915                 hang();
 916                 break;
 917             }
 918         }
 919     }
 920 }
 921
 922
 923 void check_volt_type(unsigned long*   dimm_populated,
 924                      unsigned char*   iic0_dimm_addr,
 925                      unsigned long    num_dimm_banks)
 926 {
 927     unsigned long dimm_num;
 928     unsigned long voltage_type;
 929
 930     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 931         if (dimm_populated[dimm_num] == TRUE) {
 932             voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 933             if (voltage_type != 0x04) {
 934                 printf("ERROR: DIMM %lu with unsupported voltage level.\n",
 935                     dimm_num);
 936                 hang();
 937             }
 938             else {
 939 #if 0
 940                 printf("DIMM %lu voltage level supported.\n", dimm_num);
 941 #endif
 942             }
 943             break;
 944         }
 945     }
 946 }
 947
 948 void program_cfg0(unsigned long* dimm_populated,
 949                   unsigned char* iic0_dimm_addr,
 950                   unsigned long  num_dimm_banks)
 951 {
 952     unsigned long dimm_num;
 953     unsigned long cfg0;
 954     unsigned long ecc_enabled;
 955     unsigned char ecc;
 956     unsigned char attributes;
 957     unsigned long data_width;
 958     unsigned long dimm_32bit;
 959     unsigned long dimm_64bit;
 960
 961     /*
 962      * get Memory Controller Options 0 data
 963      */
 964     mfsdram(mem_cfg0, cfg0);
 965
 966     /*
 967      * clear bits
 968      */
 969     cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK |
 970               SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
 971               SDRAM_CFG0_DMWD_MASK |
 972               SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
 973
 974
 975     /*
 976      * FIXME: assume the DDR SDRAMs in both banks are the same
 977      */
 978     ecc_enabled = TRUE;
 979     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 980         if (dimm_populated[dimm_num] == TRUE) {
 981             ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
 982             if (ecc != 0x02) {
 983                 ecc_enabled = FALSE;
 984             }
 985
 986             /*
 987              * program Registered DIMM Enable
 988              */
 989             attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
 990             if ((attributes & 0x02) != 0x00) {
 991                 cfg0 |= SDRAM_CFG0_RDEN;
 992             }
 993
 994             /*
 995              * program DDR SDRAM Data Width
 996              */
 997             data_width =
 998                 (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
 999                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
1000             if (data_width == 64 || data_width == 72) {
1001                 dimm_64bit = TRUE;
1002                 cfg0 |= SDRAM_CFG0_DMWD_64;
1003             }
1004             else if (data_width == 32 || data_width == 40) {
1005                 dimm_32bit = TRUE;
1006                 cfg0 |= SDRAM_CFG0_DMWD_32;
1007             }
1008             else {
1009                 printf("WARNING: DIMM with datawidth of %lu bits.\n",
1010                     data_width);
1011                 printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
1012                 hang();
1013             }
1014             break;
1015         }
1016     }
1017
1018     /*
1019      * program Memory Data Error Checking
1020      */
1021     if (ecc_enabled == TRUE) {
1022         cfg0 |= SDRAM_CFG0_MCHK_GEN;
1023     }
1024     else {
1025         cfg0 |= SDRAM_CFG0_MCHK_NON;
1026     }
1027
1028     /*
1029      * program Page Management Unit
1030      */
1031     cfg0 |= SDRAM_CFG0_PMUD;
1032
1033     /*
1034      * program Memory Controller Options 0
1035      * Note: DCEN must be enabled after all DDR SDRAM controller
1036      * configuration registers get initialized.
1037      */
1038     mtsdram(mem_cfg0, cfg0);
1039 }
1040
1041 void program_cfg1(unsigned long* dimm_populated,
1042                   unsigned char* iic0_dimm_addr,
1043                   unsigned long  num_dimm_banks)
1044 {
1045     unsigned long cfg1;
1046     mfsdram(mem_cfg1, cfg1);
1047
1048     /*
1049      * Self-refresh exit, disable PM
1050      */
1051     cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN);
1052
1053     /*
1054      * program Memory Controller Options 1
1055      */
1056     mtsdram(mem_cfg1, cfg1);
1057 }
1058
1059 void program_rtr (unsigned long* dimm_populated,
1060                   unsigned char* iic0_dimm_addr,
1061                   unsigned long  num_dimm_banks)
1062 {
1063     unsigned long dimm_num;
1064     unsigned long bus_period_x_10;
1065     unsigned long refresh_rate = 0;
1066     unsigned char refresh_rate_type;
1067     unsigned long refresh_interval;
1068     unsigned long sdram_rtr;
1069     PPC440_SYS_INFO sys_info;
1070
1071     /*
1072      * get the board info
1073      */
1074     get_sys_info(&sys_info);
1075     bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
1076
1077
1078     for (dimm_num = 0;  dimm_num < num_dimm_banks; dimm_num++) {
1079         if (dimm_populated[dimm_num] == TRUE) {
1080             refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
1081             switch (refresh_rate_type) {
1082             case 0x00:
1083                 refresh_rate = 15625;
1084                 break;
1085             case 0x01:
1086                 refresh_rate = 15625/4;
1087                 break;
1088             case 0x02:
1089                 refresh_rate = 15625/2;
1090                 break;
1091             case 0x03:
1092                 refresh_rate = 15626*2;
1093                 break;
1094             case 0x04:
1095                 refresh_rate = 15625*4;
1096                 break;
1097             case 0x05:
1098                 refresh_rate = 15625*8;
1099                 break;
1100             default:
1101                 printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
1102                     dimm_num);
1103                 printf("Replace the DIMM module with a supported DIMM.\n");
1104                 break;
1105             }
1106
1107             break;
1108         }
1109     }
1110
1111     refresh_interval = refresh_rate * 10 / bus_period_x_10;
1112     sdram_rtr = (refresh_interval & 0x3ff8) <<  16;
1113
1114     /*
1115      * program Refresh Timer Register (SDRAM0_RTR)
1116      */
1117     mtsdram(mem_rtr, sdram_rtr);
1118 }
1119
1120 void program_tr0 (unsigned long* dimm_populated,
1121                   unsigned char* iic0_dimm_addr,
1122                   unsigned long  num_dimm_banks)
1123 {
1124     unsigned long dimm_num;
1125     unsigned long tr0;
1126     unsigned char wcsbc;
1127     unsigned char t_rp_ns;
1128     unsigned char t_rcd_ns;
1129     unsigned char t_ras_ns;
1130     unsigned long t_rp_clk;
1131     unsigned long t_ras_rcd_clk;
1132     unsigned long t_rcd_clk;
1133     unsigned long t_rfc_clk;
1134     unsigned long plb_check;
1135     unsigned char cas_bit;
1136     unsigned long cas_index;
1137     unsigned char cas_2_0_available;
1138     unsigned char cas_2_5_available;
1139     unsigned char cas_3_0_available;
1140     unsigned long cycle_time_ns_x_10[3];
1141     unsigned long tcyc_3_0_ns_x_10;
1142     unsigned long tcyc_2_5_ns_x_10;
1143     unsigned long tcyc_2_0_ns_x_10;
1144     unsigned long tcyc_reg;
1145     unsigned long bus_period_x_10;
1146     PPC440_SYS_INFO sys_info;
1147     unsigned long residue;
1148
1149     /*
1150      * get the board info
1151      */
1152     get_sys_info(&sys_info);
1153     bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
1154
1155     /*
1156      * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
1157      */
1158     mfsdram(mem_tr0, tr0);
1159     tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
1160              SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
1161              SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
1162              SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
1163
1164     /*
1165      * initialization
1166      */
1167     wcsbc = 0;
1168     t_rp_ns = 0;
1169     t_rcd_ns = 0;
1170     t_ras_ns = 0;
1171     cas_2_0_available = TRUE;
1172     cas_2_5_available = TRUE;
1173     cas_3_0_available = TRUE;
1174     tcyc_2_0_ns_x_10 = 0;
1175     tcyc_2_5_ns_x_10 = 0;
1176     tcyc_3_0_ns_x_10 = 0;
1177
1178     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1179         if (dimm_populated[dimm_num] == TRUE) {
1180             wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
1181             t_rp_ns  = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
1182             t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
1183             t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
1184             cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1185
1186             for (cas_index = 0; cas_index < 3; cas_index++) {
1187                 switch (cas_index) {
1188                 case 0:
1189                     tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1190                     break;
1191                 case 1:
1192                     tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1193                     break;
1194                 default:
1195                     tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1196                     break;
1197                 }
1198
1199                 if ((tcyc_reg & 0x0F) >= 10) {
1200                     printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
1201                         dimm_num);
1202                     hang();
1203                 }
1204
1205                 cycle_time_ns_x_10[cas_index] =
1206                     (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
1207             }
1208
1209             cas_index = 0;
1210
1211             if ((cas_bit & 0x80) != 0) {
1212                 cas_index += 3;
1213             }
1214             else if ((cas_bit & 0x40) != 0) {
1215                 cas_index += 2;
1216             }
1217             else if ((cas_bit & 0x20) != 0) {
1218                 cas_index += 1;
1219             }
1220
1221             if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
1222                 tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
1223                 cas_index++;
1224             }
1225             else {
1226                 if (cas_index != 0) {
1227                     cas_index++;
1228                 }
1229                 cas_3_0_available = FALSE;
1230             }
1231
1232             if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
1233                 tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
1234                 cas_index++;
1235             }
1236             else {
1237                 if (cas_index != 0) {
1238                     cas_index++;
1239                 }
1240                 cas_2_5_available = FALSE;
1241             }
1242
1243             if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
1244                 tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
1245                 cas_index++;
1246             }
1247             else {
1248                 if (cas_index != 0) {
1249                     cas_index++;
1250                 }
1251                 cas_2_0_available = FALSE;
1252             }
1253
1254             break;
1255         }
1256     }
1257
1258     /*
1259      * Program SD_WR and SD_WCSBC fields
1260      */
1261     tr0 |= SDRAM_TR0_SDWR_2_CLK;                /* Write Recovery: 2 CLK */
1262     switch (wcsbc) {
1263     case 0:
1264         tr0 |= SDRAM_TR0_SDWD_0_CLK;
1265         break;
1266     default:
1267         tr0 |= SDRAM_TR0_SDWD_1_CLK;
1268         break;
1269     }
1270
1271     /*
1272      * Program SD_CASL field
1273      */
1274     if ((cas_2_0_available == TRUE) &&
1275         (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
1276         tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
1277     }
1278     else if((cas_2_5_available == TRUE) &&
1279         (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
1280         tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
1281     }
1282     else if((cas_3_0_available == TRUE) &&
1283         (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
1284         tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
1285     }
1286     else {
1287         printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
1288         printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1289         printf("Make sure the PLB speed is within the supported range.\n");
1290         hang();
1291     }
1292
1293     /*
1294      * Calculate Trp in clock cycles and round up if necessary
1295      * Program SD_PTA field
1296      */
1297     t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION;
1298     plb_check = ONE_BILLION * t_rp_clk / t_rp_ns;
1299     if (sys_info.freqPLB != plb_check) {
1300         t_rp_clk++;
1301     }
1302     switch ((unsigned long)t_rp_clk) {
1303     case 0:
1304     case 1:
1305     case 2:
1306         tr0 |= SDRAM_TR0_SDPA_2_CLK;
1307         break;
1308     case 3:
1309         tr0 |= SDRAM_TR0_SDPA_3_CLK;
1310         break;
1311     default:
1312         tr0 |= SDRAM_TR0_SDPA_4_CLK;
1313         break;
1314     }
1315
1316     /*
1317      * Program SD_CTP field
1318      */
1319     t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION;
1320     plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns);
1321     if (sys_info.freqPLB != plb_check) {
1322         t_ras_rcd_clk++;
1323     }
1324     switch (t_ras_rcd_clk) {
1325     case 0:
1326     case 1:
1327     case 2:
1328       tr0 |= SDRAM_TR0_SDCP_2_CLK;
1329       break;
1330     case 3:
1331       tr0 |= SDRAM_TR0_SDCP_3_CLK;
1332       break;
1333     case 4:
1334       tr0 |= SDRAM_TR0_SDCP_4_CLK;
1335       break;
1336     default:
1337       tr0 |= SDRAM_TR0_SDCP_5_CLK;
1338       break;
1339     }
1340
1341     /*
1342      * Program SD_LDF field
1343      */
1344     tr0 |= SDRAM_TR0_SDLD_2_CLK;
1345
1346     /*
1347      * Program SD_RFTA field
1348      * FIXME tRFC hardcoded as 75 nanoseconds
1349      */
1350     t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75);
1351     residue = sys_info.freqPLB % (ONE_BILLION / 75);
1352     if (residue >= (ONE_BILLION / 150)) {
1353         t_rfc_clk++;
1354     }
1355     switch (t_rfc_clk) {
1356     case 0:
1357     case 1:
1358     case 2:
1359     case 3:
1360     case 4:
1361     case 5:
1362     case 6:
1363         tr0 |= SDRAM_TR0_SDRA_6_CLK;
1364         break;
1365     case 7:
1366         tr0 |= SDRAM_TR0_SDRA_7_CLK;
1367         break;
1368     case 8:
1369         tr0 |= SDRAM_TR0_SDRA_8_CLK;
1370         break;
1371     case 9:
1372         tr0 |= SDRAM_TR0_SDRA_9_CLK;
1373         break;
1374     case 10:
1375         tr0 |= SDRAM_TR0_SDRA_10_CLK;
1376         break;
1377     case 11:
1378         tr0 |= SDRAM_TR0_SDRA_11_CLK;
1379         break;
1380     case 12:
1381         tr0 |= SDRAM_TR0_SDRA_12_CLK;
1382         break;
1383     default:
1384         tr0 |= SDRAM_TR0_SDRA_13_CLK;
1385         break;
1386     }
1387
1388     /*
1389      * Program SD_RCD field
1390      */
1391     t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION;
1392     plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns;
1393     if (sys_info.freqPLB != plb_check) {
1394         t_rcd_clk++;
1395     }
1396     switch (t_rcd_clk) {
1397     case 0:
1398     case 1:
1399     case 2:
1400         tr0 |= SDRAM_TR0_SDRD_2_CLK;
1401         break;
1402     case 3:
1403         tr0 |= SDRAM_TR0_SDRD_3_CLK;
1404         break;
1405     default:
1406         tr0 |= SDRAM_TR0_SDRD_4_CLK;
1407         break;
1408     }
1409
1410 #if 0
1411     printf("tr0: %x\n", tr0);
1412 #endif
1413     mtsdram(mem_tr0, tr0);
1414 }
1415
1416 void program_tr1 (void)
1417 {
1418     unsigned long tr0;
1419     unsigned long tr1;
1420     unsigned long cfg0;
1421     unsigned long ecc_temp;
1422     unsigned long dlycal;
1423     unsigned long dly_val;
1424     unsigned long i, j, k;
1425     unsigned long bxcr_num;
1426     unsigned long max_pass_length;
1427     unsigned long current_pass_length;
1428     unsigned long current_fail_length;
1429     unsigned long current_start;
1430     unsigned long rdclt;
1431     unsigned long rdclt_offset;
1432     long max_start;
1433     long max_end;
1434     long rdclt_average;
1435     unsigned char window_found;
1436     unsigned char fail_found;
1437     unsigned char pass_found;
1438     unsigned long * membase;
1439     PPC440_SYS_INFO sys_info;
1440
1441     /*
1442      * get the board info
1443      */
1444     get_sys_info(&sys_info);
1445
1446     /*
1447      * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
1448      */
1449     mfsdram(mem_tr1, tr1);
1450     tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
1451              SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
1452
1453     mfsdram(mem_tr0, tr0);
1454     if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
1455        (sys_info.freqPLB > 100000000)) {
1456         tr1 |= SDRAM_TR1_RDSS_TR2;
1457         tr1 |= SDRAM_TR1_RDSL_STAGE3;
1458         tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1459     }
1460     else {
1461         tr1 |= SDRAM_TR1_RDSS_TR1;
1462         tr1 |= SDRAM_TR1_RDSL_STAGE2;
1463         tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1464     }
1465
1466     /*
1467      * save CFG0 ECC setting to a temporary variable and turn ECC off
1468      */
1469     mfsdram(mem_cfg0, cfg0);
1470     ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
1471     mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
1472
1473     /*
1474      * get the delay line calibration register value
1475      */
1476     mfsdram(mem_dlycal, dlycal);
1477     dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
1478
1479     max_pass_length = 0;
1480     max_start = 0;
1481     max_end = 0;
1482     current_pass_length = 0;
1483     current_fail_length = 0;
1484     current_start = 0;
1485     rdclt_offset = 0;
1486     window_found = FALSE;
1487     fail_found = FALSE;
1488     pass_found = FALSE;
1489 #ifdef DEBUG
1490     printf("Starting memory test ");
1491 #endif
1492     for (k = 0; k < NUMHALFCYCLES; k++) {
1493         for (rdclt = 0; rdclt < dly_val; rdclt++)  {
1494             /*
1495              * Set the timing reg for the test.
1496              */
1497             mtsdram(mem_tr1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
1498
1499             for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
1500                 mtdcr(memcfga, mem_b0cr + (bxcr_num<<2));
1501                 if ((mfdcr(memcfgd) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
1502                     /* Bank is enabled */
1503                     membase = (unsigned long*)
1504                         (mfdcr(memcfgd) & SDRAM_BXCR_SDBA_MASK);
1505
1506                     /*
1507                      * Run the short memory test
1508                      */
1509                     for (i = 0; i < NUMMEMTESTS; i++) {
1510                         for (j = 0; j < NUMMEMWORDS; j++) {
1511                             membase[j] = test[i][j];
1512                             ppcDcbf((unsigned long)&(membase[j]));
1513                         }
1514
1515                         for (j = 0; j < NUMMEMWORDS; j++) {
1516                             if (membase[j] != test[i][j]) {
1517                                 ppcDcbf((unsigned long)&(membase[j]));
1518                                 break;
1519                             }
1520                             ppcDcbf((unsigned long)&(membase[j]));
1521                         }
1522
1523                         if (j < NUMMEMWORDS) {
1524                             break;
1525                         }
1526                     }
1527
1528                     /*
1529                      * see if the rdclt value passed
1530                      */
1531                     if (i < NUMMEMTESTS) {
1532                         break;
1533                     }
1534                 }
1535             }
1536
1537             if (bxcr_num == MAXBXCR) {
1538                 if (fail_found == TRUE) {
1539                     pass_found = TRUE;
1540                     if (current_pass_length == 0) {
1541                         current_start = rdclt_offset + rdclt;
1542                     }
1543
1544                     current_fail_length = 0;
1545                     current_pass_length++;
1546
1547                     if (current_pass_length > max_pass_length) {
1548                         max_pass_length = current_pass_length;
1549                         max_start = current_start;
1550                         max_end = rdclt_offset + rdclt;
1551                     }
1552                 }
1553             }
1554             else {
1555                 current_pass_length = 0;
1556                 current_fail_length++;
1557
1558                 if (current_fail_length >= (dly_val>>2)) {
1559                     if (fail_found == FALSE) {
1560                         fail_found = TRUE;
1561                     }
1562                     else if (pass_found == TRUE) {
1563                         window_found = TRUE;
1564                         break;
1565                     }
1566                 }
1567             }
1568         }
1569 #ifdef DEBUG
1570         printf(".");
1571 #endif
1572         if (window_found == TRUE) {
1573             break;
1574         }
1575
1576         tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1577         rdclt_offset += dly_val;
1578     }
1579 #ifdef DEBUG
1580     printf("\n");
1581 #endif
1582
1583     /*
1584      * make sure we find the window
1585      */
1586     if (window_found == FALSE) {
1587        printf("ERROR: Cannot determine a common read delay.\n");
1588        hang();
1589     }
1590
1591     /*
1592      * restore the orignal ECC setting
1593      */
1594     mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
1595
1596     /*
1597      * set the SDRAM TR1 RDCD value
1598      */
1599     tr1 &= ~SDRAM_TR1_RDCD_MASK;
1600     if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) {
1601         tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1602     }
1603     else {
1604         tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1605     }
1606
1607     /*
1608      * set the SDRAM TR1 RDCLT value
1609      */
1610     tr1 &= ~SDRAM_TR1_RDCT_MASK;
1611     while (max_end >= (dly_val<<1)) {
1612         max_end -= (dly_val<<1);
1613         max_start -= (dly_val<<1);
1614     }
1615
1616     rdclt_average = ((max_start + max_end) >> 1);
1617     if (rdclt_average >= 0x60)
1618         while(1);
1619
1620     if (rdclt_average < 0) {
1621         rdclt_average = 0;
1622     }
1623
1624     if (rdclt_average >= dly_val) {
1625         rdclt_average -= dly_val;
1626         tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1627     }
1628     tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
1629
1630 #if 0
1631     printf("tr1: %x\n", tr1);
1632 #endif
1633     /*
1634      * program SDRAM Timing Register 1 TR1
1635      */
1636     mtsdram(mem_tr1, tr1);
1637 }
1638
1639 unsigned long program_bxcr(unsigned long* dimm_populated,
1640                            unsigned char* iic0_dimm_addr,
1641                            unsigned long  num_dimm_banks)
1642 {
1643     unsigned long dimm_num;
1644     unsigned long bxcr_num;
1645     unsigned long bank_base_addr;
1646     unsigned long bank_size_bytes;
1647     unsigned long cr;
1648     unsigned long i;
1649     unsigned long temp;
1650     unsigned char num_row_addr;
1651     unsigned char num_col_addr;
1652     unsigned char num_banks;
1653     unsigned char bank_size_id;
1654
1655
1656     /*
1657      * Set the BxCR regs.  First, wipe out the bank config registers.
1658      */
1659     for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
1660         mtdcr(memcfga, mem_b0cr + (bxcr_num << 2));
1661         mtdcr(memcfgd, 0x00000000);
1662     }
1663
1664     /*
1665      * reset the bank_base address
1666      */
1667     bank_base_addr = CFG_SDRAM_BASE;
1668
1669     for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1670         if (dimm_populated[dimm_num] == TRUE) {
1671             num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
1672             num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
1673             num_banks    = spd_read(iic0_dimm_addr[dimm_num], 5);
1674             bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
1675
1676             /*
1677              * Set the SDRAM0_BxCR regs
1678              */
1679             cr = 0;
1680             bank_size_bytes = 4 * 1024 * 1024 * bank_size_id;
1681             switch (bank_size_id) {
1682             case 0x02:
1683                 cr |= SDRAM_BXCR_SDSZ_8;
1684                 break;
1685             case 0x04:
1686                 cr |= SDRAM_BXCR_SDSZ_16;
1687                 break;
1688             case 0x08:
1689                 cr |= SDRAM_BXCR_SDSZ_32;
1690                 break;
1691             case 0x10:
1692                 cr |= SDRAM_BXCR_SDSZ_64;
1693                 break;
1694             case 0x20:
1695                 cr |= SDRAM_BXCR_SDSZ_128;
1696                 break;
1697             case 0x40:
1698                 cr |= SDRAM_BXCR_SDSZ_256;
1699                 break;
1700             case 0x80:
1701                 cr |= SDRAM_BXCR_SDSZ_512;
1702                 break;
1703             default:
1704                 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1705                     dimm_num);
1706                 printf("ERROR: Unsupported value for the banksize: %d.\n",
1707                    bank_size_id);
1708                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1709                 hang();
1710             }
1711
1712             switch (num_col_addr) {
1713             case 0x08:
1714                 cr |= SDRAM_BXCR_SDAM_1;
1715                 break;
1716             case 0x09:
1717                 cr |= SDRAM_BXCR_SDAM_2;
1718                 break;
1719             case 0x0A:
1720                 cr |= SDRAM_BXCR_SDAM_3;
1721                 break;
1722             case 0x0B:
1723                 cr |= SDRAM_BXCR_SDAM_4;
1724                 break;
1725             default:
1726                 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1727                    dimm_num);
1728                 printf("ERROR: Unsupported value for number of "
1729                    "column addresses: %d.\n", num_col_addr);
1730                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1731                 hang();
1732             }
1733
1734             /*
1735              * enable the bank
1736              */
1737             cr |= SDRAM_BXCR_SDBE;
1738
1739             /*------------------------------------------------------------------
1740             | This next section is hardware dependent and must be programmed
1741             | to match the hardware.
1742             +-----------------------------------------------------------------*/
1743             if (dimm_num == 0) {
1744                 for (i = 0; i < num_banks; i++) {
1745                     mtdcr(memcfga, mem_b0cr + (i << 2));
1746                     temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
1747                                               SDRAM_BXCR_SDSZ_MASK |
1748                                               SDRAM_BXCR_SDAM_MASK |
1749                                               SDRAM_BXCR_SDBE);
1750                     cr |= temp;
1751                     cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
1752                     mtdcr(memcfgd, cr);
1753                     bank_base_addr += bank_size_bytes;
1754                 }
1755             }
1756             else {
1757                 for (i = 0; i < num_banks; i++) {
1758                     mtdcr(memcfga, mem_b2cr + (i << 2));
1759                     temp = mfdcr(memcfgd) & ~(SDRAM_BXCR_SDBA_MASK |
1760                                               SDRAM_BXCR_SDSZ_MASK |
1761                                               SDRAM_BXCR_SDAM_MASK |
1762                                               SDRAM_BXCR_SDBE);
1763                     cr |= temp;
1764                     cr |= bank_base_addr & SDRAM_BXCR_SDBA_MASK;
1765                     mtdcr(memcfgd, cr);
1766                     bank_base_addr += bank_size_bytes;
1767                 }
1768             }
1769         }
1770     }
1771
1772     return(bank_base_addr);
1773 }
1774
1775 void program_ecc (unsigned long  num_bytes)
1776 {
1777     unsigned long bank_base_addr;
1778     unsigned long current_address;
1779     unsigned long end_address;
1780     unsigned long address_increment;
1781     unsigned long cfg0;
1782
1783     /*
1784      * get Memory Controller Options 0 data
1785      */
1786     mfsdram(mem_cfg0, cfg0);
1787
1788     /*
1789      * reset the bank_base address
1790      */
1791     bank_base_addr = CFG_SDRAM_BASE;
1792
1793     if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) {
1794         mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
1795             SDRAM_CFG0_MCHK_GEN);
1796
1797         if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) {
1798             address_increment = 4;
1799         }
1800         else {
1801             address_increment = 8;
1802         }
1803
1804         current_address = (unsigned long)(bank_base_addr);
1805         end_address = (unsigned long)(bank_base_addr) + num_bytes;
1806
1807         while (current_address < end_address) {
1808             *((unsigned long*)current_address) = 0x00000000;
1809             current_address += address_increment;
1810         }
1811
1812         mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) |
1813             SDRAM_CFG0_MCHK_CHK);
1814     }
1815 }
1816
1817 #endif /* CONFIG_440 */
1818
1819 #endif /* CONFIG_SPD_EEPROM */