3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * based on work by Anne Sophie Harnois <anne-sophie.harnois@nextream.fr>
8 * Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
10 * See file CREDITS for list of people who contributed to this
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 #include <asm-ppc/io.h>
35 #ifdef CONFIG_HARD_I2C
37 DECLARE_GLOBAL_DATA_PTR;
39 #if defined(CONFIG_I2C_MULTI_BUS)
40 /* Initialize the bus pointer to whatever one the SPD EEPROM is on.
41 * Default is bus 0. This is necessary because the DDR initialization
42 * runs from ROM, and we can't switch buses because we can't modify
43 * the global variables.
45 #ifndef CONFIG_SYS_SPD_BUS_NUM
46 #define CONFIG_SYS_SPD_BUS_NUM 0
48 static unsigned int i2c_bus_num __attribute__ ((section (".data"))) = CONFIG_SYS_SPD_BUS_NUM;
49 #endif /* CONFIG_I2C_MULTI_BUS */
51 static void _i2c_bus_reset(void)
56 /* Reset status register */
57 /* write 1 in SCMP and IRQA to clear these fields */
58 out_8((u8 *)IIC_STS, 0x0A);
60 /* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
61 out_8((u8 *)IIC_EXTSTS, 0x8F);
63 /* Place chip in the reset state */
64 out_8((u8 *)IIC_XTCNTLSS, IIC_XTCNTLSS_SRST);
66 /* Check if bus is free */
67 dc = in_8((u8 *)IIC_DIRECTCNTL);
68 if (!DIRCTNL_FREE(dc)){
69 /* Try to set bus free state */
70 out_8((u8 *)IIC_DIRECTCNTL, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC);
72 /* Wait until we regain bus control */
73 for (i = 0; i < 100; ++i) {
74 dc = in_8((u8 *)IIC_DIRECTCNTL);
79 dc ^= IIC_DIRCNTL_SCC;
80 out_8((u8 *)IIC_DIRECTCNTL, dc);
82 dc ^= IIC_DIRCNTL_SCC;
83 out_8((u8 *)IIC_DIRECTCNTL, dc);
88 out_8((u8 *)IIC_XTCNTLSS, 0);
91 void i2c_init(int speed, int slaveadd)
93 unsigned long freqOPB;
97 #ifdef CONFIG_SYS_I2C_INIT_BOARD
98 /* call board specific i2c bus reset routine before accessing the */
99 /* environment, which might be in a chip on that bus. For details */
100 /* about this problem see doc/I2C_Edge_Conditions. */
104 for (bus = 0; bus < CONFIG_SYS_MAX_I2C_BUS; bus++) {
107 /* Handle possible failed I2C state */
108 /* FIXME: put this into i2c_init_board()? */
111 /* clear lo master address */
112 out_8((u8 *)IIC_LMADR, 0);
114 /* clear hi master address */
115 out_8((u8 *)IIC_HMADR, 0);
117 /* clear lo slave address */
118 out_8((u8 *)IIC_LSADR, 0);
120 /* clear hi slave address */
121 out_8((u8 *)IIC_HSADR, 0);
123 /* Clock divide Register */
124 /* get OPB frequency */
125 freqOPB = get_OPB_freq();
126 /* set divisor according to freqOPB */
127 divisor = (freqOPB - 1) / 10000000;
130 out_8((u8 *)IIC_CLKDIV, divisor);
133 out_8((u8 *)IIC_INTRMSK, 0);
135 /* clear transfer count */
136 out_8((u8 *)IIC_XFRCNT, 0);
138 /* clear extended control & stat */
139 /* write 1 in SRC SRS SWC SWS to clear these fields */
140 out_8((u8 *)IIC_XTCNTLSS, 0xF0);
142 /* Mode Control Register
143 Flush Slave/Master data buffer */
144 out_8((u8 *)IIC_MDCNTL, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
146 val = in_8((u8 *)IIC_MDCNTL);
148 /* Ignore General Call, slave transfers are ignored,
149 * disable interrupts, exit unknown bus state, enable hold
150 * SCL 100kHz normaly or FastMode for 400kHz and above
153 val |= IIC_MDCNTL_EUBS|IIC_MDCNTL_HSCL;
155 val |= IIC_MDCNTL_FSM;
156 out_8((u8 *)IIC_MDCNTL, val);
158 /* clear control reg */
159 out_8((u8 *)IIC_CNTL, 0x00);
162 /* set to SPD bus as default bus upon powerup */
163 I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
167 * This code tries to use the features of the 405GP i2c
168 * controller. It will transfer up to 4 bytes in one pass
169 * on the loop. It only does out_8((u8 *)lbz) to the buffer when it
170 * is possible to do out16(lhz) transfers.
172 * cmd_type is 0 for write 1 for read.
174 * addr_len can take any value from 0-255, it is only limited
175 * by the char, we could make it larger if needed. If it is
176 * 0 we skip the address write cycle.
178 * Typical case is a Write of an addr followd by a Read. The
179 * IBM FAQ does not cover this. On the last byte of the write
180 * we don't set the creg CHT bit, and on the first bytes of the
181 * read we set the RPST bit.
183 * It does not support address only transfers, there must be
184 * a data part. If you want to write the address yourself, put
185 * it in the data pointer.
187 * It does not support transfer to/from address 0.
189 * It does not check XFRCNT.
191 static int i2c_transfer(unsigned char cmd_type,
193 unsigned char addr[],
194 unsigned char addr_len,
195 unsigned char data[],
196 unsigned short data_len)
206 if (data == 0 || data_len == 0) {
207 /* Don't support data transfer of no length or to address 0 */
208 printf( "i2c_transfer: bad call\n" );
211 if (addr && addr_len) {
221 /* Clear Stop Complete Bit */
222 out_8((u8 *)IIC_STS, IIC_STS_SCMP);
227 status = in_8((u8 *)IIC_STS);
229 } while ((status & IIC_STS_PT) && (i > 0));
231 if (status & IIC_STS_PT) {
232 result = IIC_NOK_TOUT;
235 /* flush the Master/Slave Databuffers */
236 out_8((u8 *)IIC_MDCNTL, ((in_8((u8 *)IIC_MDCNTL))|IIC_MDCNTL_FMDB|IIC_MDCNTL_FSDB));
237 /* need to wait 4 OPB clocks? code below should take that long */
239 /* 7-bit adressing */
240 out_8((u8 *)IIC_HMADR, 0);
241 out_8((u8 *)IIC_LMADR, chip);
247 while (tran != cnt && (result == IIC_OK)) {
250 /* Control register =
251 * Normal transfer, 7-bits adressing, Transfer up to bc bytes, Normal start,
252 * Transfer is a sequence of transfers
256 bc = (cnt - tran) > 4 ? 4 : cnt - tran;
257 creg |= (bc - 1) << 4;
258 /* if the real cmd type is write continue trans */
259 if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt))
260 creg |= IIC_CNTL_CHT;
263 creg |= IIC_CNTL_READ;
265 for(j=0; j < bc; j++)
267 out_8((u8 *)IIC_MDBUF, ptr[tran+j]);
268 out_8((u8 *)IIC_CNTL, creg);
270 /* Transfer is in progress
271 * we have to wait for upto 5 bytes of data
272 * 1 byte chip address+r/w bit then bc bytes
274 * udelay(10) is 1 bit time at 100khz
275 * Doubled for slop. 20 is too small.
280 status = in_8((u8 *)IIC_STS);
283 } while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) && (i > 0));
285 if (status & IIC_STS_ERR) {
287 status = in_8((u8 *)IIC_EXTSTS);
288 /* Lost arbitration? */
289 if (status & IIC_EXTSTS_LA)
291 /* Incomplete transfer? */
292 if (status & IIC_EXTSTS_ICT)
293 result = IIC_NOK_ICT;
294 /* Transfer aborted? */
295 if (status & IIC_EXTSTS_XFRA)
296 result = IIC_NOK_XFRA;
297 } else if ( status & IIC_STS_PT) {
298 result = IIC_NOK_TOUT;
300 /* Command is reading => get buffer */
301 if ((reading) && (result == IIC_OK)) {
302 /* Are there data in buffer */
303 if (status & IIC_STS_MDBS) {
305 * even if we have data we have to wait 4OPB clocks
306 * for it to hit the front of the FIFO, after that
307 * we can just read. We should check XFCNT here and
308 * if the FIFO is full there is no need to wait.
312 ptr[tran+j] = in_8((u8 *)IIC_MDBUF);
314 result = IIC_NOK_DATA;
318 if (ptr == addr && tran == cnt) {
324 creg = IIC_CNTL_RPST;
330 int i2c_probe(uchar chip)
337 * What is needed is to send the chip address and verify that the
338 * address was <ACK>ed (i.e. there was a chip at that address which
339 * drove the data line low).
341 return (i2c_transfer(1, chip << 1, 0,0, buf, 1) != 0);
345 int i2c_read(uchar chip, uint addr, int alen, uchar * buffer, int len)
351 printf ("I2C read: addr len %d not supported\n", alen);
356 xaddr[0] = (addr >> 24) & 0xFF;
357 xaddr[1] = (addr >> 16) & 0xFF;
358 xaddr[2] = (addr >> 8) & 0xFF;
359 xaddr[3] = addr & 0xFF;
363 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
365 * EEPROM chips that implement "address overflow" are ones
366 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
367 * address and the extra bits end up in the "chip address"
368 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
369 * four 256 byte chips.
371 * Note that we consider the length of the address field to
372 * still be one byte because the extra address bits are
373 * hidden in the chip address.
376 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
378 if ((ret = i2c_transfer(1, chip<<1, &xaddr[4-alen], alen, buffer, len)) != 0) {
379 if (gd->have_console)
380 printf( "I2c read: failed %d\n", ret);
386 int i2c_write(uchar chip, uint addr, int alen, uchar * buffer, int len)
391 printf ("I2C write: addr len %d not supported\n", alen);
397 xaddr[0] = (addr >> 24) & 0xFF;
398 xaddr[1] = (addr >> 16) & 0xFF;
399 xaddr[2] = (addr >> 8) & 0xFF;
400 xaddr[3] = addr & 0xFF;
403 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
405 * EEPROM chips that implement "address overflow" are ones
406 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
407 * address and the extra bits end up in the "chip address"
408 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
409 * four 256 byte chips.
411 * Note that we consider the length of the address field to
412 * still be one byte because the extra address bits are
413 * hidden in the chip address.
416 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
419 return (i2c_transfer(0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
422 /*-----------------------------------------------------------------------
425 uchar i2c_reg_read(uchar i2c_addr, uchar reg)
429 i2c_read(i2c_addr, reg, 1, &buf, 1);
434 /*-----------------------------------------------------------------------
437 void i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
439 i2c_write(i2c_addr, reg, 1, &val, 1);
442 #if defined(CONFIG_I2C_MULTI_BUS)
444 * Functions for multiple I2C bus handling
446 unsigned int i2c_get_bus_num(void)
451 int i2c_set_bus_num(unsigned int bus)
453 if (bus >= CONFIG_SYS_MAX_I2C_BUS)
460 #endif /* CONFIG_I2C_MULTI_BUS */
462 /* TODO: add 100/400k switching */
463 unsigned int i2c_get_bus_speed(void)
465 return CONFIG_SYS_I2C_SPEED;
468 int i2c_set_bus_speed(unsigned int speed)
470 if (speed != CONFIG_SYS_I2C_SPEED)
475 #endif /* CONFIG_HARD_I2C */