3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
29 #if defined(CFG_440_GPIO_TABLE)
30 gpio_param_s gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CFG_440_GPIO_TABLE;
33 #if defined(GPIO0_OSRL)
34 /* Only some 4xx variants support alternate funtions on the GPIO's */
35 void gpio_config(int pin, int in_out, int gpio_alt, int out_val)
44 if (pin >= GPIO_MAX) {
49 if (pin >= GPIO_MAX/2) {
51 pin2 = (pin - GPIO_MAX/2) << 1;
54 mask = 0x80000000 >> pin;
55 mask2 = 0xc0000000 >> (pin2 << 1);
57 /* first set TCR to 0 */
58 out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) & ~mask);
60 if (in_out == GPIO_OUT) {
61 val = in32(GPIO0_OSRL + offs + offs2) & ~mask2;
64 val |= GPIO_ALT1_SEL >> pin2;
67 val |= GPIO_ALT2_SEL >> pin2;
70 val |= GPIO_ALT3_SEL >> pin2;
73 out32(GPIO0_OSRL + offs + offs2, val);
75 /* setup requested output value */
76 if (out_val == GPIO_OUT_0)
77 out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~mask);
78 else if (out_val == GPIO_OUT_1)
79 out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) | mask);
81 /* now configure TCR to drive output if selected */
82 out32(GPIO0_TCR + offs, in32(GPIO0_TCR + offs) | mask);
84 val = in32(GPIO0_ISR1L + offs + offs2) & ~mask2;
85 val |= GPIO_IN_SEL >> pin2;
86 out32(GPIO0_ISR1L + offs + offs2, val);
89 #endif /* GPIO_OSRL */
91 void gpio_write_bit(int pin, int val)
95 if (pin >= GPIO_MAX) {
101 out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) | GPIO_VAL(pin));
103 out32(GPIO0_OR + offs, in32(GPIO0_OR + offs) & ~GPIO_VAL(pin));
106 int gpio_read_out_bit(int pin)
110 if (pin >= GPIO_MAX) {
115 return (in32(GPIO0_OR + offs) & GPIO_VAL(pin) ? 1 : 0);
118 #if defined(CFG_440_GPIO_TABLE)
119 void gpio_set_chip_configuration(void)
121 unsigned char i=0, j=0, offs=0, gpio_core;
122 unsigned long reg, core_add;
124 for (gpio_core=0; gpio_core<GPIO_GROUP_MAX; gpio_core++) {
127 /* GPIO config of the GPIOs 0 to 31 */
128 for (i=0; i<GPIO_MAX; i++, j++) {
129 if (i == GPIO_MAX/2) {
134 core_add = gpio_tab[gpio_core][i].add;
136 if ((gpio_tab[gpio_core][i].in_out == GPIO_IN) ||
137 (gpio_tab[gpio_core][i].in_out == GPIO_BI)) {
139 switch (gpio_tab[gpio_core][i].alt_nb) {
144 reg = in32(GPIO_IS1(core_add+offs))
145 & ~(GPIO_MASK >> (j*2));
146 reg = reg | (GPIO_IN_SEL >> (j*2));
147 out32(GPIO_IS1(core_add+offs), reg);
151 reg = in32(GPIO_IS2(core_add+offs))
152 & ~(GPIO_MASK >> (j*2));
153 reg = reg | (GPIO_IN_SEL >> (j*2));
154 out32(GPIO_IS2(core_add+offs), reg);
158 reg = in32(GPIO_IS3(core_add+offs))
159 & ~(GPIO_MASK >> (j*2));
160 reg = reg | (GPIO_IN_SEL >> (j*2));
161 out32(GPIO_IS3(core_add+offs), reg);
166 if ((gpio_tab[gpio_core][i].in_out == GPIO_OUT) ||
167 (gpio_tab[gpio_core][i].in_out == GPIO_BI)) {
169 switch (gpio_tab[gpio_core][i].alt_nb) {
171 if (gpio_core == GPIO0) {
176 * else -> don't touch
178 reg = in32(GPIO0_OR);
179 if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
180 reg |= (0x80000000 >> (i));
181 else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
182 reg &= ~(0x80000000 >> (i));
183 out32(GPIO0_OR, reg);
185 reg = in32(GPIO0_TCR) | (0x80000000 >> (i));
186 out32(GPIO0_TCR, reg);
189 if (gpio_core == GPIO1) {
194 * else -> don't touch
196 reg = in32(GPIO1_OR);
197 if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_1)
198 reg |= (0x80000000 >> (i));
199 else if (gpio_tab[gpio_core][i].out_val == GPIO_OUT_0)
200 reg &= ~(0x80000000 >> (i));
201 out32(GPIO1_OR, reg);
203 reg = in32(GPIO1_TCR) | (0x80000000 >> (i));
204 out32(GPIO1_TCR, reg);
207 reg = in32(GPIO_OS(core_add+offs))
208 & ~(GPIO_MASK >> (j*2));
209 out32(GPIO_OS(core_add+offs), reg);
210 reg = in32(GPIO_TS(core_add+offs))
211 & ~(GPIO_MASK >> (j*2));
212 out32(GPIO_TS(core_add+offs), reg);
216 reg = in32(GPIO_OS(core_add+offs))
217 & ~(GPIO_MASK >> (j*2));
218 reg = reg | (GPIO_ALT1_SEL >> (j*2));
219 out32(GPIO_OS(core_add+offs), reg);
220 reg = in32(GPIO_TS(core_add+offs))
221 & ~(GPIO_MASK >> (j*2));
222 reg = reg | (GPIO_ALT1_SEL >> (j*2));
223 out32(GPIO_TS(core_add+offs), reg);
227 reg = in32(GPIO_OS(core_add+offs))
228 & ~(GPIO_MASK >> (j*2));
229 reg = reg | (GPIO_ALT2_SEL >> (j*2));
230 out32(GPIO_OS(core_add+offs), reg);
231 reg = in32(GPIO_TS(core_add+offs))
232 & ~(GPIO_MASK >> (j*2));
233 reg = reg | (GPIO_ALT2_SEL >> (j*2));
234 out32(GPIO_TS(core_add+offs), reg);
238 reg = in32(GPIO_OS(core_add+offs))
239 & ~(GPIO_MASK >> (j*2));
240 reg = reg | (GPIO_ALT3_SEL >> (j*2));
241 out32(GPIO_OS(core_add+offs), reg);
242 reg = in32(GPIO_TS(core_add+offs))
243 & ~(GPIO_MASK >> (j*2));
244 reg = reg | (GPIO_ALT3_SEL >> (j*2));
245 out32(GPIO_TS(core_add+offs), reg);
252 #endif /* CFG_440_GPIO_TABLE */