1 /*-----------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
23 * File Name: enetemac.c
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
49 * - Receive buffer descriptor ring is used to send buffers
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 *-----------------------------------------------------------------------------*
71 * 17-Nov-03 travis.sawyer@sandburst.com
72 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
73 * in the 440GX. This port should work with the 440GP
75 * 15-Aug-05 sr@denx.de
76 * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
77 now handling all 4xx cpu's.
78 *-----------------------------------------------------------------------------*/
83 #include <asm/processor.h>
85 #include <asm/cache.h>
89 #include <ppc4xx_enet.h>
93 #include <asm/ppc4xx-intvec.h>
96 * Only compile for platform with AMCC EMAC ethernet controller and
97 * network support enabled.
98 * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
100 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
102 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
103 #error "CONFIG_MII has to be defined!"
106 #if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI)
107 #error "CONFIG_NET_MULTI has to be defined for NetConsole"
110 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
111 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */
113 /* Ethernet Transmit and Receive Buffers */
115 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
116 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
118 #define ENET_MAX_MTU PKTSIZE
119 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
121 /*-----------------------------------------------------------------------------+
122 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
123 * Interrupt Controller).
124 *-----------------------------------------------------------------------------*/
125 #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
126 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
127 #define EMAC_UIC_DEF UIC_ENET
128 #define EMAC_UIC_DEF1 UIC_ENET1
129 #define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
133 #define BI_PHYMODE_NONE 0
134 #define BI_PHYMODE_ZMII 1
135 #define BI_PHYMODE_RGMII 2
136 #define BI_PHYMODE_GMII 3
137 #define BI_PHYMODE_RTBI 4
138 #define BI_PHYMODE_TBI 5
139 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
140 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
141 defined(CONFIG_405EX)
142 #define BI_PHYMODE_SMII 6
143 #define BI_PHYMODE_MII 7
144 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
145 #define BI_PHYMODE_RMII 8
149 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
150 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
151 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
152 defined(CONFIG_405EX)
153 #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
156 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
157 #define SDR0_ETH_CFG_CLK_SEL_V(n) (0x01 << (8 + n))
160 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
161 #define MAL_RX_CHAN_MUL 8 /* 460EX/GT uses MAL channel 8 for EMAC1 */
163 #define MAL_RX_CHAN_MUL 1
166 /*-----------------------------------------------------------------------------+
167 * Global variables. TX and RX descriptors and buffers.
168 *-----------------------------------------------------------------------------*/
170 static uint32_t mal_ier;
172 #if !defined(CONFIG_NET_MULTI)
173 struct eth_device *emac0_dev = NULL;
177 * Get count of EMAC devices (doesn't have to be the max. possible number
178 * supported by the cpu)
180 * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
181 * EMAC count is possible. As it is needed for the Kilauea/Haleakala
182 * 405EX/405EXr eval board, using the same binary.
184 #if defined(CONFIG_BOARD_EMAC_COUNT)
185 #define LAST_EMAC_NUM board_emac_count()
186 #else /* CONFIG_BOARD_EMAC_COUNT */
187 #if defined(CONFIG_HAS_ETH3)
188 #define LAST_EMAC_NUM 4
189 #elif defined(CONFIG_HAS_ETH2)
190 #define LAST_EMAC_NUM 3
191 #elif defined(CONFIG_HAS_ETH1)
192 #define LAST_EMAC_NUM 2
194 #define LAST_EMAC_NUM 1
196 #endif /* CONFIG_BOARD_EMAC_COUNT */
198 /* normal boards start with EMAC0 */
199 #if !defined(CONFIG_EMAC_NR_START)
200 #define CONFIG_EMAC_NR_START 0
203 #if defined(CONFIG_405EX) || defined(CONFIG_440EPX)
204 #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev)))
206 #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * 2))
209 #define MAL_RX_DESC_SIZE 2048
210 #define MAL_TX_DESC_SIZE 2048
211 #define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE)
213 /*-----------------------------------------------------------------------------+
214 * Prototypes and externals.
215 *-----------------------------------------------------------------------------*/
216 static void enet_rcv (struct eth_device *dev, unsigned long malisr);
218 int enetInt (struct eth_device *dev);
219 static void mal_err (struct eth_device *dev, unsigned long isr,
220 unsigned long uic, unsigned long maldef,
221 unsigned long mal_errr);
222 static void emac_err (struct eth_device *dev, unsigned long isr);
224 extern int phy_setup_aneg (char *devname, unsigned char addr);
225 extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
226 unsigned char reg, unsigned short *value);
227 extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
228 unsigned char reg, unsigned short value);
230 int board_emac_count(void);
232 static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p)
234 #if defined(CONFIG_440SPE) || \
235 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
236 defined(CONFIG_405EX)
240 val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
242 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
245 mfsdr(SDR0_ETH_CFG, val);
246 val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
247 mtsdr(SDR0_ETH_CFG, val);
251 static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p)
253 #if defined(CONFIG_440SPE) || \
254 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
255 defined(CONFIG_405EX)
259 val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
261 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
264 mfsdr(SDR0_ETH_CFG, val);
265 val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
266 mtsdr(SDR0_ETH_CFG, val);
270 /*-----------------------------------------------------------------------------+
272 | Disable MAL channel, and EMACn
273 +-----------------------------------------------------------------------------*/
274 static void ppc_4xx_eth_halt (struct eth_device *dev)
276 EMAC_4XX_HW_PST hw_p = dev->priv;
277 uint32_t failsafe = 10000;
279 out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
281 /* 1st reset MAL channel */
282 /* Note: writing a 0 to a channel has no effect */
283 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
284 mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
286 mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
288 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
291 while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
292 udelay (1000); /* Delay 1 MS so as not to hammer the register */
298 /* provide clocks for EMAC internal loopback */
299 emac_loopback_enable(hw_p);
302 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
304 /* remove clocks for EMAC internal loopback */
305 emac_loopback_disable(hw_p);
307 #ifndef CONFIG_NETCONSOLE
308 hw_p->print_speed = 1; /* print speed message again next time */
314 #if defined (CONFIG_440GX)
315 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
318 unsigned long zmiifer;
319 unsigned long rmiifer;
321 mfsdr(sdr_pfc1, pfc1);
322 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
329 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
330 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
331 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
332 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
333 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
334 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
335 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
336 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
339 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
340 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
341 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
342 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
343 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
344 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
345 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
346 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
349 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
350 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
351 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
352 bis->bi_phymode[1] = BI_PHYMODE_NONE;
353 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
354 bis->bi_phymode[3] = BI_PHYMODE_NONE;
357 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
358 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
359 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
360 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
361 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
362 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
363 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
364 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
367 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
368 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
369 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
370 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
371 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
372 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
373 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
374 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
377 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
378 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
379 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
380 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
381 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
382 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
386 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
388 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
389 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
390 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
391 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
395 /* Ensure we setup mdio for this devnum and ONLY this devnum */
396 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
398 out_be32((void *)ZMII_FER, zmiifer);
399 out_be32((void *)RGMII_FER, rmiifer);
403 #endif /* CONFIG_440_GX */
405 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
406 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
408 unsigned long zmiifer=0x0;
411 mfsdr(sdr_pfc1, pfc1);
412 pfc1 &= SDR0_PFC1_SELECT_MASK;
415 case SDR0_PFC1_SELECT_CONFIG_2:
417 out_be32((void *)ZMII_FER, 0x00);
418 out_be32((void *)RGMII_FER, 0x00000037);
419 bis->bi_phymode[0] = BI_PHYMODE_GMII;
420 bis->bi_phymode[1] = BI_PHYMODE_NONE;
422 case SDR0_PFC1_SELECT_CONFIG_4:
423 /* 2 x RGMII ports */
424 out_be32((void *)ZMII_FER, 0x00);
425 out_be32((void *)RGMII_FER, 0x00000055);
426 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
427 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
429 case SDR0_PFC1_SELECT_CONFIG_6:
431 out_be32((void *)ZMII_FER,
432 ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
433 ((ZMII_FER_SMII) << ZMII_FER_V(1)));
434 out_be32((void *)RGMII_FER, 0x00000000);
435 bis->bi_phymode[0] = BI_PHYMODE_SMII;
436 bis->bi_phymode[1] = BI_PHYMODE_SMII;
438 case SDR0_PFC1_SELECT_CONFIG_1_2:
439 /* only 1 x MII supported */
440 out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
441 out_be32((void *)RGMII_FER, 0x00000000);
442 bis->bi_phymode[0] = BI_PHYMODE_MII;
443 bis->bi_phymode[1] = BI_PHYMODE_NONE;
449 /* Ensure we setup mdio for this devnum and ONLY this devnum */
450 zmiifer = in_be32((void *)ZMII_FER);
451 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
452 out_be32((void *)ZMII_FER, zmiifer);
456 #endif /* CONFIG_440EPX */
458 #if defined(CONFIG_405EX)
459 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
464 * Right now only 2*RGMII is supported. Please extend when needed.
469 /* 2 x RGMII ports */
470 out_be32((void *)RGMII_FER, 0x00000055);
471 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
472 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
481 /* Ensure we setup mdio for this devnum and ONLY this devnum */
482 gmiifer = in_be32((void *)RGMII_FER);
483 gmiifer |= (1 << (19-devnum));
484 out_be32((void *)RGMII_FER, gmiifer);
488 #endif /* CONFIG_405EX */
490 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
491 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
494 u32 zmiifer; /* ZMII0_FER reg. */
495 u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */
496 u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */
503 * NOTE: 460GT has 2 RGMII bridge cores:
504 * emac0 ------ RGMII0_BASE
508 * emac2 ------ RGMII1_BASE
512 * 460EX has 1 RGMII bridge core:
513 * and RGMII1_BASE is disabled
514 * emac0 ------ RGMII0_BASE
520 * Right now only 2*RGMII is supported. Please extend when needed.
526 /* GMC0 EMAC4_0, ZMII Bridge */
527 zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
528 bis->bi_phymode[0] = BI_PHYMODE_MII;
529 bis->bi_phymode[1] = BI_PHYMODE_NONE;
530 bis->bi_phymode[2] = BI_PHYMODE_NONE;
531 bis->bi_phymode[3] = BI_PHYMODE_NONE;
535 /* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */
536 zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
537 zmiifer |= ZMII_FER_MII << ZMII_FER_V(2);
538 bis->bi_phymode[0] = BI_PHYMODE_MII;
539 bis->bi_phymode[1] = BI_PHYMODE_NONE;
540 bis->bi_phymode[2] = BI_PHYMODE_MII;
541 bis->bi_phymode[3] = BI_PHYMODE_NONE;
545 /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
546 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
547 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
548 bis->bi_phymode[0] = BI_PHYMODE_RMII;
549 bis->bi_phymode[1] = BI_PHYMODE_RMII;
550 bis->bi_phymode[2] = BI_PHYMODE_NONE;
551 bis->bi_phymode[3] = BI_PHYMODE_NONE;
555 /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */
557 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
558 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
559 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
560 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
561 bis->bi_phymode[0] = BI_PHYMODE_RMII;
562 bis->bi_phymode[1] = BI_PHYMODE_RMII;
563 bis->bi_phymode[2] = BI_PHYMODE_RMII;
564 bis->bi_phymode[3] = BI_PHYMODE_RMII;
568 /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
569 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
570 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
571 bis->bi_phymode[0] = BI_PHYMODE_SMII;
572 bis->bi_phymode[1] = BI_PHYMODE_SMII;
573 bis->bi_phymode[2] = BI_PHYMODE_NONE;
574 bis->bi_phymode[3] = BI_PHYMODE_NONE;
578 /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */
580 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
581 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
582 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
583 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
584 bis->bi_phymode[0] = BI_PHYMODE_SMII;
585 bis->bi_phymode[1] = BI_PHYMODE_SMII;
586 bis->bi_phymode[2] = BI_PHYMODE_SMII;
587 bis->bi_phymode[3] = BI_PHYMODE_SMII;
590 /* This is the default mode that we want for board bringup - Maple */
592 /* GMC0 EMAC4_0, RGMII Bridge 0 */
593 rmiifer |= RGMII_FER_MDIO(0);
596 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
597 bis->bi_phymode[0] = BI_PHYMODE_GMII;
598 bis->bi_phymode[1] = BI_PHYMODE_NONE;
599 bis->bi_phymode[2] = BI_PHYMODE_NONE;
600 bis->bi_phymode[3] = BI_PHYMODE_NONE;
602 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */
603 bis->bi_phymode[0] = BI_PHYMODE_NONE;
604 bis->bi_phymode[1] = BI_PHYMODE_GMII;
605 bis->bi_phymode[2] = BI_PHYMODE_NONE;
606 bis->bi_phymode[3] = BI_PHYMODE_NONE;
611 /* GMC0 EMAC4_0, RGMII Bridge 0 */
612 /* GMC1 EMAC4_2, RGMII Bridge 1 */
613 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
614 rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC2 */
615 rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
616 rmiifer1 |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC2 */
618 bis->bi_phymode[0] = BI_PHYMODE_GMII;
619 bis->bi_phymode[1] = BI_PHYMODE_NONE;
620 bis->bi_phymode[2] = BI_PHYMODE_GMII;
621 bis->bi_phymode[3] = BI_PHYMODE_NONE;
624 /* 2 RGMII - 460EX */
625 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
626 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
627 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
628 rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
630 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
631 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
632 bis->bi_phymode[2] = BI_PHYMODE_NONE;
633 bis->bi_phymode[3] = BI_PHYMODE_NONE;
636 /* 4 RGMII - 460GT */
637 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
638 /* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */
639 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
640 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
641 rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2);
642 rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3);
643 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
644 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
645 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
646 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
652 /* Set EMAC for MDIO */
653 mfsdr(SDR0_ETH_CFG, eth_cfg);
654 eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
655 mtsdr(SDR0_ETH_CFG, eth_cfg);
657 out_be32((void *)RGMII_FER, rmiifer);
658 #if defined(CONFIG_460GT)
659 out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1);
662 /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
663 mfsdr(SDR0_ETH_CFG, eth_cfg);
664 eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
665 mtsdr(SDR0_ETH_CFG, eth_cfg);
669 #endif /* CONFIG_460EX || CONFIG_460GT */
671 static inline void *malloc_aligned(u32 size, u32 align)
673 return (void *)(((u32)malloc(size + align) + align - 1) &
677 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
680 unsigned long reg = 0;
683 unsigned long duplex;
684 unsigned long failsafe;
686 unsigned short devnum;
687 unsigned short reg_short;
688 #if defined(CONFIG_440GX) || \
689 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
690 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
691 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
692 defined(CONFIG_405EX)
694 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
695 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
696 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
697 defined(CONFIG_405EX)
703 #ifdef CONFIG_4xx_DCACHE
704 static u32 last_used_ea = 0;
707 EMAC_4XX_HW_PST hw_p = dev->priv;
709 /* before doing anything, figure out if we have a MAC address */
711 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
712 printf("ERROR: ethaddr not set!\n");
716 #if defined(CONFIG_440GX) || \
717 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
718 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
719 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
720 defined(CONFIG_405EX)
721 /* Need to get the OPB frequency so we can access the PHY */
722 get_sys_info (&sysinfo);
726 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
728 devnum = hw_p->devnum;
733 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
734 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
735 * is possible that new packets (without relationship with
736 * current transfer) have got the time to arrived before
737 * netloop calls eth_halt
739 printf ("About preceeding transfer (eth%d):\n"
740 "- Sent packet number %d\n"
741 "- Received packet number %d\n"
742 "- Handled packet number %d\n",
745 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
747 hw_p->stats.pkts_tx = 0;
748 hw_p->stats.pkts_rx = 0;
749 hw_p->stats.pkts_handled = 0;
750 hw_p->print_speed = 1; /* print speed message again next time */
753 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
754 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
756 hw_p->rx_slot = 0; /* MAL Receive Slot */
757 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
758 hw_p->rx_u_index = 0; /* Receive User Queue Index */
760 hw_p->tx_slot = 0; /* MAL Transmit Slot */
761 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
762 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
764 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
766 /* NOTE: 440GX spec states that mode is mutually exclusive */
767 /* NOTE: Therefore, disable all other EMACS, since we handle */
768 /* NOTE: only one emac at a time */
770 out_be32((void *)ZMII_FER, 0);
773 #if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
774 out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
775 #elif defined(CONFIG_440GX) || \
776 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
777 defined(CONFIG_460EX) || defined(CONFIG_460GT)
778 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
781 out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
782 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
783 #if defined(CONFIG_405EX)
784 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
789 /* provide clocks for EMAC internal loopback */
790 emac_loopback_enable(hw_p);
793 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
795 /* remove clocks for EMAC internal loopback */
796 emac_loopback_disable(hw_p);
799 while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
804 printf("\nProblem resetting EMAC!\n");
806 #if defined(CONFIG_440GX) || \
807 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
808 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
809 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
810 defined(CONFIG_405EX)
811 /* Whack the M1 register */
813 mode_reg &= ~0x00000038;
814 if (sysinfo.freqOPB <= 50000000);
815 else if (sysinfo.freqOPB <= 66666667)
816 mode_reg |= EMAC_M1_OBCI_66;
817 else if (sysinfo.freqOPB <= 83333333)
818 mode_reg |= EMAC_M1_OBCI_83;
819 else if (sysinfo.freqOPB <= 100000000)
820 mode_reg |= EMAC_M1_OBCI_100;
822 mode_reg |= EMAC_M1_OBCI_GT100;
824 out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
825 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
827 /* wait for PHY to complete auto negotiation */
829 #ifndef CONFIG_CS8952_PHY
832 reg = CONFIG_PHY_ADDR;
834 #if defined (CONFIG_PHY1_ADDR)
836 reg = CONFIG_PHY1_ADDR;
839 #if defined (CONFIG_440GX)
841 reg = CONFIG_PHY2_ADDR;
844 reg = CONFIG_PHY3_ADDR;
848 reg = CONFIG_PHY_ADDR;
852 bis->bi_phynum[devnum] = reg;
854 #if defined(CONFIG_PHY_RESET)
856 * Reset the phy, only if its the first time through
857 * otherwise, just check the speeds & feeds
859 if (hw_p->first_init == 0) {
860 #if defined(CONFIG_M88E1111_PHY)
861 miiphy_write (dev->name, reg, 0x14, 0x0ce3);
862 miiphy_write (dev->name, reg, 0x18, 0x4101);
863 miiphy_write (dev->name, reg, 0x09, 0x0e00);
864 miiphy_write (dev->name, reg, 0x04, 0x01e1);
866 miiphy_reset (dev->name, reg);
868 #if defined(CONFIG_440GX) || \
869 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
870 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
871 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
872 defined(CONFIG_405EX)
874 #if defined(CONFIG_CIS8201_PHY)
876 * Cicada 8201 PHY needs to have an extended register whacked
879 if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
880 #if defined(CONFIG_CIS8201_SHORT_ETCH)
881 miiphy_write (dev->name, reg, 23, 0x1300);
883 miiphy_write (dev->name, reg, 23, 0x1000);
886 * Vitesse VSC8201/Cicada CIS8201 errata:
887 * Interoperability problem with Intel 82547EI phys
888 * This work around (provided by Vitesse) changes
889 * the default timer convergence from 8ms to 12ms
891 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
892 miiphy_write (dev->name, reg, 0x08, 0x0200);
893 miiphy_write (dev->name, reg, 0x1f, 0x52b5);
894 miiphy_write (dev->name, reg, 0x02, 0x0004);
895 miiphy_write (dev->name, reg, 0x01, 0x0671);
896 miiphy_write (dev->name, reg, 0x00, 0x8fae);
897 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
898 miiphy_write (dev->name, reg, 0x08, 0x0000);
899 miiphy_write (dev->name, reg, 0x1f, 0x0000);
900 /* end Vitesse/Cicada errata */
904 #if defined(CONFIG_ET1011C_PHY)
906 * Agere ET1011c PHY needs to have an extended register whacked
909 if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
910 miiphy_read (dev->name, reg, 0x16, ®_short);
912 reg_short |= 0x6; /* RGMII DLL Delay*/
913 miiphy_write (dev->name, reg, 0x16, reg_short);
915 miiphy_read (dev->name, reg, 0x17, ®_short);
916 reg_short &= ~(0x40);
917 miiphy_write (dev->name, reg, 0x17, reg_short);
919 miiphy_write(dev->name, reg, 0x1c, 0x74f0);
924 /* Start/Restart autonegotiation */
925 phy_setup_aneg (dev->name, reg);
928 #endif /* defined(CONFIG_PHY_RESET) */
930 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
933 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
935 if ((reg_short & PHY_BMSR_AUTN_ABLE)
936 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
937 puts ("Waiting for PHY auto negotiation to complete");
939 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
943 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
944 puts (" TIMEOUT !\n");
948 if ((i++ % 1000) == 0) {
951 udelay (1000); /* 1 ms */
952 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
956 udelay (500000); /* another 500 ms (results in faster booting) */
958 #endif /* #ifndef CONFIG_CS8952_PHY */
960 speed = miiphy_speed (dev->name, reg);
961 duplex = miiphy_duplex (dev->name, reg);
963 if (hw_p->print_speed) {
964 hw_p->print_speed = 0;
965 printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
966 (int) speed, (duplex == HALF) ? "HALF" : "FULL",
970 #if defined(CONFIG_440) && \
971 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
972 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
973 !defined(CONFIG_460EX) && !defined(CONFIG_460GT)
974 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
977 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
979 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
984 /* Set ZMII/RGMII speed according to the phy link speed */
985 reg = in_be32((void *)ZMII_SSR);
986 if ( (speed == 100) || (speed == 1000) )
987 out_be32((void *)ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
989 out_be32((void *)ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
991 if ((devnum == 2) || (devnum == 3)) {
993 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
994 else if (speed == 100)
995 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
996 else if (speed == 10)
997 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
999 printf("Error in RGMII Speed\n");
1002 out_be32((void *)RGMII_SSR, reg);
1004 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
1006 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1007 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1008 defined(CONFIG_405EX)
1010 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
1011 else if (speed == 100)
1012 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
1013 else if (speed == 10)
1014 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
1016 printf("Error in RGMII Speed\n");
1019 out_be32((void *)RGMII_SSR, reg);
1020 #if defined(CONFIG_460GT)
1021 if ((devnum == 2) || (devnum == 3))
1022 out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg);
1026 /* set the Mal configuration reg */
1027 #if defined(CONFIG_440GX) || \
1028 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1029 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
1030 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1031 defined(CONFIG_405EX)
1032 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
1033 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
1035 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
1036 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
1037 if (get_pvr() == PVR_440GP_RB) {
1038 mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
1043 * Malloc MAL buffer desciptors, make sure they are
1044 * aligned on cache line boundary size
1045 * (401/403/IOP480 = 16, 405 = 32)
1046 * and doesn't cross cache block boundaries.
1048 if (hw_p->first_init == 0) {
1049 debug("*** Allocating descriptor memory ***\n");
1051 bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096);
1053 printf("%s: Error allocating MAL descriptor buffers!\n");
1057 #ifdef CONFIG_4xx_DCACHE
1058 flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
1060 bd_uncached = bis->bi_memsize;
1062 bd_uncached = last_used_ea + MAL_ALLOC_SIZE;
1064 last_used_ea = bd_uncached;
1065 program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE,
1066 TLB_WORD2_I_ENABLE);
1068 bd_uncached = bd_cached;
1070 hw_p->tx_phys = bd_cached;
1071 hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
1072 hw_p->tx = (mal_desc_t *)(bd_uncached);
1073 hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
1074 debug("hw_p->tx=%08x, hw_p->rx=%08x\n", hw_p->tx, hw_p->rx);
1077 for (i = 0; i < NUM_TX_BUFF; i++) {
1078 hw_p->tx[i].ctrl = 0;
1079 hw_p->tx[i].data_len = 0;
1080 if (hw_p->first_init == 0)
1081 hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE,
1083 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
1084 if ((NUM_TX_BUFF - 1) == i)
1085 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
1086 hw_p->tx_run[i] = -1;
1087 debug("TX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->tx[i].data_ptr);
1090 for (i = 0; i < NUM_RX_BUFF; i++) {
1091 hw_p->rx[i].ctrl = 0;
1092 hw_p->rx[i].data_len = 0;
1093 hw_p->rx[i].data_ptr = (char *)NetRxPackets[i];
1094 if ((NUM_RX_BUFF - 1) == i)
1095 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
1096 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
1097 hw_p->rx_ready[i] = -1;
1098 debug("RX_BUFF %d @ 0x%08lx\n", i, (u32)hw_p->rx[i].data_ptr);
1103 reg |= dev->enetaddr[0]; /* set high address */
1105 reg |= dev->enetaddr[1];
1107 out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg);
1110 reg |= dev->enetaddr[2]; /* set low address */
1112 reg |= dev->enetaddr[3];
1114 reg |= dev->enetaddr[4];
1116 reg |= dev->enetaddr[5];
1118 out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg);
1122 /* setup MAL tx & rx channel pointers */
1123 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
1124 mtdcr (maltxctp2r, hw_p->tx_phys);
1126 mtdcr (maltxctp1r, hw_p->tx_phys);
1128 #if defined(CONFIG_440)
1129 mtdcr (maltxbattr, 0x0);
1130 mtdcr (malrxbattr, 0x0);
1133 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
1134 mtdcr (malrxctp8r, hw_p->rx);
1135 /* set RX buffer size */
1136 mtdcr (malrcbs8, ENET_MAX_MTU_ALIGNED / 16);
1138 mtdcr (malrxctp1r, hw_p->rx_phys);
1139 /* set RX buffer size */
1140 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
1143 #if defined (CONFIG_440GX)
1145 /* setup MAL tx & rx channel pointers */
1146 mtdcr (maltxbattr, 0x0);
1147 mtdcr (malrxbattr, 0x0);
1148 mtdcr (maltxctp2r, hw_p->tx_phys);
1149 mtdcr (malrxctp2r, hw_p->rx_phys);
1150 /* set RX buffer size */
1151 mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
1154 /* setup MAL tx & rx channel pointers */
1155 mtdcr (maltxbattr, 0x0);
1156 mtdcr (maltxctp3r, hw_p->tx_phys);
1157 mtdcr (malrxbattr, 0x0);
1158 mtdcr (malrxctp3r, hw_p->rx_phys);
1159 /* set RX buffer size */
1160 mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
1162 #endif /* CONFIG_440GX */
1165 /* setup MAL tx & rx channel pointers */
1166 #if defined(CONFIG_440)
1167 mtdcr (maltxbattr, 0x0);
1168 mtdcr (malrxbattr, 0x0);
1170 mtdcr (maltxctp0r, hw_p->tx_phys);
1171 mtdcr (malrxctp0r, hw_p->rx_phys);
1172 /* set RX buffer size */
1173 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
1177 /* Enable MAL transmit and receive channels */
1178 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
1179 mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
1181 mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
1183 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
1185 /* set transmit enable & receive enable */
1186 out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
1188 mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr);
1190 /* set rx-/tx-fifo size */
1191 mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE;
1194 if (speed == _1000BASET) {
1195 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1196 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1199 mfsdr (sdr_pfc1, pfc1);
1200 pfc1 |= SDR0_PFC1_EM_1000;
1201 mtsdr (sdr_pfc1, pfc1);
1203 mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
1204 } else if (speed == _100BASET)
1205 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
1207 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
1209 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
1211 out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg);
1213 /* Enable broadcast and indvidual address */
1214 /* TBS: enabling runts as some misbehaved nics will send runts */
1215 out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
1217 /* we probably need to set the tx mode1 reg? maybe at tx time */
1219 /* set transmit request threshold register */
1220 out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
1222 /* set receive low/high water mark register */
1223 #if defined(CONFIG_440)
1224 /* 440s has a 64 byte burst length */
1225 out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
1227 /* 405s have a 16 byte burst length */
1228 out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
1229 #endif /* defined(CONFIG_440) */
1230 out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
1232 /* Set fifo limit entry in tx mode 0 */
1233 out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
1235 out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
1238 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
1239 if (speed == _100BASET)
1240 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
1242 out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
1243 out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
1245 if (hw_p->first_init == 0) {
1247 * Connect interrupt service routines
1249 irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
1250 (interrupt_handler_t *) enetInt, dev);
1253 mtmsr (msr); /* enable interrupts again */
1256 hw_p->first_init = 1;
1262 static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
1265 struct enet_frame *ef_ptr;
1266 ulong time_start, time_now;
1267 unsigned long temp_txm0;
1268 EMAC_4XX_HW_PST hw_p = dev->priv;
1270 ef_ptr = (struct enet_frame *) ptr;
1272 /*-----------------------------------------------------------------------+
1273 * Copy in our address into the frame.
1274 *-----------------------------------------------------------------------*/
1275 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
1277 /*-----------------------------------------------------------------------+
1278 * If frame is too long or too short, modify length.
1279 *-----------------------------------------------------------------------*/
1280 /* TBS: where does the fragment go???? */
1281 if (len > ENET_MAX_MTU)
1284 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
1285 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
1286 flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len);
1288 /*-----------------------------------------------------------------------+
1289 * set TX Buffer busy, and send it
1290 *-----------------------------------------------------------------------*/
1291 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
1292 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
1293 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
1294 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
1295 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
1297 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
1298 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
1302 out_be32((void *)EMAC_TXM0 + hw_p->hw_addr,
1303 in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
1304 #ifdef INFO_4XX_ENET
1305 hw_p->stats.pkts_tx++;
1308 /*-----------------------------------------------------------------------+
1309 * poll unitl the packet is sent and then make sure it is OK
1310 *-----------------------------------------------------------------------*/
1311 time_start = get_timer (0);
1313 temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr);
1314 /* loop until either TINT turns on or 3 seconds elapse */
1315 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
1316 /* transmit is done, so now check for errors
1317 * If there is an error, an interrupt should
1318 * happen when we return
1320 time_now = get_timer (0);
1321 if ((time_now - time_start) > 3000) {
1331 #if defined (CONFIG_440) || defined(CONFIG_405EX)
1333 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1335 * Hack: On 440SP all enet irq sources are located on UIC1
1336 * Needs some cleanup. --sr
1338 #define UIC0MSR uic1msr
1339 #define UIC0SR uic1sr
1340 #define UIC1MSR uic1msr
1341 #define UIC1SR uic1sr
1342 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
1344 * Hack: On 460EX/GT all enet irq sources are located on UIC2
1345 * Needs some cleanup. --ag
1347 #define UIC0MSR uic2msr
1348 #define UIC0SR uic2sr
1349 #define UIC1MSR uic2msr
1350 #define UIC1SR uic2sr
1352 #define UIC0MSR uic0msr
1353 #define UIC0SR uic0sr
1354 #define UIC1MSR uic1msr
1355 #define UIC1SR uic1sr
1358 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1359 defined(CONFIG_405EX)
1360 #define UICMSR_ETHX uic0msr
1361 #define UICSR_ETHX uic0sr
1362 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
1363 #define UICMSR_ETHX uic2msr
1364 #define UICSR_ETHX uic2sr
1366 #define UICMSR_ETHX uic1msr
1367 #define UICSR_ETHX uic1sr
1370 int enetInt (struct eth_device *dev)
1373 int rc = -1; /* default to not us */
1374 unsigned long mal_isr;
1375 unsigned long emac_isr = 0;
1376 unsigned long mal_rx_eob;
1377 unsigned long my_uic0msr, my_uic1msr;
1378 unsigned long my_uicmsr_ethx;
1380 #if defined(CONFIG_440GX)
1381 unsigned long my_uic2msr;
1383 EMAC_4XX_HW_PST hw_p;
1386 * Because the mal is generic, we need to get the current
1389 #if defined(CONFIG_NET_MULTI)
1390 dev = eth_get_dev();
1397 /* enter loop that stays in interrupt code until nothing to service */
1401 my_uic0msr = mfdcr (UIC0MSR);
1402 my_uic1msr = mfdcr (UIC1MSR);
1403 #if defined(CONFIG_440GX)
1404 my_uic2msr = mfdcr (uic2msr);
1406 my_uicmsr_ethx = mfdcr (UICMSR_ETHX);
1408 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
1409 && !(my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))
1410 && !(my_uicmsr_ethx & (UIC_ETH0 | UIC_ETH1))) {
1414 #if defined (CONFIG_440GX)
1415 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
1416 && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
1421 /* get and clear controller status interrupts */
1422 /* look at Mal and EMAC interrupts */
1423 if ((my_uic0msr & (UIC_MRE | UIC_MTE))
1424 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1425 /* we have a MAL interrupt */
1426 mal_isr = mfdcr (malesr);
1427 /* look for mal error */
1428 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
1429 mal_err (dev, mal_isr, my_uic1msr, MAL_UIC_DEF, MAL_UIC_ERR);
1435 /* port by port dispatch of emac interrupts */
1436 if (hw_p->devnum == 0) {
1437 if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */
1438 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
1439 if ((hw_p->emac_ier & emac_isr) != 0) {
1440 emac_err (dev, emac_isr);
1445 if ((hw_p->emac_ier & emac_isr)
1446 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1447 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1448 mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1449 mtdcr (UICSR_ETHX, UIC_ETH0); /* Clear */
1450 return (rc); /* we had errors so get out */
1454 #if !defined(CONFIG_440SP)
1455 if (hw_p->devnum == 1) {
1456 if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */
1457 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
1458 if ((hw_p->emac_ier & emac_isr) != 0) {
1459 emac_err (dev, emac_isr);
1464 if ((hw_p->emac_ier & emac_isr)
1465 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1466 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1467 mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1468 mtdcr (UICSR_ETHX, UIC_ETH1); /* Clear */
1469 return (rc); /* we had errors so get out */
1472 #if defined (CONFIG_440GX)
1473 if (hw_p->devnum == 2) {
1474 if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
1475 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
1476 if ((hw_p->emac_ier & emac_isr) != 0) {
1477 emac_err (dev, emac_isr);
1482 if ((hw_p->emac_ier & emac_isr)
1483 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1484 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1485 mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1486 mtdcr (uic2sr, UIC_ETH2);
1487 return (rc); /* we had errors so get out */
1491 if (hw_p->devnum == 3) {
1492 if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */
1493 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
1494 if ((hw_p->emac_ier & emac_isr) != 0) {
1495 emac_err (dev, emac_isr);
1500 if ((hw_p->emac_ier & emac_isr)
1501 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1502 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1503 mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1504 mtdcr (uic2sr, UIC_ETH3);
1505 return (rc); /* we had errors so get out */
1508 #endif /* CONFIG_440GX */
1509 #endif /* !CONFIG_440SP */
1511 /* handle MAX TX EOB interrupt from a tx */
1512 if (my_uic0msr & UIC_MTE) {
1513 mal_rx_eob = mfdcr (maltxeobisr);
1514 mtdcr (maltxeobisr, mal_rx_eob);
1515 mtdcr (UIC0SR, UIC_MTE);
1517 /* handle MAL RX EOB interupt from a receive */
1518 /* check for EOB on valid channels */
1519 if (my_uic0msr & UIC_MRE) {
1520 mal_rx_eob = mfdcr (malrxeobisr);
1522 (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)))
1523 != 0) { /* call emac routine for channel x */
1525 mtdcr(malrxeobisr, mal_rx_eob); */
1526 enet_rcv (dev, emac_isr);
1527 /* indicate that we serviced an interrupt */
1533 mtdcr (UIC0SR, UIC_MRE); /* Clear */
1534 mtdcr (UIC1SR, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1535 switch (hw_p->devnum) {
1537 mtdcr (UICSR_ETHX, UIC_ETH0);
1540 mtdcr (UICSR_ETHX, UIC_ETH1);
1542 #if defined (CONFIG_440GX)
1544 mtdcr (uic2sr, UIC_ETH2);
1547 mtdcr (uic2sr, UIC_ETH3);
1549 #endif /* CONFIG_440GX */
1558 #else /* CONFIG_440 */
1560 int enetInt (struct eth_device *dev)
1563 int rc = -1; /* default to not us */
1564 unsigned long mal_isr;
1565 unsigned long emac_isr = 0;
1566 unsigned long mal_rx_eob;
1567 unsigned long my_uicmsr;
1569 EMAC_4XX_HW_PST hw_p;
1572 * Because the mal is generic, we need to get the current
1575 #if defined(CONFIG_NET_MULTI)
1576 dev = eth_get_dev();
1583 /* enter loop that stays in interrupt code until nothing to service */
1587 my_uicmsr = mfdcr (uicmsr);
1589 if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
1592 /* get and clear controller status interrupts */
1593 /* look at Mal and EMAC interrupts */
1594 if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
1595 mal_isr = mfdcr (malesr);
1596 /* look for mal error */
1597 if ((my_uicmsr & MAL_UIC_ERR) != 0) {
1598 mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
1604 /* port by port dispatch of emac interrupts */
1606 if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
1607 emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr);
1608 if ((hw_p->emac_ier & emac_isr) != 0) {
1609 emac_err (dev, emac_isr);
1614 if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
1615 mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
1616 return (rc); /* we had errors so get out */
1619 /* handle MAX TX EOB interrupt from a tx */
1620 if (my_uicmsr & UIC_MAL_TXEOB) {
1621 mal_rx_eob = mfdcr (maltxeobisr);
1622 mtdcr (maltxeobisr, mal_rx_eob);
1623 mtdcr (uicsr, UIC_MAL_TXEOB);
1625 /* handle MAL RX EOB interupt from a receive */
1626 /* check for EOB on valid channels */
1627 if (my_uicmsr & UIC_MAL_RXEOB)
1629 mal_rx_eob = mfdcr (malrxeobisr);
1630 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1632 mtdcr(malrxeobisr, mal_rx_eob); */
1633 enet_rcv (dev, emac_isr);
1634 /* indicate that we serviced an interrupt */
1639 mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
1640 #if defined(CONFIG_405EZ)
1641 mtsdr (sdricintstat, SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
1642 #endif /* defined(CONFIG_405EZ) */
1649 #endif /* CONFIG_440 */
1651 /*-----------------------------------------------------------------------------+
1653 *-----------------------------------------------------------------------------*/
1654 static void mal_err (struct eth_device *dev, unsigned long isr,
1655 unsigned long uic, unsigned long maldef,
1656 unsigned long mal_errr)
1658 EMAC_4XX_HW_PST hw_p = dev->priv;
1660 mtdcr (malesr, isr); /* clear interrupt */
1662 /* clear DE interrupt */
1663 mtdcr (maltxdeir, 0xC0000000);
1664 mtdcr (malrxdeir, 0x80000000);
1666 #ifdef INFO_4XX_ENET
1667 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
1670 eth_init (hw_p->bis); /* start again... */
1673 /*-----------------------------------------------------------------------------+
1674 * EMAC Error Routine
1675 *-----------------------------------------------------------------------------*/
1676 static void emac_err (struct eth_device *dev, unsigned long isr)
1678 EMAC_4XX_HW_PST hw_p = dev->priv;
1680 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
1681 out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr);
1684 /*-----------------------------------------------------------------------------+
1685 * enet_rcv() handles the ethernet receive data
1686 *-----------------------------------------------------------------------------*/
1687 static void enet_rcv (struct eth_device *dev, unsigned long malisr)
1689 struct enet_frame *ef_ptr;
1690 unsigned long data_len;
1691 unsigned long rx_eob_isr;
1692 EMAC_4XX_HW_PST hw_p = dev->priv;
1698 rx_eob_isr = mfdcr (malrxeobisr);
1699 if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) {
1701 mtdcr (malrxeobisr, rx_eob_isr);
1704 while (1) { /* do all */
1707 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
1708 || (loop_count >= NUM_RX_BUFF))
1713 data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff; /* Get len */
1715 if (data_len > ENET_MAX_MTU) /* Check len */
1718 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
1720 hw_p->stats.rx_err_log[hw_p->
1723 hw_p->rx_err_index++;
1724 if (hw_p->rx_err_index ==
1726 hw_p->rx_err_index =
1729 } /* data_len < max mtu */
1731 if (!data_len) { /* no data */
1732 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
1734 hw_p->stats.data_len_err++; /* Error at Rx */
1739 /* Check if user has already eaten buffer */
1740 /* if not => ERROR */
1741 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
1742 if (hw_p->is_receiving)
1743 printf ("ERROR : Receive buffers are full!\n");
1746 hw_p->stats.rx_frames++;
1747 hw_p->stats.rx += data_len;
1748 ef_ptr = (struct enet_frame *) hw_p->rx[i].
1750 #ifdef INFO_4XX_ENET
1751 hw_p->stats.pkts_rx++;
1756 hw_p->rx_ready[hw_p->rx_i_index] = i;
1758 if (NUM_RX_BUFF == hw_p->rx_i_index)
1759 hw_p->rx_i_index = 0;
1762 if (NUM_RX_BUFF == hw_p->rx_slot)
1766 * free receive buffer only when
1767 * buffer has been handled (eth_rx)
1768 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1772 } /* if EMACK_RXCHL */
1776 static int ppc_4xx_eth_rx (struct eth_device *dev)
1781 EMAC_4XX_HW_PST hw_p = dev->priv;
1783 hw_p->is_receiving = 1; /* tell driver */
1787 * use ring buffer and
1788 * get index from rx buffer desciptor queue
1790 user_index = hw_p->rx_ready[hw_p->rx_u_index];
1791 if (user_index == -1) {
1793 break; /* nothing received - leave for() loop */
1797 mtmsr (msr & ~(MSR_EE));
1799 length = hw_p->rx[user_index].data_len & 0x0fff;
1801 /* Pass the packet up to the protocol layers. */
1802 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1803 /* NetReceive(NetRxPackets[i], length); */
1804 invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr,
1805 (u32)hw_p->rx[user_index].data_ptr +
1807 NetReceive (NetRxPackets[user_index], length - 4);
1808 /* Free Recv Buffer */
1809 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
1810 /* Free rx buffer descriptor queue */
1811 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1813 if (NUM_RX_BUFF == hw_p->rx_u_index)
1814 hw_p->rx_u_index = 0;
1816 #ifdef INFO_4XX_ENET
1817 hw_p->stats.pkts_handled++;
1820 mtmsr (msr); /* Enable IRQ's */
1823 hw_p->is_receiving = 0; /* tell driver */
1828 int ppc_4xx_eth_initialize (bd_t * bis)
1830 static int virgin = 0;
1831 struct eth_device *dev;
1833 EMAC_4XX_HW_PST hw = NULL;
1834 u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
1837 #if defined(CONFIG_440GX)
1840 mfsdr (sdr_pfc1, pfc1);
1841 pfc1 &= ~(0x01e00000);
1843 mtsdr (sdr_pfc1, pfc1);
1846 /* first clear all mac-addresses */
1847 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
1848 memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
1850 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1852 default: /* fall through */
1854 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1855 bis->bi_enetaddr, 6);
1856 hw_addr[eth_num] = 0x0;
1858 #ifdef CONFIG_HAS_ETH1
1860 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1861 bis->bi_enet1addr, 6);
1862 hw_addr[eth_num] = 0x100;
1865 #ifdef CONFIG_HAS_ETH2
1867 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1868 bis->bi_enet2addr, 6);
1869 hw_addr[eth_num] = 0x400;
1872 #ifdef CONFIG_HAS_ETH3
1874 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1875 bis->bi_enet3addr, 6);
1876 hw_addr[eth_num] = 0x600;
1882 /* set phy num and mode */
1883 bis->bi_phynum[0] = CONFIG_PHY_ADDR;
1884 bis->bi_phymode[0] = 0;
1886 #if defined(CONFIG_PHY1_ADDR)
1887 bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
1888 bis->bi_phymode[1] = 0;
1890 #if defined(CONFIG_440GX)
1891 bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
1892 bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
1893 bis->bi_phymode[2] = 2;
1894 bis->bi_phymode[3] = 2;
1897 #if defined(CONFIG_440GX) || \
1898 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1899 defined(CONFIG_405EX)
1900 ppc_4xx_eth_setup_bridge(0, bis);
1903 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1905 * See if we can actually bring up the interface,
1906 * otherwise, skip it
1908 if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
1909 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1913 /* Allocate device structure */
1914 dev = (struct eth_device *) malloc (sizeof (*dev));
1916 printf ("ppc_4xx_eth_initialize: "
1917 "Cannot allocate eth_device %d\n", eth_num);
1920 memset(dev, 0, sizeof(*dev));
1922 /* Allocate our private use data */
1923 hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
1925 printf ("ppc_4xx_eth_initialize: "
1926 "Cannot allocate private hw data for eth_device %d",
1931 memset(hw, 0, sizeof(*hw));
1933 hw->hw_addr = hw_addr[eth_num];
1934 memcpy (dev->enetaddr, ethaddr[eth_num], 6);
1935 hw->devnum = eth_num;
1936 hw->print_speed = 1;
1938 sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
1939 dev->priv = (void *) hw;
1940 dev->init = ppc_4xx_eth_init;
1941 dev->halt = ppc_4xx_eth_halt;
1942 dev->send = ppc_4xx_eth_send;
1943 dev->recv = ppc_4xx_eth_rx;
1946 /* set the MAL IER ??? names may change with new spec ??? */
1947 #if defined(CONFIG_440SPE) || \
1948 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1949 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1950 defined(CONFIG_405EX)
1952 MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
1953 MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
1956 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
1957 MAL_IER_OPBE | MAL_IER_PLBE;
1959 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
1960 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
1961 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
1962 mtdcr (malier, mal_ier);
1964 /* install MAL interrupt handler */
1965 irq_install_handler (VECNUM_MS,
1966 (interrupt_handler_t *) enetInt,
1968 irq_install_handler (VECNUM_MTE,
1969 (interrupt_handler_t *) enetInt,
1971 irq_install_handler (VECNUM_MRE,
1972 (interrupt_handler_t *) enetInt,
1974 irq_install_handler (VECNUM_TXDE,
1975 (interrupt_handler_t *) enetInt,
1977 irq_install_handler (VECNUM_RXDE,
1978 (interrupt_handler_t *) enetInt,
1983 #if defined(CONFIG_NET_MULTI)
1989 #if defined(CONFIG_NET_MULTI)
1990 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
1991 miiphy_register (dev->name,
1992 emac4xx_miiphy_read, emac4xx_miiphy_write);
1995 } /* end for each supported device */
2000 #if !defined(CONFIG_NET_MULTI)
2001 void eth_halt (void) {
2003 ppc_4xx_eth_halt(emac0_dev);
2009 int eth_init (bd_t *bis)
2011 ppc_4xx_eth_initialize(bis);
2013 return ppc_4xx_eth_init(emac0_dev, bis);
2015 printf("ERROR: ethaddr not set!\n");
2020 int eth_send(volatile void *packet, int length)
2022 return (ppc_4xx_eth_send(emac0_dev, packet, length));
2027 return (ppc_4xx_eth_rx(emac0_dev));
2030 int emac4xx_miiphy_initialize (bd_t * bis)
2032 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
2033 miiphy_register ("ppc_4xx_eth0",
2034 emac4xx_miiphy_read, emac4xx_miiphy_write);
2039 #endif /* !defined(CONFIG_NET_MULTI) */