1 /*-----------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
23 * File Name: enetemac.c
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
49 * - Receive buffer descriptor ring is used to send buffers
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 *-----------------------------------------------------------------------------*
71 * 17-Nov-03 travis.sawyer@sandburst.com
72 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
73 * in the 440GX. This port should work with the 440GP
75 * 15-Aug-05 sr@denx.de
76 * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
77 now handling all 4xx cpu's.
78 *-----------------------------------------------------------------------------*/
83 #include <asm/processor.h>
86 #include <ppc4xx_enet.h>
93 * Only compile for platform with AMCC EMAC ethernet controller and
94 * network support enabled.
95 * Remark: CONFIG_405 describes Xilinx PPC405 FPGA without EMAC controller!
97 #if defined(CONFIG_CMD_NET) && !defined(CONFIG_405) && !defined(CONFIG_IOP480)
99 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
100 #error "CONFIG_MII has to be defined!"
103 #if defined(CONFIG_NETCONSOLE) && !defined(CONFIG_NET_MULTI)
104 #error "CONFIG_NET_MULTI has to be defined for NetConsole"
107 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
108 #define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
110 /* Ethernet Transmit and Receive Buffers */
112 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
113 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
115 #define ENET_MAX_MTU PKTSIZE
116 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
118 /*-----------------------------------------------------------------------------+
119 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
120 * Interrupt Controller).
121 *-----------------------------------------------------------------------------*/
122 #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
123 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
124 #define EMAC_UIC_DEF UIC_ENET
125 #define EMAC_UIC_DEF1 UIC_ENET1
126 #define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
130 #define BI_PHYMODE_NONE 0
131 #define BI_PHYMODE_ZMII 1
132 #define BI_PHYMODE_RGMII 2
133 #define BI_PHYMODE_GMII 3
134 #define BI_PHYMODE_RTBI 4
135 #define BI_PHYMODE_TBI 5
136 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
137 defined(CONFIG_405EX)
138 #define BI_PHYMODE_SMII 6
139 #define BI_PHYMODE_MII 7
142 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
143 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
144 defined(CONFIG_405EX)
145 #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
148 /*-----------------------------------------------------------------------------+
149 * Global variables. TX and RX descriptors and buffers.
150 *-----------------------------------------------------------------------------*/
152 static uint32_t mal_ier;
154 #if !defined(CONFIG_NET_MULTI)
155 struct eth_device *emac0_dev = NULL;
159 * Get count of EMAC devices (doesn't have to be the max. possible number
160 * supported by the cpu)
162 * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
163 * EMAC count is possible. As it is needed for the Kilauea/Haleakala
164 * 405EX/405EXr eval board, using the same binary.
166 #if defined(CONFIG_BOARD_EMAC_COUNT)
167 #define LAST_EMAC_NUM board_emac_count()
168 #else /* CONFIG_BOARD_EMAC_COUNT */
169 #if defined(CONFIG_HAS_ETH3)
170 #define LAST_EMAC_NUM 4
171 #elif defined(CONFIG_HAS_ETH2)
172 #define LAST_EMAC_NUM 3
173 #elif defined(CONFIG_HAS_ETH1)
174 #define LAST_EMAC_NUM 2
176 #define LAST_EMAC_NUM 1
178 #endif /* CONFIG_BOARD_EMAC_COUNT */
180 /* normal boards start with EMAC0 */
181 #if !defined(CONFIG_EMAC_NR_START)
182 #define CONFIG_EMAC_NR_START 0
185 #if defined(CONFIG_405EX) || defined(CONFIG_440EPX)
186 #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev)))
188 #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * 2))
191 /*-----------------------------------------------------------------------------+
192 * Prototypes and externals.
193 *-----------------------------------------------------------------------------*/
194 static void enet_rcv (struct eth_device *dev, unsigned long malisr);
196 int enetInt (struct eth_device *dev);
197 static void mal_err (struct eth_device *dev, unsigned long isr,
198 unsigned long uic, unsigned long maldef,
199 unsigned long mal_errr);
200 static void emac_err (struct eth_device *dev, unsigned long isr);
202 extern int phy_setup_aneg (char *devname, unsigned char addr);
203 extern int emac4xx_miiphy_read (char *devname, unsigned char addr,
204 unsigned char reg, unsigned short *value);
205 extern int emac4xx_miiphy_write (char *devname, unsigned char addr,
206 unsigned char reg, unsigned short value);
208 int board_emac_count(void);
210 /*-----------------------------------------------------------------------------+
212 | Disable MAL channel, and EMACn
213 +-----------------------------------------------------------------------------*/
214 static void ppc_4xx_eth_halt (struct eth_device *dev)
216 EMAC_4XX_HW_PST hw_p = dev->priv;
217 uint32_t failsafe = 10000;
218 #if defined(CONFIG_440SPE) || \
219 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
220 defined(CONFIG_405EX)
224 out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
226 /* 1st reset MAL channel */
227 /* Note: writing a 0 to a channel has no effect */
228 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
229 mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
231 mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
233 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
236 while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
237 udelay (1000); /* Delay 1 MS so as not to hammer the register */
244 #if defined(CONFIG_440SPE) || \
245 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
246 defined(CONFIG_405EX)
247 /* provide clocks for EMAC internal loopback */
248 mfsdr (sdr_mfr, mfr);
249 mfr |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
253 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
255 #if defined(CONFIG_440SPE) || \
256 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
257 defined(CONFIG_405EX)
258 /* remove clocks for EMAC internal loopback */
259 mfsdr (sdr_mfr, mfr);
260 mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
265 #ifndef CONFIG_NETCONSOLE
266 hw_p->print_speed = 1; /* print speed message again next time */
272 #if defined (CONFIG_440GX)
273 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
276 unsigned long zmiifer;
277 unsigned long rmiifer;
279 mfsdr(sdr_pfc1, pfc1);
280 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
287 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
288 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
289 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
290 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
291 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
292 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
293 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
294 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
297 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
298 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
299 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
300 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
301 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
302 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
303 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
304 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
307 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
308 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
309 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
310 bis->bi_phymode[1] = BI_PHYMODE_NONE;
311 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
312 bis->bi_phymode[3] = BI_PHYMODE_NONE;
315 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
316 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
317 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
318 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
319 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
320 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
321 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
322 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
325 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
326 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
327 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
328 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
329 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
330 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
331 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
332 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
335 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
336 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
337 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
338 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
339 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
340 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
344 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
346 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
347 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
348 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
349 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
353 /* Ensure we setup mdio for this devnum and ONLY this devnum */
354 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
356 out32 (ZMII_FER, zmiifer);
357 out32 (RGMII_FER, rmiifer);
361 #endif /* CONFIG_440_GX */
363 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
364 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
366 unsigned long zmiifer=0x0;
369 mfsdr(sdr_pfc1, pfc1);
370 pfc1 &= SDR0_PFC1_SELECT_MASK;
373 case SDR0_PFC1_SELECT_CONFIG_2:
375 out32 (ZMII_FER, 0x00);
376 out32 (RGMII_FER, 0x00000037);
377 bis->bi_phymode[0] = BI_PHYMODE_GMII;
378 bis->bi_phymode[1] = BI_PHYMODE_NONE;
380 case SDR0_PFC1_SELECT_CONFIG_4:
381 /* 2 x RGMII ports */
382 out32 (ZMII_FER, 0x00);
383 out32 (RGMII_FER, 0x00000055);
384 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
385 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
387 case SDR0_PFC1_SELECT_CONFIG_6:
390 ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
391 ((ZMII_FER_SMII) << ZMII_FER_V(1)));
392 out32 (RGMII_FER, 0x00000000);
393 bis->bi_phymode[0] = BI_PHYMODE_SMII;
394 bis->bi_phymode[1] = BI_PHYMODE_SMII;
396 case SDR0_PFC1_SELECT_CONFIG_1_2:
397 /* only 1 x MII supported */
398 out32 (ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
399 out32 (RGMII_FER, 0x00000000);
400 bis->bi_phymode[0] = BI_PHYMODE_MII;
401 bis->bi_phymode[1] = BI_PHYMODE_NONE;
407 /* Ensure we setup mdio for this devnum and ONLY this devnum */
408 zmiifer = in32 (ZMII_FER);
409 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
410 out32 (ZMII_FER, zmiifer);
414 #endif /* CONFIG_440EPX */
416 #if defined(CONFIG_405EX)
417 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
422 * Right now only 2*RGMII is supported. Please extend when needed.
427 /* 2 x RGMII ports */
428 out32 (RGMII_FER, 0x00000055);
429 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
430 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
439 /* Ensure we setup mdio for this devnum and ONLY this devnum */
440 gmiifer = in32(RGMII_FER);
441 gmiifer |= (1 << (19-devnum));
442 out32 (RGMII_FER, gmiifer);
446 #endif /* CONFIG_405EX */
448 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
451 unsigned long reg = 0;
454 unsigned long duplex;
455 unsigned long failsafe;
457 unsigned short devnum;
458 unsigned short reg_short;
459 #if defined(CONFIG_440GX) || \
460 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
461 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
462 defined(CONFIG_405EX)
464 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
465 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
466 defined(CONFIG_405EX)
470 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
471 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
472 defined(CONFIG_405EX)
476 EMAC_4XX_HW_PST hw_p = dev->priv;
478 /* before doing anything, figure out if we have a MAC address */
480 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
481 printf("ERROR: ethaddr not set!\n");
485 #if defined(CONFIG_440GX) || \
486 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
487 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
488 defined(CONFIG_405EX)
489 /* Need to get the OPB frequency so we can access the PHY */
490 get_sys_info (&sysinfo);
494 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
496 devnum = hw_p->devnum;
501 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
502 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
503 * is possible that new packets (without relationship with
504 * current transfer) have got the time to arrived before
505 * netloop calls eth_halt
507 printf ("About preceeding transfer (eth%d):\n"
508 "- Sent packet number %d\n"
509 "- Received packet number %d\n"
510 "- Handled packet number %d\n",
513 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
515 hw_p->stats.pkts_tx = 0;
516 hw_p->stats.pkts_rx = 0;
517 hw_p->stats.pkts_handled = 0;
518 hw_p->print_speed = 1; /* print speed message again next time */
521 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
522 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
524 hw_p->rx_slot = 0; /* MAL Receive Slot */
525 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
526 hw_p->rx_u_index = 0; /* Receive User Queue Index */
528 hw_p->tx_slot = 0; /* MAL Transmit Slot */
529 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
530 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
532 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
534 /* NOTE: 440GX spec states that mode is mutually exclusive */
535 /* NOTE: Therefore, disable all other EMACS, since we handle */
536 /* NOTE: only one emac at a time */
541 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
542 out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
543 #elif defined(CONFIG_440GX) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
544 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
545 #elif defined(CONFIG_440GP)
547 out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
549 if ((devnum == 0) || (devnum == 1)) {
550 out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
551 } else { /* ((devnum == 2) || (devnum == 3)) */
552 out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
553 out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
554 (RGMII_FER_RGMII << RGMII_FER_V (3))));
558 out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
559 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
560 #if defined(CONFIG_405EX)
561 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
564 __asm__ volatile ("eieio");
566 /* reset emac so we have access to the phy */
567 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
568 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
569 defined(CONFIG_405EX)
570 /* provide clocks for EMAC internal loopback */
571 mfsdr (sdr_mfr, mfr);
572 mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
576 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
577 __asm__ volatile ("eieio");
580 while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
585 printf("\nProblem resetting EMAC!\n");
587 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
588 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
589 defined(CONFIG_405EX)
590 /* remove clocks for EMAC internal loopback */
591 mfsdr (sdr_mfr, mfr);
592 mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
596 #if defined(CONFIG_440GX) || \
597 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
598 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
599 defined(CONFIG_405EX)
600 /* Whack the M1 register */
602 mode_reg &= ~0x00000038;
603 if (sysinfo.freqOPB <= 50000000);
604 else if (sysinfo.freqOPB <= 66666667)
605 mode_reg |= EMAC_M1_OBCI_66;
606 else if (sysinfo.freqOPB <= 83333333)
607 mode_reg |= EMAC_M1_OBCI_83;
608 else if (sysinfo.freqOPB <= 100000000)
609 mode_reg |= EMAC_M1_OBCI_100;
611 mode_reg |= EMAC_M1_OBCI_GT100;
613 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
614 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
616 /* wait for PHY to complete auto negotiation */
618 #ifndef CONFIG_CS8952_PHY
621 reg = CONFIG_PHY_ADDR;
623 #if defined (CONFIG_PHY1_ADDR)
625 reg = CONFIG_PHY1_ADDR;
628 #if defined (CONFIG_440GX)
630 reg = CONFIG_PHY2_ADDR;
633 reg = CONFIG_PHY3_ADDR;
637 reg = CONFIG_PHY_ADDR;
641 bis->bi_phynum[devnum] = reg;
643 #if defined(CONFIG_PHY_RESET)
645 * Reset the phy, only if its the first time through
646 * otherwise, just check the speeds & feeds
648 if (hw_p->first_init == 0) {
649 #if defined(CONFIG_M88E1111_PHY)
650 miiphy_write (dev->name, reg, 0x14, 0x0ce3);
651 miiphy_write (dev->name, reg, 0x18, 0x4101);
652 miiphy_write (dev->name, reg, 0x09, 0x0e00);
653 miiphy_write (dev->name, reg, 0x04, 0x01e1);
655 miiphy_reset (dev->name, reg);
657 #if defined(CONFIG_440GX) || \
658 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
659 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
660 defined(CONFIG_405EX)
662 #if defined(CONFIG_CIS8201_PHY)
664 * Cicada 8201 PHY needs to have an extended register whacked
667 if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
668 #if defined(CONFIG_CIS8201_SHORT_ETCH)
669 miiphy_write (dev->name, reg, 23, 0x1300);
671 miiphy_write (dev->name, reg, 23, 0x1000);
674 * Vitesse VSC8201/Cicada CIS8201 errata:
675 * Interoperability problem with Intel 82547EI phys
676 * This work around (provided by Vitesse) changes
677 * the default timer convergence from 8ms to 12ms
679 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
680 miiphy_write (dev->name, reg, 0x08, 0x0200);
681 miiphy_write (dev->name, reg, 0x1f, 0x52b5);
682 miiphy_write (dev->name, reg, 0x02, 0x0004);
683 miiphy_write (dev->name, reg, 0x01, 0x0671);
684 miiphy_write (dev->name, reg, 0x00, 0x8fae);
685 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
686 miiphy_write (dev->name, reg, 0x08, 0x0000);
687 miiphy_write (dev->name, reg, 0x1f, 0x0000);
688 /* end Vitesse/Cicada errata */
692 #if defined(CONFIG_ET1011C_PHY)
694 * Agere ET1011c PHY needs to have an extended register whacked
697 if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
698 miiphy_read (dev->name, reg, 0x16, ®_short);
700 reg_short |= 0x6; /* RGMII DLL Delay*/
701 miiphy_write (dev->name, reg, 0x16, reg_short);
703 miiphy_read (dev->name, reg, 0x17, ®_short);
704 reg_short &= ~(0x40);
705 miiphy_write (dev->name, reg, 0x17, reg_short);
707 miiphy_write(dev->name, reg, 0x1c, 0x74f0);
712 /* Start/Restart autonegotiation */
713 phy_setup_aneg (dev->name, reg);
716 #endif /* defined(CONFIG_PHY_RESET) */
718 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
721 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
723 if ((reg_short & PHY_BMSR_AUTN_ABLE)
724 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
725 puts ("Waiting for PHY auto negotiation to complete");
727 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
731 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
732 puts (" TIMEOUT !\n");
736 if ((i++ % 1000) == 0) {
739 udelay (1000); /* 1 ms */
740 miiphy_read (dev->name, reg, PHY_BMSR, ®_short);
744 udelay (500000); /* another 500 ms (results in faster booting) */
746 #endif /* #ifndef CONFIG_CS8952_PHY */
748 speed = miiphy_speed (dev->name, reg);
749 duplex = miiphy_duplex (dev->name, reg);
751 if (hw_p->print_speed) {
752 hw_p->print_speed = 0;
753 printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
754 (int) speed, (duplex == HALF) ? "HALF" : "FULL",
758 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
759 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
760 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
763 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
765 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
770 /* Set ZMII/RGMII speed according to the phy link speed */
771 reg = in32 (ZMII_SSR);
772 if ( (speed == 100) || (speed == 1000) )
773 out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
775 out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
777 if ((devnum == 2) || (devnum == 3)) {
779 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
780 else if (speed == 100)
781 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
782 else if (speed == 10)
783 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
785 printf("Error in RGMII Speed\n");
788 out32 (RGMII_SSR, reg);
790 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
792 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
793 defined(CONFIG_405EX)
795 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
796 else if (speed == 100)
797 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
798 else if (speed == 10)
799 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
801 printf("Error in RGMII Speed\n");
804 out32 (RGMII_SSR, reg);
807 /* set the Mal configuration reg */
808 #if defined(CONFIG_440GX) || \
809 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
810 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
811 defined(CONFIG_405EX)
812 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
813 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
815 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
816 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
817 if (get_pvr() == PVR_440GP_RB) {
818 mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
822 /* Free "old" buffers */
823 if (hw_p->alloc_tx_buf)
824 free (hw_p->alloc_tx_buf);
825 if (hw_p->alloc_rx_buf)
826 free (hw_p->alloc_rx_buf);
829 * Malloc MAL buffer desciptors, make sure they are
830 * aligned on cache line boundary size
831 * (401/403/IOP480 = 16, 405 = 32)
832 * and doesn't cross cache block boundaries.
835 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
836 ((2 * CFG_CACHELINE_SIZE) - 2));
837 if (NULL == hw_p->alloc_tx_buf)
839 if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
841 (mal_desc_t *) ((int) hw_p->alloc_tx_buf +
844 alloc_tx_buf & CACHELINE_MASK));
846 hw_p->tx = hw_p->alloc_tx_buf;
850 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
851 ((2 * CFG_CACHELINE_SIZE) - 2));
852 if (NULL == hw_p->alloc_rx_buf) {
853 free(hw_p->alloc_tx_buf);
854 hw_p->alloc_tx_buf = NULL;
858 if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
860 (mal_desc_t *) ((int) hw_p->alloc_rx_buf +
863 alloc_rx_buf & CACHELINE_MASK));
865 hw_p->rx = hw_p->alloc_rx_buf;
868 for (i = 0; i < NUM_TX_BUFF; i++) {
869 hw_p->tx[i].ctrl = 0;
870 hw_p->tx[i].data_len = 0;
871 if (hw_p->first_init == 0) {
873 (char *) malloc (ENET_MAX_MTU_ALIGNED);
874 if (NULL == hw_p->txbuf_ptr) {
875 free(hw_p->alloc_rx_buf);
876 free(hw_p->alloc_tx_buf);
877 hw_p->alloc_rx_buf = NULL;
878 hw_p->alloc_tx_buf = NULL;
879 for(j = 0; j < i; j++) {
880 free(hw_p->tx[i].data_ptr);
881 hw_p->tx[i].data_ptr = NULL;
885 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
886 if ((NUM_TX_BUFF - 1) == i)
887 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
888 hw_p->tx_run[i] = -1;
890 printf ("TX_BUFF %d @ 0x%08lx\n", i,
891 (ulong) hw_p->tx[i].data_ptr);
895 for (i = 0; i < NUM_RX_BUFF; i++) {
896 hw_p->rx[i].ctrl = 0;
897 hw_p->rx[i].data_len = 0;
898 /* rx[i].data_ptr = (char *) &rx_buff[i]; */
899 hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
900 if ((NUM_RX_BUFF - 1) == i)
901 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
902 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
903 hw_p->rx_ready[i] = -1;
905 printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) hw_p->rx[i].data_ptr);
911 reg |= dev->enetaddr[0]; /* set high address */
913 reg |= dev->enetaddr[1];
915 out32 (EMAC_IAH + hw_p->hw_addr, reg);
918 reg |= dev->enetaddr[2]; /* set low address */
920 reg |= dev->enetaddr[3];
922 reg |= dev->enetaddr[4];
924 reg |= dev->enetaddr[5];
926 out32 (EMAC_IAL + hw_p->hw_addr, reg);
930 /* setup MAL tx & rx channel pointers */
931 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
932 mtdcr (maltxctp2r, hw_p->tx);
934 mtdcr (maltxctp1r, hw_p->tx);
936 #if defined(CONFIG_440)
937 mtdcr (maltxbattr, 0x0);
938 mtdcr (malrxbattr, 0x0);
940 mtdcr (malrxctp1r, hw_p->rx);
941 /* set RX buffer size */
942 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
944 #if defined (CONFIG_440GX)
946 /* setup MAL tx & rx channel pointers */
947 mtdcr (maltxbattr, 0x0);
948 mtdcr (malrxbattr, 0x0);
949 mtdcr (maltxctp2r, hw_p->tx);
950 mtdcr (malrxctp2r, hw_p->rx);
951 /* set RX buffer size */
952 mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
955 /* setup MAL tx & rx channel pointers */
956 mtdcr (maltxbattr, 0x0);
957 mtdcr (maltxctp3r, hw_p->tx);
958 mtdcr (malrxbattr, 0x0);
959 mtdcr (malrxctp3r, hw_p->rx);
960 /* set RX buffer size */
961 mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
963 #endif /* CONFIG_440GX */
966 /* setup MAL tx & rx channel pointers */
967 #if defined(CONFIG_440)
968 mtdcr (maltxbattr, 0x0);
969 mtdcr (malrxbattr, 0x0);
971 mtdcr (maltxctp0r, hw_p->tx);
972 mtdcr (malrxctp0r, hw_p->rx);
973 /* set RX buffer size */
974 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
978 /* Enable MAL transmit and receive channels */
979 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
980 mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
982 mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
984 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
986 /* set transmit enable & receive enable */
987 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
989 /* set receive fifo to 4k and tx fifo to 2k */
990 mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
991 mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
994 if (speed == _1000BASET) {
995 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
996 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
999 mfsdr (sdr_pfc1, pfc1);
1000 pfc1 |= SDR0_PFC1_EM_1000;
1001 mtsdr (sdr_pfc1, pfc1);
1003 mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
1004 } else if (speed == _100BASET)
1005 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
1007 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
1009 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
1011 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
1013 /* Enable broadcast and indvidual address */
1014 /* TBS: enabling runts as some misbehaved nics will send runts */
1015 out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
1017 /* we probably need to set the tx mode1 reg? maybe at tx time */
1019 /* set transmit request threshold register */
1020 out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
1022 /* set receive low/high water mark register */
1023 #if defined(CONFIG_440)
1024 /* 440s has a 64 byte burst length */
1025 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
1027 /* 405s have a 16 byte burst length */
1028 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
1029 #endif /* defined(CONFIG_440) */
1030 out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
1032 /* Set fifo limit entry in tx mode 0 */
1033 out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
1035 out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
1038 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
1039 if (speed == _100BASET)
1040 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
1042 out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
1043 out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
1045 if (hw_p->first_init == 0) {
1047 * Connect interrupt service routines
1049 irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
1050 (interrupt_handler_t *) enetInt, dev);
1053 mtmsr (msr); /* enable interrupts again */
1056 hw_p->first_init = 1;
1062 static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr,
1065 struct enet_frame *ef_ptr;
1066 ulong time_start, time_now;
1067 unsigned long temp_txm0;
1068 EMAC_4XX_HW_PST hw_p = dev->priv;
1070 ef_ptr = (struct enet_frame *) ptr;
1072 /*-----------------------------------------------------------------------+
1073 * Copy in our address into the frame.
1074 *-----------------------------------------------------------------------*/
1075 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
1077 /*-----------------------------------------------------------------------+
1078 * If frame is too long or too short, modify length.
1079 *-----------------------------------------------------------------------*/
1080 /* TBS: where does the fragment go???? */
1081 if (len > ENET_MAX_MTU)
1084 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
1085 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
1087 /*-----------------------------------------------------------------------+
1088 * set TX Buffer busy, and send it
1089 *-----------------------------------------------------------------------*/
1090 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
1091 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
1092 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
1093 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
1094 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
1096 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
1097 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
1099 __asm__ volatile ("eieio");
1101 out32 (EMAC_TXM0 + hw_p->hw_addr,
1102 in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
1103 #ifdef INFO_4XX_ENET
1104 hw_p->stats.pkts_tx++;
1107 /*-----------------------------------------------------------------------+
1108 * poll unitl the packet is sent and then make sure it is OK
1109 *-----------------------------------------------------------------------*/
1110 time_start = get_timer (0);
1112 temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr);
1113 /* loop until either TINT turns on or 3 seconds elapse */
1114 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
1115 /* transmit is done, so now check for errors
1116 * If there is an error, an interrupt should
1117 * happen when we return
1119 time_now = get_timer (0);
1120 if ((time_now - time_start) > 3000) {
1130 #if defined (CONFIG_440) || defined(CONFIG_405EX)
1132 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1134 * Hack: On 440SP all enet irq sources are located on UIC1
1135 * Needs some cleanup. --sr
1137 #define UIC0MSR uic1msr
1138 #define UIC0SR uic1sr
1140 #define UIC0MSR uic0msr
1141 #define UIC0SR uic0sr
1144 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1145 defined(CONFIG_405EX)
1146 #define UICMSR_ETHX uic0msr
1147 #define UICSR_ETHX uic0sr
1149 #define UICMSR_ETHX uic1msr
1150 #define UICSR_ETHX uic1sr
1153 int enetInt (struct eth_device *dev)
1156 int rc = -1; /* default to not us */
1157 unsigned long mal_isr;
1158 unsigned long emac_isr = 0;
1159 unsigned long mal_rx_eob;
1160 unsigned long my_uic0msr, my_uic1msr;
1161 unsigned long my_uicmsr_ethx;
1163 #if defined(CONFIG_440GX)
1164 unsigned long my_uic2msr;
1166 EMAC_4XX_HW_PST hw_p;
1169 * Because the mal is generic, we need to get the current
1172 #if defined(CONFIG_NET_MULTI)
1173 dev = eth_get_dev();
1180 /* enter loop that stays in interrupt code until nothing to service */
1184 my_uic0msr = mfdcr (UIC0MSR);
1185 my_uic1msr = mfdcr (uic1msr);
1186 #if defined(CONFIG_440GX)
1187 my_uic2msr = mfdcr (uic2msr);
1189 my_uicmsr_ethx = mfdcr (UICMSR_ETHX);
1191 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
1192 && !(my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))
1193 && !(my_uicmsr_ethx & (UIC_ETH0 | UIC_ETH1))) {
1197 #if defined (CONFIG_440GX)
1198 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
1199 && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
1204 /* get and clear controller status interrupts */
1205 /* look at Mal and EMAC interrupts */
1206 if ((my_uic0msr & (UIC_MRE | UIC_MTE))
1207 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1208 /* we have a MAL interrupt */
1209 mal_isr = mfdcr (malesr);
1210 /* look for mal error */
1211 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
1212 mal_err (dev, mal_isr, my_uic1msr, MAL_UIC_DEF, MAL_UIC_ERR);
1218 /* port by port dispatch of emac interrupts */
1219 if (hw_p->devnum == 0) {
1220 if (UIC_ETH0 & my_uicmsr_ethx) { /* look for EMAC errors */
1221 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1222 if ((hw_p->emac_ier & emac_isr) != 0) {
1223 emac_err (dev, emac_isr);
1228 if ((hw_p->emac_ier & emac_isr)
1229 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1230 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1231 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1232 mtdcr (UICSR_ETHX, UIC_ETH0); /* Clear */
1233 return (rc); /* we had errors so get out */
1237 #if !defined(CONFIG_440SP)
1238 if (hw_p->devnum == 1) {
1239 if (UIC_ETH1 & my_uicmsr_ethx) { /* look for EMAC errors */
1240 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1241 if ((hw_p->emac_ier & emac_isr) != 0) {
1242 emac_err (dev, emac_isr);
1247 if ((hw_p->emac_ier & emac_isr)
1248 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1249 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1250 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1251 mtdcr (UICSR_ETHX, UIC_ETH1); /* Clear */
1252 return (rc); /* we had errors so get out */
1255 #if defined (CONFIG_440GX)
1256 if (hw_p->devnum == 2) {
1257 if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
1258 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1259 if ((hw_p->emac_ier & emac_isr) != 0) {
1260 emac_err (dev, emac_isr);
1265 if ((hw_p->emac_ier & emac_isr)
1266 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1267 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1268 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1269 mtdcr (uic2sr, UIC_ETH2);
1270 return (rc); /* we had errors so get out */
1274 if (hw_p->devnum == 3) {
1275 if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */
1276 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1277 if ((hw_p->emac_ier & emac_isr) != 0) {
1278 emac_err (dev, emac_isr);
1283 if ((hw_p->emac_ier & emac_isr)
1284 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
1285 mtdcr (UIC0SR, UIC_MRE | UIC_MTE); /* Clear */
1286 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1287 mtdcr (uic2sr, UIC_ETH3);
1288 return (rc); /* we had errors so get out */
1291 #endif /* CONFIG_440GX */
1292 #endif /* !CONFIG_440SP */
1294 /* handle MAX TX EOB interrupt from a tx */
1295 if (my_uic0msr & UIC_MTE) {
1296 mal_rx_eob = mfdcr (maltxeobisr);
1297 mtdcr (maltxeobisr, mal_rx_eob);
1298 mtdcr (UIC0SR, UIC_MTE);
1300 /* handle MAL RX EOB interupt from a receive */
1301 /* check for EOB on valid channels */
1302 if (my_uic0msr & UIC_MRE) {
1303 mal_rx_eob = mfdcr (malrxeobisr);
1304 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1306 mtdcr(malrxeobisr, mal_rx_eob); */
1307 enet_rcv (dev, emac_isr);
1308 /* indicate that we serviced an interrupt */
1314 mtdcr (UIC0SR, UIC_MRE); /* Clear */
1315 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
1316 switch (hw_p->devnum) {
1318 mtdcr (UICSR_ETHX, UIC_ETH0);
1321 mtdcr (UICSR_ETHX, UIC_ETH1);
1323 #if defined (CONFIG_440GX)
1325 mtdcr (uic2sr, UIC_ETH2);
1328 mtdcr (uic2sr, UIC_ETH3);
1330 #endif /* CONFIG_440GX */
1339 #else /* CONFIG_440 */
1341 int enetInt (struct eth_device *dev)
1344 int rc = -1; /* default to not us */
1345 unsigned long mal_isr;
1346 unsigned long emac_isr = 0;
1347 unsigned long mal_rx_eob;
1348 unsigned long my_uicmsr;
1350 EMAC_4XX_HW_PST hw_p;
1353 * Because the mal is generic, we need to get the current
1356 #if defined(CONFIG_NET_MULTI)
1357 dev = eth_get_dev();
1364 /* enter loop that stays in interrupt code until nothing to service */
1368 my_uicmsr = mfdcr (uicmsr);
1370 if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
1373 /* get and clear controller status interrupts */
1374 /* look at Mal and EMAC interrupts */
1375 if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
1376 mal_isr = mfdcr (malesr);
1377 /* look for mal error */
1378 if ((my_uicmsr & MAL_UIC_ERR) != 0) {
1379 mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
1385 /* port by port dispatch of emac interrupts */
1387 if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
1388 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
1389 if ((hw_p->emac_ier & emac_isr) != 0) {
1390 emac_err (dev, emac_isr);
1395 if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
1396 mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
1397 return (rc); /* we had errors so get out */
1400 /* handle MAX TX EOB interrupt from a tx */
1401 if (my_uicmsr & UIC_MAL_TXEOB) {
1402 mal_rx_eob = mfdcr (maltxeobisr);
1403 mtdcr (maltxeobisr, mal_rx_eob);
1404 mtdcr (uicsr, UIC_MAL_TXEOB);
1406 /* handle MAL RX EOB interupt from a receive */
1407 /* check for EOB on valid channels */
1408 if (my_uicmsr & UIC_MAL_RXEOB)
1410 mal_rx_eob = mfdcr (malrxeobisr);
1411 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
1413 mtdcr(malrxeobisr, mal_rx_eob); */
1414 enet_rcv (dev, emac_isr);
1415 /* indicate that we serviced an interrupt */
1420 mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
1421 #if defined(CONFIG_405EZ)
1422 mtsdr (sdricintstat, SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
1423 #endif /* defined(CONFIG_405EZ) */
1430 #endif /* CONFIG_440 */
1432 /*-----------------------------------------------------------------------------+
1434 *-----------------------------------------------------------------------------*/
1435 static void mal_err (struct eth_device *dev, unsigned long isr,
1436 unsigned long uic, unsigned long maldef,
1437 unsigned long mal_errr)
1439 EMAC_4XX_HW_PST hw_p = dev->priv;
1441 mtdcr (malesr, isr); /* clear interrupt */
1443 /* clear DE interrupt */
1444 mtdcr (maltxdeir, 0xC0000000);
1445 mtdcr (malrxdeir, 0x80000000);
1447 #ifdef INFO_4XX_ENET
1448 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
1451 eth_init (hw_p->bis); /* start again... */
1454 /*-----------------------------------------------------------------------------+
1455 * EMAC Error Routine
1456 *-----------------------------------------------------------------------------*/
1457 static void emac_err (struct eth_device *dev, unsigned long isr)
1459 EMAC_4XX_HW_PST hw_p = dev->priv;
1461 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
1462 out32 (EMAC_ISR + hw_p->hw_addr, isr);
1465 /*-----------------------------------------------------------------------------+
1466 * enet_rcv() handles the ethernet receive data
1467 *-----------------------------------------------------------------------------*/
1468 static void enet_rcv (struct eth_device *dev, unsigned long malisr)
1470 struct enet_frame *ef_ptr;
1471 unsigned long data_len;
1472 unsigned long rx_eob_isr;
1473 EMAC_4XX_HW_PST hw_p = dev->priv;
1479 rx_eob_isr = mfdcr (malrxeobisr);
1480 if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
1482 mtdcr (malrxeobisr, rx_eob_isr);
1485 while (1) { /* do all */
1488 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
1489 || (loop_count >= NUM_RX_BUFF))
1494 data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
1496 if (data_len > ENET_MAX_MTU) /* Check len */
1499 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
1501 hw_p->stats.rx_err_log[hw_p->
1504 hw_p->rx_err_index++;
1505 if (hw_p->rx_err_index ==
1507 hw_p->rx_err_index =
1510 } /* data_len < max mtu */
1512 if (!data_len) { /* no data */
1513 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
1515 hw_p->stats.data_len_err++; /* Error at Rx */
1520 /* Check if user has already eaten buffer */
1521 /* if not => ERROR */
1522 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
1523 if (hw_p->is_receiving)
1524 printf ("ERROR : Receive buffers are full!\n");
1527 hw_p->stats.rx_frames++;
1528 hw_p->stats.rx += data_len;
1529 ef_ptr = (struct enet_frame *) hw_p->rx[i].
1531 #ifdef INFO_4XX_ENET
1532 hw_p->stats.pkts_rx++;
1537 hw_p->rx_ready[hw_p->rx_i_index] = i;
1539 if (NUM_RX_BUFF == hw_p->rx_i_index)
1540 hw_p->rx_i_index = 0;
1543 if (NUM_RX_BUFF == hw_p->rx_slot)
1547 * free receive buffer only when
1548 * buffer has been handled (eth_rx)
1549 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1553 } /* if EMACK_RXCHL */
1557 static int ppc_4xx_eth_rx (struct eth_device *dev)
1562 EMAC_4XX_HW_PST hw_p = dev->priv;
1564 hw_p->is_receiving = 1; /* tell driver */
1568 * use ring buffer and
1569 * get index from rx buffer desciptor queue
1571 user_index = hw_p->rx_ready[hw_p->rx_u_index];
1572 if (user_index == -1) {
1574 break; /* nothing received - leave for() loop */
1578 mtmsr (msr & ~(MSR_EE));
1580 length = hw_p->rx[user_index].data_len;
1582 /* Pass the packet up to the protocol layers. */
1583 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1584 /* NetReceive(NetRxPackets[i], length); */
1585 NetReceive (NetRxPackets[user_index], length - 4);
1586 /* Free Recv Buffer */
1587 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
1588 /* Free rx buffer descriptor queue */
1589 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1591 if (NUM_RX_BUFF == hw_p->rx_u_index)
1592 hw_p->rx_u_index = 0;
1594 #ifdef INFO_4XX_ENET
1595 hw_p->stats.pkts_handled++;
1598 mtmsr (msr); /* Enable IRQ's */
1601 hw_p->is_receiving = 0; /* tell driver */
1606 int ppc_4xx_eth_initialize (bd_t * bis)
1608 static int virgin = 0;
1609 struct eth_device *dev;
1611 EMAC_4XX_HW_PST hw = NULL;
1612 u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
1615 #if defined(CONFIG_440GX)
1618 mfsdr (sdr_pfc1, pfc1);
1619 pfc1 &= ~(0x01e00000);
1621 mtsdr (sdr_pfc1, pfc1);
1624 /* first clear all mac-addresses */
1625 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
1626 memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
1628 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1630 default: /* fall through */
1632 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1633 bis->bi_enetaddr, 6);
1634 hw_addr[eth_num] = 0x0;
1636 #ifdef CONFIG_HAS_ETH1
1638 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1639 bis->bi_enet1addr, 6);
1640 hw_addr[eth_num] = 0x100;
1643 #ifdef CONFIG_HAS_ETH2
1645 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1646 bis->bi_enet2addr, 6);
1647 hw_addr[eth_num] = 0x400;
1650 #ifdef CONFIG_HAS_ETH3
1652 memcpy(ethaddr[eth_num + CONFIG_EMAC_NR_START],
1653 bis->bi_enet3addr, 6);
1654 hw_addr[eth_num] = 0x600;
1660 /* set phy num and mode */
1661 bis->bi_phynum[0] = CONFIG_PHY_ADDR;
1662 bis->bi_phymode[0] = 0;
1664 #if defined(CONFIG_PHY1_ADDR)
1665 bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
1666 bis->bi_phymode[1] = 0;
1668 #if defined(CONFIG_440GX)
1669 bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
1670 bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
1671 bis->bi_phymode[2] = 2;
1672 bis->bi_phymode[3] = 2;
1675 #if defined(CONFIG_440GX) || \
1676 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1677 defined(CONFIG_405EX)
1678 ppc_4xx_eth_setup_bridge(0, bis);
1681 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1683 * See if we can actually bring up the interface,
1684 * otherwise, skip it
1686 if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
1687 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1691 /* Allocate device structure */
1692 dev = (struct eth_device *) malloc (sizeof (*dev));
1694 printf ("ppc_4xx_eth_initialize: "
1695 "Cannot allocate eth_device %d\n", eth_num);
1698 memset(dev, 0, sizeof(*dev));
1700 /* Allocate our private use data */
1701 hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
1703 printf ("ppc_4xx_eth_initialize: "
1704 "Cannot allocate private hw data for eth_device %d",
1709 memset(hw, 0, sizeof(*hw));
1711 hw->hw_addr = hw_addr[eth_num];
1712 memcpy (dev->enetaddr, ethaddr[eth_num], 6);
1713 hw->devnum = eth_num;
1714 hw->print_speed = 1;
1716 sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
1717 dev->priv = (void *) hw;
1718 dev->init = ppc_4xx_eth_init;
1719 dev->halt = ppc_4xx_eth_halt;
1720 dev->send = ppc_4xx_eth_send;
1721 dev->recv = ppc_4xx_eth_rx;
1724 /* set the MAL IER ??? names may change with new spec ??? */
1725 #if defined(CONFIG_440SPE) || \
1726 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1727 defined(CONFIG_405EX)
1729 MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
1730 MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
1733 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
1734 MAL_IER_OPBE | MAL_IER_PLBE;
1736 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
1737 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
1738 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
1739 mtdcr (malier, mal_ier);
1741 /* install MAL interrupt handler */
1742 irq_install_handler (VECNUM_MS,
1743 (interrupt_handler_t *) enetInt,
1745 irq_install_handler (VECNUM_MTE,
1746 (interrupt_handler_t *) enetInt,
1748 irq_install_handler (VECNUM_MRE,
1749 (interrupt_handler_t *) enetInt,
1751 irq_install_handler (VECNUM_TXDE,
1752 (interrupt_handler_t *) enetInt,
1754 irq_install_handler (VECNUM_RXDE,
1755 (interrupt_handler_t *) enetInt,
1760 #if defined(CONFIG_NET_MULTI)
1766 #if defined(CONFIG_NET_MULTI)
1767 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
1768 miiphy_register (dev->name,
1769 emac4xx_miiphy_read, emac4xx_miiphy_write);
1772 } /* end for each supported device */
1776 #if !defined(CONFIG_NET_MULTI)
1777 void eth_halt (void) {
1779 ppc_4xx_eth_halt(emac0_dev);
1785 int eth_init (bd_t *bis)
1787 ppc_4xx_eth_initialize(bis);
1789 return ppc_4xx_eth_init(emac0_dev, bis);
1791 printf("ERROR: ethaddr not set!\n");
1796 int eth_send(volatile void *packet, int length)
1798 return (ppc_4xx_eth_send(emac0_dev, packet, length));
1803 return (ppc_4xx_eth_rx(emac0_dev));
1806 int emac4xx_miiphy_initialize (bd_t * bis)
1808 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
1809 miiphy_register ("ppc_4xx_eth0",
1810 emac4xx_miiphy_read, emac4xx_miiphy_write);
1815 #endif /* !defined(CONFIG_NET_MULTI) */