cpu/ppc4xx/44x_spd_ddr2.c

   1 /*
   2  * cpu/ppc4xx/44x_spd_ddr2.c
   3  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
   4  * DDR2 controller (non Denali Core). Those are 440SP/SPe.
   5  *
   6  * (C) Copyright 2007
   7  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   8  *
   9  * COPYRIGHT   AMCC   CORPORATION 2004
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  *
  29  */
  30
  31 /* define DEBUG for debugging output (obviously ;-)) */
  32 #if 0
  33 #define DEBUG
  34 #endif
  35
  36 #include <common.h>
  37 #include <command.h>
  38 #include <ppc4xx.h>
  39 #include <i2c.h>
  40 #include <asm/io.h>
  41 #include <asm/processor.h>
  42 #include <asm/mmu.h>
  43
  44 #if defined(CONFIG_SPD_EEPROM) &&                               \
  45         (defined(CONFIG_440SP) || defined(CONFIG_440SPE))
  46
  47 /*-----------------------------------------------------------------------------+
  48  * Defines
  49  *-----------------------------------------------------------------------------*/
  50 #ifndef TRUE
  51 #define TRUE            1
  52 #endif
  53 #ifndef FALSE
  54 #define FALSE           0
  55 #endif
  56
  57 #define SDRAM_DDR1      1
  58 #define SDRAM_DDR2      2
  59 #define SDRAM_NONE      0
  60
  61 #define MAXDIMMS        2
  62 #define MAXRANKS        4
  63 #define MAXBXCF         4
  64 #define MAX_SPD_BYTES   256   /* Max number of bytes on the DIMM's SPD EEPROM */
  65
  66 #define ONE_BILLION     1000000000
  67
  68 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
  69
  70 #define CMD_NOP         (7 << 19)
  71 #define CMD_PRECHARGE   (2 << 19)
  72 #define CMD_REFRESH     (1 << 19)
  73 #define CMD_EMR         (0 << 19)
  74 #define CMD_READ        (5 << 19)
  75 #define CMD_WRITE       (4 << 19)
  76
  77 #define SELECT_MR       (0 << 16)
  78 #define SELECT_EMR      (1 << 16)
  79 #define SELECT_EMR2     (2 << 16)
  80 #define SELECT_EMR3     (3 << 16)
  81
  82 /* MR */
  83 #define DLL_RESET       0x00000100
  84
  85 #define WRITE_RECOV_2   (1 << 9)
  86 #define WRITE_RECOV_3   (2 << 9)
  87 #define WRITE_RECOV_4   (3 << 9)
  88 #define WRITE_RECOV_5   (4 << 9)
  89 #define WRITE_RECOV_6   (5 << 9)
  90
  91 #define BURST_LEN_4     0x00000002
  92
  93 /* EMR */
  94 #define ODT_0_OHM       0x00000000
  95 #define ODT_50_OHM      0x00000044
  96 #define ODT_75_OHM      0x00000004
  97 #define ODT_150_OHM     0x00000040
  98
  99 #define ODS_FULL        0x00000000
 100 #define ODS_REDUCED     0x00000002
 101
 102 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
 103 #define ODT_EB0R        (0x80000000 >> 8)
 104 #define ODT_EB0W        (0x80000000 >> 7)
 105 #define CALC_ODT_R(n)   (ODT_EB0R << (n << 1))
 106 #define CALC_ODT_W(n)   (ODT_EB0W << (n << 1))
 107 #define CALC_ODT_RW(n)  (CALC_ODT_R(n) | CALC_ODT_W(n))
 108
 109 /* Defines for the Read Cycle Delay test */
 110 #define NUMMEMTESTS     8
 111 #define NUMMEMWORDS     8
 112 #define NUMLOOPS        64              /* memory test loops */
 113
 114 #undef CONFIG_ECC_ERROR_RESET           /* test-only: see description below, at check_ecc() */
 115
 116 /*
 117  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
 118  * region. Right now the cache should still be disabled in U-Boot because of the
 119  * EMAC driver, that need it's buffer descriptor to be located in non cached
 120  * memory.
 121  *
 122  * If at some time this restriction doesn't apply anymore, just define
 123  * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
 124  * everything correctly.
 125  */
 126 #ifdef CFG_ENABLE_SDRAM_CACHE
 127 #define MY_TLB_WORD2_I_ENABLE   0                       /* enable caching on SDRAM */
 128 #else
 129 #define MY_TLB_WORD2_I_ENABLE   TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
 130 #endif
 131
 132 /*
 133  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
 134  */
 135 void __spd_ddr_init_hang (void)
 136 {
 137         hang ();
 138 }
 139 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
 140
 141 /*
 142  * To provide an interface for board specific config values in this common
 143  * DDR setup code, we implement he "weak" default functions here. They return
 144  * the default value back to the caller.
 145  *
 146  * Please see include/configs/yucca.h for an example fora board specific
 147  * implementation.
 148  */
 149 u32 __ddr_wrdtr(u32 default_val)
 150 {
 151         return default_val;
 152 }
 153 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
 154
 155 u32 __ddr_clktr(u32 default_val)
 156 {
 157         return default_val;
 158 }
 159 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
 160
 161
 162 /* Private Structure Definitions */
 163
 164 /* enum only to ease code for cas latency setting */
 165 typedef enum ddr_cas_id {
 166         DDR_CAS_2      = 20,
 167         DDR_CAS_2_5    = 25,
 168         DDR_CAS_3      = 30,
 169         DDR_CAS_4      = 40,
 170         DDR_CAS_5      = 50
 171 } ddr_cas_id_t;
 172
 173 /*-----------------------------------------------------------------------------+
 174  * Prototypes
 175  *-----------------------------------------------------------------------------*/
 176 static unsigned long sdram_memsize(void);
 177 static void get_spd_info(unsigned long *dimm_populated,
 178                          unsigned char *iic0_dimm_addr,
 179                          unsigned long num_dimm_banks);
 180 static void check_mem_type(unsigned long *dimm_populated,
 181                            unsigned char *iic0_dimm_addr,
 182                            unsigned long num_dimm_banks);
 183 static void check_frequency(unsigned long *dimm_populated,
 184                             unsigned char *iic0_dimm_addr,
 185                             unsigned long num_dimm_banks);
 186 static void check_rank_number(unsigned long *dimm_populated,
 187                               unsigned char *iic0_dimm_addr,
 188                               unsigned long num_dimm_banks);
 189 static void check_voltage_type(unsigned long *dimm_populated,
 190                                unsigned char *iic0_dimm_addr,
 191                                unsigned long num_dimm_banks);
 192 static void program_memory_queue(unsigned long *dimm_populated,
 193                                  unsigned char *iic0_dimm_addr,
 194                                  unsigned long num_dimm_banks);
 195 static void program_codt(unsigned long *dimm_populated,
 196                          unsigned char *iic0_dimm_addr,
 197                          unsigned long num_dimm_banks);
 198 static void program_mode(unsigned long *dimm_populated,
 199                          unsigned char *iic0_dimm_addr,
 200                          unsigned long num_dimm_banks,
 201                          ddr_cas_id_t *selected_cas,
 202                          int *write_recovery);
 203 static void program_tr(unsigned long *dimm_populated,
 204                        unsigned char *iic0_dimm_addr,
 205                        unsigned long num_dimm_banks);
 206 static void program_rtr(unsigned long *dimm_populated,
 207                         unsigned char *iic0_dimm_addr,
 208                         unsigned long num_dimm_banks);
 209 static void program_bxcf(unsigned long *dimm_populated,
 210                          unsigned char *iic0_dimm_addr,
 211                          unsigned long num_dimm_banks);
 212 static void program_copt1(unsigned long *dimm_populated,
 213                           unsigned char *iic0_dimm_addr,
 214                           unsigned long num_dimm_banks);
 215 static void program_initplr(unsigned long *dimm_populated,
 216                             unsigned char *iic0_dimm_addr,
 217                             unsigned long num_dimm_banks,
 218                             ddr_cas_id_t selected_cas,
 219                             int write_recovery);
 220 static unsigned long is_ecc_enabled(void);
 221 #ifdef CONFIG_DDR_ECC
 222 static void program_ecc(unsigned long *dimm_populated,
 223                         unsigned char *iic0_dimm_addr,
 224                         unsigned long num_dimm_banks,
 225                         unsigned long tlb_word2_i_value);
 226 static void program_ecc_addr(unsigned long start_address,
 227                              unsigned long num_bytes,
 228                              unsigned long tlb_word2_i_value);
 229 #endif
 230 static void program_DQS_calibration(unsigned long *dimm_populated,
 231                                     unsigned char *iic0_dimm_addr,
 232                                     unsigned long num_dimm_banks);
 233 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
 234 static void     test(void);
 235 #else
 236 static void     DQS_calibration_process(void);
 237 #endif
 238 static void ppc440sp_sdram_register_dump(void);
 239 int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
 240 void dcbz_area(u32 start_address, u32 num_bytes);
 241 void dflush(void);
 242
 243 static u32 mfdcr_any(u32 dcr)
 244 {
 245         u32 val;
 246
 247         switch (dcr) {
 248         case SDRAM_R0BAS + 0:
 249                 val = mfdcr(SDRAM_R0BAS + 0);
 250                 break;
 251         case SDRAM_R0BAS + 1:
 252                 val = mfdcr(SDRAM_R0BAS + 1);
 253                 break;
 254         case SDRAM_R0BAS + 2:
 255                 val = mfdcr(SDRAM_R0BAS + 2);
 256                 break;
 257         case SDRAM_R0BAS + 3:
 258                 val = mfdcr(SDRAM_R0BAS + 3);
 259                 break;
 260         default:
 261                 printf("DCR %d not defined in case statement!!!\n", dcr);
 262                 val = 0; /* just to satisfy the compiler */
 263         }
 264
 265         return val;
 266 }
 267
 268 static void mtdcr_any(u32 dcr, u32 val)
 269 {
 270         switch (dcr) {
 271         case SDRAM_R0BAS + 0:
 272                 mtdcr(SDRAM_R0BAS + 0, val);
 273                 break;
 274         case SDRAM_R0BAS + 1:
 275                 mtdcr(SDRAM_R0BAS + 1, val);
 276                 break;
 277         case SDRAM_R0BAS + 2:
 278                 mtdcr(SDRAM_R0BAS + 2, val);
 279                 break;
 280         case SDRAM_R0BAS + 3:
 281                 mtdcr(SDRAM_R0BAS + 3, val);
 282                 break;
 283         default:
 284                 printf("DCR %d not defined in case statement!!!\n", dcr);
 285         }
 286 }
 287
 288 static unsigned char spd_read(uchar chip, uint addr)
 289 {
 290         unsigned char data[2];
 291
 292         if (i2c_probe(chip) == 0)
 293                 if (i2c_read(chip, addr, 1, data, 1) == 0)
 294                         return data[0];
 295
 296         return 0;
 297 }
 298
 299 /*-----------------------------------------------------------------------------+
 300  * sdram_memsize
 301  *-----------------------------------------------------------------------------*/
 302 static unsigned long sdram_memsize(void)
 303 {
 304         unsigned long mem_size;
 305         unsigned long mcopt2;
 306         unsigned long mcstat;
 307         unsigned long mb0cf;
 308         unsigned long sdsz;
 309         unsigned long i;
 310
 311         mem_size = 0;
 312
 313         mfsdram(SDRAM_MCOPT2, mcopt2);
 314         mfsdram(SDRAM_MCSTAT, mcstat);
 315
 316         /* DDR controller must be enabled and not in self-refresh. */
 317         /* Otherwise memsize is zero. */
 318         if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
 319             && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
 320             && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
 321                 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
 322                 for (i = 0; i < MAXBXCF; i++) {
 323                         mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
 324                         /* Banks enabled */
 325                         if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
 326                                 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
 327
 328                                 switch(sdsz) {
 329                                 case SDRAM_RXBAS_SDSZ_8:
 330                                         mem_size+=8;
 331                                         break;
 332                                 case SDRAM_RXBAS_SDSZ_16:
 333                                         mem_size+=16;
 334                                         break;
 335                                 case SDRAM_RXBAS_SDSZ_32:
 336                                         mem_size+=32;
 337                                         break;
 338                                 case SDRAM_RXBAS_SDSZ_64:
 339                                         mem_size+=64;
 340                                         break;
 341                                 case SDRAM_RXBAS_SDSZ_128:
 342                                         mem_size+=128;
 343                                         break;
 344                                 case SDRAM_RXBAS_SDSZ_256:
 345                                         mem_size+=256;
 346                                         break;
 347                                 case SDRAM_RXBAS_SDSZ_512:
 348                                         mem_size+=512;
 349                                         break;
 350                                 case SDRAM_RXBAS_SDSZ_1024:
 351                                         mem_size+=1024;
 352                                         break;
 353                                 case SDRAM_RXBAS_SDSZ_2048:
 354                                         mem_size+=2048;
 355                                         break;
 356                                 case SDRAM_RXBAS_SDSZ_4096:
 357                                         mem_size+=4096;
 358                                         break;
 359                                 default:
 360                                         mem_size=0;
 361                                         break;
 362                                 }
 363                         }
 364                 }
 365         }
 366
 367         mem_size *= 1024 * 1024;
 368         return(mem_size);
 369 }
 370
 371 /*-----------------------------------------------------------------------------+
 372  * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
 373  * Note: This routine runs from flash with a stack set up in the chip's
 374  * sram space.  It is important that the routine does not require .sbss, .bss or
 375  * .data sections.  It also cannot call routines that require these sections.
 376  *-----------------------------------------------------------------------------*/
 377 /*-----------------------------------------------------------------------------
 378  * Function:     initdram
 379  * Description:  Configures SDRAM memory banks for DDR operation.
 380  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
 381  *               via the IIC bus and then configures the DDR SDRAM memory
 382  *               banks appropriately. If Auto Memory Configuration is
 383  *               not used, it is assumed that no DIMM is plugged
 384  *-----------------------------------------------------------------------------*/
 385 long int initdram(int board_type)
 386 {
 387         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 388         unsigned char spd0[MAX_SPD_BYTES];
 389         unsigned char spd1[MAX_SPD_BYTES];
 390         unsigned char *dimm_spd[MAXDIMMS];
 391         unsigned long dimm_populated[MAXDIMMS];
 392         unsigned long num_dimm_banks;               /* on board dimm banks */
 393         unsigned long val;
 394         ddr_cas_id_t  selected_cas;
 395         int write_recovery;
 396         unsigned long dram_size = 0;
 397
 398         num_dimm_banks = sizeof(iic0_dimm_addr);
 399
 400         /*------------------------------------------------------------------
 401          * Set up an array of SPD matrixes.
 402          *-----------------------------------------------------------------*/
 403         dimm_spd[0] = spd0;
 404         dimm_spd[1] = spd1;
 405
 406         /*------------------------------------------------------------------
 407          * Reset the DDR-SDRAM controller.
 408          *-----------------------------------------------------------------*/
 409         mtsdr(SDR0_SRST, (0x80000000 >> 10));
 410         mtsdr(SDR0_SRST, 0x00000000);
 411
 412         /*
 413          * Make sure I2C controller is initialized
 414          * before continuing.
 415          */
 416
 417         /* switch to correct I2C bus */
 418         I2C_SET_BUS(CFG_SPD_BUS_NUM);
 419         i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
 420
 421         /*------------------------------------------------------------------
 422          * Clear out the serial presence detect buffers.
 423          * Perform IIC reads from the dimm.  Fill in the spds.
 424          * Check to see if the dimm slots are populated
 425          *-----------------------------------------------------------------*/
 426         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 427
 428         /*------------------------------------------------------------------
 429          * Check the memory type for the dimms plugged.
 430          *-----------------------------------------------------------------*/
 431         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 432
 433         /*------------------------------------------------------------------
 434          * Check the frequency supported for the dimms plugged.
 435          *-----------------------------------------------------------------*/
 436         check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 437
 438         /*------------------------------------------------------------------
 439          * Check the total rank number.
 440          *-----------------------------------------------------------------*/
 441         check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 442
 443         /*------------------------------------------------------------------
 444          * Check the voltage type for the dimms plugged.
 445          *-----------------------------------------------------------------*/
 446         check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 447
 448         /*------------------------------------------------------------------
 449          * Program SDRAM controller options 2 register
 450          * Except Enabling of the memory controller.
 451          *-----------------------------------------------------------------*/
 452         mfsdram(SDRAM_MCOPT2, val);
 453         mtsdram(SDRAM_MCOPT2,
 454                 (val &
 455                  ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
 456                    SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
 457                    SDRAM_MCOPT2_ISIE_MASK))
 458                 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
 459                    SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
 460                    SDRAM_MCOPT2_ISIE_ENABLE));
 461
 462         /*------------------------------------------------------------------
 463          * Program SDRAM controller options 1 register
 464          * Note: Does not enable the memory controller.
 465          *-----------------------------------------------------------------*/
 466         program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 467
 468         /*------------------------------------------------------------------
 469          * Set the SDRAM Controller On Die Termination Register
 470          *-----------------------------------------------------------------*/
 471         program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 472
 473         /*------------------------------------------------------------------
 474          * Program SDRAM refresh register.
 475          *-----------------------------------------------------------------*/
 476         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 477
 478         /*------------------------------------------------------------------
 479          * Program SDRAM mode register.
 480          *-----------------------------------------------------------------*/
 481         program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 482                      &selected_cas, &write_recovery);
 483
 484         /*------------------------------------------------------------------
 485          * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
 486          *-----------------------------------------------------------------*/
 487         mfsdram(SDRAM_WRDTR, val);
 488         mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
 489                 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
 490
 491         /*------------------------------------------------------------------
 492          * Set the SDRAM Clock Timing Register
 493          *-----------------------------------------------------------------*/
 494         mfsdram(SDRAM_CLKTR, val);
 495         mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
 496                 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
 497
 498         /*------------------------------------------------------------------
 499          * Program the BxCF registers.
 500          *-----------------------------------------------------------------*/
 501         program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 502
 503         /*------------------------------------------------------------------
 504          * Program SDRAM timing registers.
 505          *-----------------------------------------------------------------*/
 506         program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 507
 508         /*------------------------------------------------------------------
 509          * Set the Extended Mode register
 510          *-----------------------------------------------------------------*/
 511         mfsdram(SDRAM_MEMODE, val);
 512         mtsdram(SDRAM_MEMODE,
 513                 (val & ~(SDRAM_MEMODE_DIC_MASK  | SDRAM_MEMODE_DLL_MASK |
 514                          SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
 515                 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
 516                  | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
 517
 518         /*------------------------------------------------------------------
 519          * Program Initialization preload registers.
 520          *-----------------------------------------------------------------*/
 521         program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 522                         selected_cas, write_recovery);
 523
 524         /*------------------------------------------------------------------
 525          * Delay to ensure 200usec have elapsed since reset.
 526          *-----------------------------------------------------------------*/
 527         udelay(400);
 528
 529         /*------------------------------------------------------------------
 530          * Set the memory queue core base addr.
 531          *-----------------------------------------------------------------*/
 532         program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 533
 534         /*------------------------------------------------------------------
 535          * Program SDRAM controller options 2 register
 536          * Enable the memory controller.
 537          *-----------------------------------------------------------------*/
 538         mfsdram(SDRAM_MCOPT2, val);
 539         mtsdram(SDRAM_MCOPT2,
 540                 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
 541                          SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
 542                 (SDRAM_MCOPT2_DCEN_ENABLE | SDRAM_MCOPT2_IPTR_EXECUTE));
 543
 544         /*------------------------------------------------------------------
 545          * Wait for SDRAM_CFG0_DC_EN to complete.
 546          *-----------------------------------------------------------------*/
 547         do {
 548                 mfsdram(SDRAM_MCSTAT, val);
 549         } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
 550
 551         /* get installed memory size */
 552         dram_size = sdram_memsize();
 553
 554         /* and program tlb entries for this size (dynamic) */
 555
 556         /*
 557          * Program TLB entries with caches enabled, for best performace
 558          * while auto-calibrating and ECC generation
 559          */
 560         program_tlb(0, 0, dram_size, 0);
 561
 562         /*------------------------------------------------------------------
 563          * DQS calibration.
 564          *-----------------------------------------------------------------*/
 565         program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 566
 567 #ifdef CONFIG_DDR_ECC
 568         /*------------------------------------------------------------------
 569          * If ecc is enabled, initialize the parity bits.
 570          *-----------------------------------------------------------------*/
 571         program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
 572 #endif
 573
 574         /*
 575          * Now after initialization (auto-calibration and ECC generation)
 576          * remove the TLB entries with caches enabled and program again with
 577          * desired cache functionality
 578          */
 579         remove_tlb(0, dram_size);
 580         program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
 581
 582         ppc440sp_sdram_register_dump();
 583
 584         return dram_size;
 585 }
 586
 587 static void get_spd_info(unsigned long *dimm_populated,
 588                          unsigned char *iic0_dimm_addr,
 589                          unsigned long num_dimm_banks)
 590 {
 591         unsigned long dimm_num;
 592         unsigned long dimm_found;
 593         unsigned char num_of_bytes;
 594         unsigned char total_size;
 595
 596         dimm_found = FALSE;
 597         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 598                 num_of_bytes = 0;
 599                 total_size = 0;
 600
 601                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 602                 debug("\nspd_read(0x%x) returned %d\n",
 603                       iic0_dimm_addr[dimm_num], num_of_bytes);
 604                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 605                 debug("spd_read(0x%x) returned %d\n",
 606                       iic0_dimm_addr[dimm_num], total_size);
 607
 608                 if ((num_of_bytes != 0) && (total_size != 0)) {
 609                         dimm_populated[dimm_num] = TRUE;
 610                         dimm_found = TRUE;
 611                         debug("DIMM slot %lu: populated\n", dimm_num);
 612                 } else {
 613                         dimm_populated[dimm_num] = FALSE;
 614                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 615                 }
 616         }
 617
 618         if (dimm_found == FALSE) {
 619                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 620                 spd_ddr_init_hang ();
 621         }
 622 }
 623
 624 #ifdef CONFIG_ADD_RAM_INFO
 625 void board_add_ram_info(int use_default)
 626 {
 627         PPC440_SYS_INFO board_cfg;
 628         u32 val;
 629
 630         if (is_ecc_enabled())
 631                 puts(" (ECC");
 632         else
 633                 puts(" (ECC not");
 634
 635         get_sys_info(&board_cfg);
 636
 637         mfsdr(SDR0_DDR0, val);
 638         val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
 639         printf(" enabled, %d MHz", (val * 2) / 1000000);
 640
 641         mfsdram(SDRAM_MMODE, val);
 642         val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
 643         printf(", CL%d)", val);
 644 }
 645 #endif
 646
 647 /*------------------------------------------------------------------
 648  * For the memory DIMMs installed, this routine verifies that they
 649  * really are DDR specific DIMMs.
 650  *-----------------------------------------------------------------*/
 651 static void check_mem_type(unsigned long *dimm_populated,
 652                            unsigned char *iic0_dimm_addr,
 653                            unsigned long num_dimm_banks)
 654 {
 655         unsigned long dimm_num;
 656         unsigned long dimm_type;
 657
 658         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 659                 if (dimm_populated[dimm_num] == TRUE) {
 660                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 661                         switch (dimm_type) {
 662                         case 1:
 663                                 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
 664                                        "slot %d.\n", (unsigned int)dimm_num);
 665                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 666                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 667                                 spd_ddr_init_hang ();
 668                                 break;
 669                         case 2:
 670                                 printf("ERROR: EDO DIMM detected in slot %d.\n",
 671                                        (unsigned int)dimm_num);
 672                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 673                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 674                                 spd_ddr_init_hang ();
 675                                 break;
 676                         case 3:
 677                                 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
 678                                        (unsigned int)dimm_num);
 679                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 680                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 681                                 spd_ddr_init_hang ();
 682                                 break;
 683                         case 4:
 684                                 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
 685                                        (unsigned int)dimm_num);
 686                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 687                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 688                                 spd_ddr_init_hang ();
 689                                 break;
 690                         case 5:
 691                                 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
 692                                        (unsigned int)dimm_num);
 693                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 694                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 695                                 spd_ddr_init_hang ();
 696                                 break;
 697                         case 6:
 698                                 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
 699                                        (unsigned int)dimm_num);
 700                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 701                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 702                                 spd_ddr_init_hang ();
 703                                 break;
 704                         case 7:
 705                                 debug("DIMM slot %d: DDR1 SDRAM detected\n", dimm_num);
 706                                 dimm_populated[dimm_num] = SDRAM_DDR1;
 707                                 break;
 708                         case 8:
 709                                 debug("DIMM slot %d: DDR2 SDRAM detected\n", dimm_num);
 710                                 dimm_populated[dimm_num] = SDRAM_DDR2;
 711                                 break;
 712                         default:
 713                                 printf("ERROR: Unknown DIMM detected in slot %d.\n",
 714                                        (unsigned int)dimm_num);
 715                                 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
 716                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 717                                 spd_ddr_init_hang ();
 718                                 break;
 719                         }
 720                 }
 721         }
 722         for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
 723                 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
 724                     && (dimm_populated[dimm_num]   != SDRAM_NONE)
 725                     && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
 726                         printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
 727                         spd_ddr_init_hang ();
 728                 }
 729         }
 730 }
 731
 732 /*------------------------------------------------------------------
 733  * For the memory DIMMs installed, this routine verifies that
 734  * frequency previously calculated is supported.
 735  *-----------------------------------------------------------------*/
 736 static void check_frequency(unsigned long *dimm_populated,
 737                             unsigned char *iic0_dimm_addr,
 738                             unsigned long num_dimm_banks)
 739 {
 740         unsigned long dimm_num;
 741         unsigned long tcyc_reg;
 742         unsigned long cycle_time;
 743         unsigned long calc_cycle_time;
 744         unsigned long sdram_freq;
 745         unsigned long sdr_ddrpll;
 746         PPC440_SYS_INFO board_cfg;
 747
 748         /*------------------------------------------------------------------
 749          * Get the board configuration info.
 750          *-----------------------------------------------------------------*/
 751         get_sys_info(&board_cfg);
 752
 753         mfsdr(SDR0_DDR0, sdr_ddrpll);
 754         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
 755
 756         /*
 757          * calc_cycle_time is calculated from DDR frequency set by board/chip
 758          * and is expressed in multiple of 10 picoseconds
 759          * to match the way DIMM cycle time is calculated below.
 760          */
 761         calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
 762
 763         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 764                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 765                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 766                         /*
 767                          * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
 768                          * the higher order nibble (bits 4-7) designates the cycle time
 769                          * to a granularity of 1ns;
 770                          * the value presented by the lower order nibble (bits 0-3)
 771                          * has a granularity of .1ns and is added to the value designated
 772                          * by the higher nibble. In addition, four lines of the lower order
 773                          * nibble are assigned to support +.25,+.33, +.66 and +.75.
 774                          */
 775                          /* Convert from hex to decimal */
 776                         if ((tcyc_reg & 0x0F) == 0x0D)
 777                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
 778                         else if ((tcyc_reg & 0x0F) == 0x0C)
 779                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
 780                         else if ((tcyc_reg & 0x0F) == 0x0B)
 781                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
 782                         else if ((tcyc_reg & 0x0F) == 0x0A)
 783                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
 784                         else
 785                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
 786                                         ((tcyc_reg & 0x0F)*10);
 787                         debug("cycle_time=%d [10 picoseconds]\n", cycle_time);
 788
 789                         if  (cycle_time > (calc_cycle_time + 10)) {
 790                                 /*
 791                                  * the provided sdram cycle_time is too small
 792                                  * for the available DIMM cycle_time.
 793                                  * The additionnal 100ps is here to accept a small incertainty.
 794                                  */
 795                                 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
 796                                        "slot %d \n while calculated cycle time is %d ps.\n",
 797                                        (unsigned int)(cycle_time*10),
 798                                        (unsigned int)dimm_num,
 799                                        (unsigned int)(calc_cycle_time*10));
 800                                 printf("Replace the DIMM, or change DDR frequency via "
 801                                        "strapping bits.\n\n");
 802                                 spd_ddr_init_hang ();
 803                         }
 804                 }
 805         }
 806 }
 807
 808 /*------------------------------------------------------------------
 809  * For the memory DIMMs installed, this routine verifies two
 810  * ranks/banks maximum are availables.
 811  *-----------------------------------------------------------------*/
 812 static void check_rank_number(unsigned long *dimm_populated,
 813                               unsigned char *iic0_dimm_addr,
 814                               unsigned long num_dimm_banks)
 815 {
 816         unsigned long dimm_num;
 817         unsigned long dimm_rank;
 818         unsigned long total_rank = 0;
 819
 820         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 821                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 822                         dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
 823                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
 824                                 dimm_rank = (dimm_rank & 0x0F) +1;
 825                         else
 826                                 dimm_rank = dimm_rank & 0x0F;
 827
 828
 829                         if (dimm_rank > MAXRANKS) {
 830                                 printf("ERROR: DRAM DIMM detected with %d ranks in "
 831                                        "slot %d is not supported.\n", dimm_rank, dimm_num);
 832                                 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 833                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 834                                 spd_ddr_init_hang ();
 835                         } else
 836                                 total_rank += dimm_rank;
 837                 }
 838                 if (total_rank > MAXRANKS) {
 839                         printf("ERROR: DRAM DIMM detected with a total of %d ranks "
 840                                "for all slots.\n", (unsigned int)total_rank);
 841                         printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 842                         printf("Remove one of the DIMM modules.\n\n");
 843                         spd_ddr_init_hang ();
 844                 }
 845         }
 846 }
 847
 848 /*------------------------------------------------------------------
 849  * only support 2.5V modules.
 850  * This routine verifies this.
 851  *-----------------------------------------------------------------*/
 852 static void check_voltage_type(unsigned long *dimm_populated,
 853                                unsigned char *iic0_dimm_addr,
 854                                unsigned long num_dimm_banks)
 855 {
 856         unsigned long dimm_num;
 857         unsigned long voltage_type;
 858
 859         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 860                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 861                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 862                         switch (voltage_type) {
 863                         case 0x00:
 864                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 865                                 printf("This DIMM is 5.0 Volt/TTL.\n");
 866                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 867                                        (unsigned int)dimm_num);
 868                                 spd_ddr_init_hang ();
 869                                 break;
 870                         case 0x01:
 871                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 872                                 printf("This DIMM is LVTTL.\n");
 873                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 874                                        (unsigned int)dimm_num);
 875                                 spd_ddr_init_hang ();
 876                                 break;
 877                         case 0x02:
 878                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 879                                 printf("This DIMM is 1.5 Volt.\n");
 880                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 881                                        (unsigned int)dimm_num);
 882                                 spd_ddr_init_hang ();
 883                                 break;
 884                         case 0x03:
 885                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 886                                 printf("This DIMM is 3.3 Volt/TTL.\n");
 887                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 888                                        (unsigned int)dimm_num);
 889                                 spd_ddr_init_hang ();
 890                                 break;
 891                         case 0x04:
 892                                 /* 2.5 Voltage only for DDR1 */
 893                                 break;
 894                         case 0x05:
 895                                 /* 1.8 Voltage only for DDR2 */
 896                                 break;
 897                         default:
 898                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 899                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 900                                        (unsigned int)dimm_num);
 901                                 spd_ddr_init_hang ();
 902                                 break;
 903                         }
 904                 }
 905         }
 906 }
 907
 908 /*-----------------------------------------------------------------------------+
 909  * program_copt1.
 910  *-----------------------------------------------------------------------------*/
 911 static void program_copt1(unsigned long *dimm_populated,
 912                           unsigned char *iic0_dimm_addr,
 913                           unsigned long num_dimm_banks)
 914 {
 915         unsigned long dimm_num;
 916         unsigned long mcopt1;
 917         unsigned long ecc_enabled;
 918         unsigned long ecc = 0;
 919         unsigned long data_width = 0;
 920         unsigned long dimm_32bit;
 921         unsigned long dimm_64bit;
 922         unsigned long registered = 0;
 923         unsigned long attribute = 0;
 924         unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 925         unsigned long bankcount;
 926         unsigned long ddrtype;
 927         unsigned long val;
 928
 929 #ifdef CONFIG_DDR_ECC
 930         ecc_enabled = TRUE;
 931 #else
 932         ecc_enabled = FALSE;
 933 #endif
 934         dimm_32bit = FALSE;
 935         dimm_64bit = FALSE;
 936         buf0 = FALSE;
 937         buf1 = FALSE;
 938
 939         /*------------------------------------------------------------------
 940          * Set memory controller options reg 1, SDRAM_MCOPT1.
 941          *-----------------------------------------------------------------*/
 942         mfsdram(SDRAM_MCOPT1, val);
 943         mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
 944                          SDRAM_MCOPT1_PMU_MASK  | SDRAM_MCOPT1_DMWD_MASK |
 945                          SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
 946                          SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
 947                          SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
 948                          SDRAM_MCOPT1_DREF_MASK);
 949
 950         mcopt1 |= SDRAM_MCOPT1_QDEP;
 951         mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
 952         mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
 953         mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
 954         mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
 955         mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
 956
 957         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 958                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 959                         /* test ecc support */
 960                         ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
 961                         if (ecc != 0x02) /* ecc not supported */
 962                                 ecc_enabled = FALSE;
 963
 964                         /* test bank count */
 965                         bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
 966                         if (bankcount == 0x04) /* bank count = 4 */
 967                                 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
 968                         else /* bank count = 8 */
 969                                 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
 970
 971                         /* test DDR type */
 972                         ddrtype = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2);
 973                         /* test for buffered/unbuffered, registered, differential clocks */
 974                         registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
 975                         attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
 976
 977                         /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 978                         if (dimm_num == 0) {
 979                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
 980                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
 981                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
 982                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
 983                                 if (registered == 1) { /* DDR2 always buffered */
 984                                         /* TODO: what about above  comments ? */
 985                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
 986                                         buf0 = TRUE;
 987                                 } else {
 988                                         /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
 989                                         if ((attribute & 0x02) == 0x00) {
 990                                                 /* buffered not supported */
 991                                                 buf0 = FALSE;
 992                                         } else {
 993                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
 994                                                 buf0 = TRUE;
 995                                         }
 996                                 }
 997                         }
 998                         else if (dimm_num == 1) {
 999                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1000                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1001                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1002                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1003                                 if (registered == 1) {
1004                                         /* DDR2 always buffered */
1005                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1006                                         buf1 = TRUE;
1007                                 } else {
1008                                         if ((attribute & 0x02) == 0x00) {
1009                                                 /* buffered not supported */
1010                                                 buf1 = FALSE;
1011                                         } else {
1012                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1013                                                 buf1 = TRUE;
1014                                         }
1015                                 }
1016                         }
1017
1018                         /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1019                         data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1020                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1021
1022                         switch (data_width) {
1023                         case 72:
1024                         case 64:
1025                                 dimm_64bit = TRUE;
1026                                 break;
1027                         case 40:
1028                         case 32:
1029                                 dimm_32bit = TRUE;
1030                                 break;
1031                         default:
1032                                 printf("WARNING: Detected a DIMM with a data width of %d bits.\n",
1033                                        data_width);
1034                                 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1035                                 break;
1036                         }
1037                 }
1038         }
1039
1040         /* verify matching properties */
1041         if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1042                 if (buf0 != buf1) {
1043                         printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1044                         spd_ddr_init_hang ();
1045                 }
1046         }
1047
1048         if ((dimm_64bit == TRUE) && (dimm_32bit == TRUE)) {
1049                 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1050                 spd_ddr_init_hang ();
1051         }
1052         else if ((dimm_64bit == TRUE) && (dimm_32bit == FALSE)) {
1053                 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1054         } else if ((dimm_64bit == FALSE) && (dimm_32bit == TRUE)) {
1055                 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1056         } else {
1057                 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1058                 spd_ddr_init_hang ();
1059         }
1060
1061         if (ecc_enabled == TRUE)
1062                 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1063         else
1064                 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1065
1066         mtsdram(SDRAM_MCOPT1, mcopt1);
1067 }
1068
1069 /*-----------------------------------------------------------------------------+
1070  * program_codt.
1071  *-----------------------------------------------------------------------------*/
1072 static void program_codt(unsigned long *dimm_populated,
1073                          unsigned char *iic0_dimm_addr,
1074                          unsigned long num_dimm_banks)
1075 {
1076         unsigned long codt;
1077         unsigned long modt0 = 0;
1078         unsigned long modt1 = 0;
1079         unsigned long modt2 = 0;
1080         unsigned long modt3 = 0;
1081         unsigned char dimm_num;
1082         unsigned char dimm_rank;
1083         unsigned char total_rank = 0;
1084         unsigned char total_dimm = 0;
1085         unsigned char dimm_type = 0;
1086         unsigned char firstSlot = 0;
1087
1088         /*------------------------------------------------------------------
1089          * Set the SDRAM Controller On Die Termination Register
1090          *-----------------------------------------------------------------*/
1091         mfsdram(SDRAM_CODT, codt);
1092         codt |= (SDRAM_CODT_IO_NMODE
1093                  & (~SDRAM_CODT_DQS_SINGLE_END
1094                     & ~SDRAM_CODT_CKSE_SINGLE_END
1095                     & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END
1096                     & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END));
1097
1098         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1099                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1100                         dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1101                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1102                                 dimm_rank = (dimm_rank & 0x0F) + 1;
1103                                 dimm_type = SDRAM_DDR2;
1104                         } else {
1105                                 dimm_rank = dimm_rank & 0x0F;
1106                                 dimm_type = SDRAM_DDR1;
1107                         }
1108
1109                         total_rank += dimm_rank;
1110                         total_dimm++;
1111                         if ((dimm_num == 0) && (total_dimm == 1))
1112                                 firstSlot = TRUE;
1113                         else
1114                                 firstSlot = FALSE;
1115                 }
1116         }
1117         if (dimm_type == SDRAM_DDR2) {
1118                 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1119                 if ((total_dimm == 1) && (firstSlot == TRUE)) {
1120                         if (total_rank == 1) {
1121                                 codt |= CALC_ODT_R(0);
1122                                 modt0 = CALC_ODT_W(0);
1123                                 modt1 = 0x00000000;
1124                                 modt2 = 0x00000000;
1125                                 modt3 = 0x00000000;
1126                         }
1127                         if (total_rank == 2) {
1128                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1129                                 modt0 = CALC_ODT_W(0);
1130                                 modt1 = CALC_ODT_W(0);
1131                                 modt2 = 0x00000000;
1132                                 modt3 = 0x00000000;
1133                         }
1134                 } else if ((total_dimm == 1) && (firstSlot != TRUE)) {
1135                         if (total_rank == 1) {
1136                                 codt |= CALC_ODT_R(2);
1137                                 modt0 = 0x00000000;
1138                                 modt1 = 0x00000000;
1139                                 modt2 = CALC_ODT_W(2);
1140                                 modt3 = 0x00000000;
1141                         }
1142                         if (total_rank == 2) {
1143                                 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1144                                 modt0 = 0x00000000;
1145                                 modt1 = 0x00000000;
1146                                 modt2 = CALC_ODT_W(2);
1147                                 modt3 = CALC_ODT_W(2);
1148                         }
1149                 }
1150                 if (total_dimm == 2) {
1151                         if (total_rank == 2) {
1152                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1153                                 modt0 = CALC_ODT_RW(2);
1154                                 modt1 = 0x00000000;
1155                                 modt2 = CALC_ODT_RW(0);
1156                                 modt3 = 0x00000000;
1157                         }
1158                         if (total_rank == 4) {
1159                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1160                                         CALC_ODT_R(2) | CALC_ODT_R(3);
1161                                 modt0 = CALC_ODT_RW(2);
1162                                 modt1 = 0x00000000;
1163                                 modt2 = CALC_ODT_RW(0);
1164                                 modt3 = 0x00000000;
1165                         }
1166                 }
1167         } else {
1168                 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1169                 modt0 = 0x00000000;
1170                 modt1 = 0x00000000;
1171                 modt2 = 0x00000000;
1172                 modt3 = 0x00000000;
1173
1174                 if (total_dimm == 1) {
1175                         if (total_rank == 1)
1176                                 codt |= 0x00800000;
1177                         if (total_rank == 2)
1178                                 codt |= 0x02800000;
1179                 }
1180                 if (total_dimm == 2) {
1181                         if (total_rank == 2)
1182                                 codt |= 0x08800000;
1183                         if (total_rank == 4)
1184                                 codt |= 0x2a800000;
1185                 }
1186         }
1187
1188         debug("nb of dimm %d\n", total_dimm);
1189         debug("nb of rank %d\n", total_rank);
1190         if (total_dimm == 1)
1191                 debug("dimm in slot %d\n", firstSlot);
1192
1193         mtsdram(SDRAM_CODT, codt);
1194         mtsdram(SDRAM_MODT0, modt0);
1195         mtsdram(SDRAM_MODT1, modt1);
1196         mtsdram(SDRAM_MODT2, modt2);
1197         mtsdram(SDRAM_MODT3, modt3);
1198 }
1199
1200 /*-----------------------------------------------------------------------------+
1201  * program_initplr.
1202  *-----------------------------------------------------------------------------*/
1203 static void program_initplr(unsigned long *dimm_populated,
1204                             unsigned char *iic0_dimm_addr,
1205                             unsigned long num_dimm_banks,
1206                             ddr_cas_id_t selected_cas,
1207                             int write_recovery)
1208 {
1209         u32 cas = 0;
1210         u32 odt = 0;
1211         u32 ods = 0;
1212         u32 mr;
1213         u32 wr;
1214         u32 emr;
1215         u32 emr2;
1216         u32 emr3;
1217         int dimm_num;
1218         int total_dimm = 0;
1219
1220         /******************************************************
1221          ** Assumption: if more than one DIMM, all DIMMs are the same
1222          **             as already checked in check_memory_type
1223          ******************************************************/
1224
1225         if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1226                 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1227                 mtsdram(SDRAM_INITPLR1, 0x81900400);
1228                 mtsdram(SDRAM_INITPLR2, 0x81810000);
1229                 mtsdram(SDRAM_INITPLR3, 0xff800162);
1230                 mtsdram(SDRAM_INITPLR4, 0x81900400);
1231                 mtsdram(SDRAM_INITPLR5, 0x86080000);
1232                 mtsdram(SDRAM_INITPLR6, 0x86080000);
1233                 mtsdram(SDRAM_INITPLR7, 0x81000062);
1234         } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1235                 switch (selected_cas) {
1236                 case DDR_CAS_3:
1237                         cas = 3 << 4;
1238                         break;
1239                 case DDR_CAS_4:
1240                         cas = 4 << 4;
1241                         break;
1242                 case DDR_CAS_5:
1243                         cas = 5 << 4;
1244                         break;
1245                 default:
1246                         printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1247                         spd_ddr_init_hang ();
1248                         break;
1249                 }
1250
1251 #if 0
1252                 /*
1253                  * ToDo - Still a problem with the write recovery:
1254                  * On the Corsair CM2X512-5400C4 module, setting write recovery
1255                  * in the INITPLR reg to the value calculated in program_mode()
1256                  * results in not correctly working DDR2 memory (crash after
1257                  * relocation).
1258                  *
1259                  * So for now, set the write recovery to 3. This seems to work
1260                  * on the Corair module too.
1261                  *
1262                  * 2007-03-01, sr
1263                  */
1264                 switch (write_recovery) {
1265                 case 3:
1266                         wr = WRITE_RECOV_3;
1267                         break;
1268                 case 4:
1269                         wr = WRITE_RECOV_4;
1270                         break;
1271                 case 5:
1272                         wr = WRITE_RECOV_5;
1273                         break;
1274                 case 6:
1275                         wr = WRITE_RECOV_6;
1276                         break;
1277                 default:
1278                         printf("ERROR: write recovery not support (%d)", write_recovery);
1279                         spd_ddr_init_hang ();
1280                         break;
1281                 }
1282 #else
1283                 wr = WRITE_RECOV_3; /* test-only, see description above */
1284 #endif
1285
1286                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1287                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1288                                 total_dimm++;
1289                 if (total_dimm == 1) {
1290                         odt = ODT_150_OHM;
1291                         ods = ODS_FULL;
1292                 } else if (total_dimm == 2) {
1293                         odt = ODT_75_OHM;
1294                         ods = ODS_REDUCED;
1295                 } else {
1296                         printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1297                         spd_ddr_init_hang ();
1298                 }
1299
1300                 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1301                 emr = CMD_EMR | SELECT_EMR | odt | ods;
1302                 emr2 = CMD_EMR | SELECT_EMR2;
1303                 emr3 = CMD_EMR | SELECT_EMR3;
1304                 mtsdram(SDRAM_INITPLR0,  0xB5000000 | CMD_NOP);         /* NOP */
1305                 udelay(1000);
1306                 mtsdram(SDRAM_INITPLR1,  0x82000400 | CMD_PRECHARGE);   /* precharge 8 DDR clock cycle */
1307                 mtsdram(SDRAM_INITPLR2,  0x80800000 | emr2);            /* EMR2 */
1308                 mtsdram(SDRAM_INITPLR3,  0x80800000 | emr3);            /* EMR3 */
1309                 mtsdram(SDRAM_INITPLR4,  0x80800000 | emr);             /* EMR DLL ENABLE */
1310                 mtsdram(SDRAM_INITPLR5,  0x80800000 | mr | DLL_RESET);  /* MR w/ DLL reset */
1311                 udelay(1000);
1312                 mtsdram(SDRAM_INITPLR6,  0x82000400 | CMD_PRECHARGE);   /* precharge 8 DDR clock cycle */
1313                 mtsdram(SDRAM_INITPLR7,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1314                 mtsdram(SDRAM_INITPLR8,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1315                 mtsdram(SDRAM_INITPLR9,  0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1316                 mtsdram(SDRAM_INITPLR10, 0x8a000000 | CMD_REFRESH);     /* Refresh  50 DDR clock cycle */
1317                 mtsdram(SDRAM_INITPLR11, 0x80000000 | mr);              /* MR w/o DLL reset */
1318                 mtsdram(SDRAM_INITPLR12, 0x80800380 | emr);             /* EMR OCD Default */
1319                 mtsdram(SDRAM_INITPLR13, 0x80800000 | emr);             /* EMR OCD Exit */
1320         } else {
1321                 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1322                 spd_ddr_init_hang ();
1323         }
1324 }
1325
1326 /*------------------------------------------------------------------
1327  * This routine programs the SDRAM_MMODE register.
1328  * the selected_cas is an output parameter, that will be passed
1329  * by caller to call the above program_initplr( )
1330  *-----------------------------------------------------------------*/
1331 static void program_mode(unsigned long *dimm_populated,
1332                          unsigned char *iic0_dimm_addr,
1333                          unsigned long num_dimm_banks,
1334                          ddr_cas_id_t *selected_cas,
1335                          int *write_recovery)
1336 {
1337         unsigned long dimm_num;
1338         unsigned long sdram_ddr1;
1339         unsigned long t_wr_ns;
1340         unsigned long t_wr_clk;
1341         unsigned long cas_bit;
1342         unsigned long cas_index;
1343         unsigned long sdram_freq;
1344         unsigned long ddr_check;
1345         unsigned long mmode;
1346         unsigned long tcyc_reg;
1347         unsigned long cycle_2_0_clk;
1348         unsigned long cycle_2_5_clk;
1349         unsigned long cycle_3_0_clk;
1350         unsigned long cycle_4_0_clk;
1351         unsigned long cycle_5_0_clk;
1352         unsigned long max_2_0_tcyc_ns_x_100;
1353         unsigned long max_2_5_tcyc_ns_x_100;
1354         unsigned long max_3_0_tcyc_ns_x_100;
1355         unsigned long max_4_0_tcyc_ns_x_100;
1356         unsigned long max_5_0_tcyc_ns_x_100;
1357         unsigned long cycle_time_ns_x_100[3];
1358         PPC440_SYS_INFO board_cfg;
1359         unsigned char cas_2_0_available;
1360         unsigned char cas_2_5_available;
1361         unsigned char cas_3_0_available;
1362         unsigned char cas_4_0_available;
1363         unsigned char cas_5_0_available;
1364         unsigned long sdr_ddrpll;
1365
1366         /*------------------------------------------------------------------
1367          * Get the board configuration info.
1368          *-----------------------------------------------------------------*/
1369         get_sys_info(&board_cfg);
1370
1371         mfsdr(SDR0_DDR0, sdr_ddrpll);
1372         sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1373         debug("sdram_freq=%d\n", sdram_freq);
1374
1375         /*------------------------------------------------------------------
1376          * Handle the timing.  We need to find the worst case timing of all
1377          * the dimm modules installed.
1378          *-----------------------------------------------------------------*/
1379         t_wr_ns = 0;
1380         cas_2_0_available = TRUE;
1381         cas_2_5_available = TRUE;
1382         cas_3_0_available = TRUE;
1383         cas_4_0_available = TRUE;
1384         cas_5_0_available = TRUE;
1385         max_2_0_tcyc_ns_x_100 = 10;
1386         max_2_5_tcyc_ns_x_100 = 10;
1387         max_3_0_tcyc_ns_x_100 = 10;
1388         max_4_0_tcyc_ns_x_100 = 10;
1389         max_5_0_tcyc_ns_x_100 = 10;
1390         sdram_ddr1 = TRUE;
1391
1392         /* loop through all the DIMM slots on the board */
1393         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1394                 /* If a dimm is installed in a particular slot ... */
1395                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1396                         if (dimm_populated[dimm_num] == SDRAM_DDR1)
1397                                 sdram_ddr1 = TRUE;
1398                         else
1399                                 sdram_ddr1 = FALSE;
1400
1401                         /* t_wr_ns = max(t_wr_ns, (unsigned long)dimm_spd[dimm_num][36] >> 2); */ /*  not used in this loop. */
1402                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1403                         debug("cas_bit[SPD byte 18]=%02x\n", cas_bit);
1404
1405                         /* For a particular DIMM, grab the three CAS values it supports */
1406                         for (cas_index = 0; cas_index < 3; cas_index++) {
1407                                 switch (cas_index) {
1408                                 case 0:
1409                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1410                                         break;
1411                                 case 1:
1412                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1413                                         break;
1414                                 default:
1415                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1416                                         break;
1417                                 }
1418
1419                                 if ((tcyc_reg & 0x0F) >= 10) {
1420                                         if ((tcyc_reg & 0x0F) == 0x0D) {
1421                                                 /* Convert from hex to decimal */
1422                                                 cycle_time_ns_x_100[cas_index] =
1423                                                         (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1424                                         } else {
1425                                                 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1426                                                        "in slot %d\n", (unsigned int)dimm_num);
1427                                                 spd_ddr_init_hang ();
1428                                         }
1429                                 } else {
1430                                         /* Convert from hex to decimal */
1431                                         cycle_time_ns_x_100[cas_index] =
1432                                                 (((tcyc_reg & 0xF0) >> 4) * 100) +
1433                                                 ((tcyc_reg & 0x0F)*10);
1434                                 }
1435                                 debug("cas_index=%d: cycle_time_ns_x_100=%d\n", cas_index,
1436                                       cycle_time_ns_x_100[cas_index]);
1437                         }
1438
1439                         /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1440                         /* supported for a particular DIMM. */
1441                         cas_index = 0;
1442
1443                         if (sdram_ddr1) {
1444                                 /*
1445                                  * DDR devices use the following bitmask for CAS latency:
1446                                  *  Bit   7    6    5    4    3    2    1    0
1447                                  *       TBD  4.0  3.5  3.0  2.5  2.0  1.5  1.0
1448                                  */
1449                                 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1450                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1451                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1452                                                                     cycle_time_ns_x_100[cas_index]);
1453                                         cas_index++;
1454                                 } else {
1455                                         if (cas_index != 0)
1456                                                 cas_index++;
1457                                         cas_4_0_available = FALSE;
1458                                 }
1459
1460                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1461                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1462                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1463                                                                     cycle_time_ns_x_100[cas_index]);
1464                                         cas_index++;
1465                                 } else {
1466                                         if (cas_index != 0)
1467                                                 cas_index++;
1468                                         cas_3_0_available = FALSE;
1469                                 }
1470
1471                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1472                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1473                                         max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1474                                                                     cycle_time_ns_x_100[cas_index]);
1475                                         cas_index++;
1476                                 } else {
1477                                         if (cas_index != 0)
1478                                                 cas_index++;
1479                                         cas_2_5_available = FALSE;
1480                                 }
1481
1482                                 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1483                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1484                                         max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1485                                                                     cycle_time_ns_x_100[cas_index]);
1486                                         cas_index++;
1487                                 } else {
1488                                         if (cas_index != 0)
1489                                                 cas_index++;
1490                                         cas_2_0_available = FALSE;
1491                                 }
1492                         } else {
1493                                 /*
1494                                  * DDR2 devices use the following bitmask for CAS latency:
1495                                  *  Bit   7    6    5    4    3    2    1    0
1496                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
1497                                  */
1498                                 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1499                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1500                                         max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1501                                                                     cycle_time_ns_x_100[cas_index]);
1502                                         cas_index++;
1503                                 } else {
1504                                         if (cas_index != 0)
1505                                                 cas_index++;
1506                                         cas_5_0_available = FALSE;
1507                                 }
1508
1509                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1510                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1511                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1512                                                                     cycle_time_ns_x_100[cas_index]);
1513                                         cas_index++;
1514                                 } else {
1515                                         if (cas_index != 0)
1516                                                 cas_index++;
1517                                         cas_4_0_available = FALSE;
1518                                 }
1519
1520                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1521                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1522                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1523                                                                     cycle_time_ns_x_100[cas_index]);
1524                                         cas_index++;
1525                                 } else {
1526                                         if (cas_index != 0)
1527                                                 cas_index++;
1528                                         cas_3_0_available = FALSE;
1529                                 }
1530                         }
1531                 }
1532         }
1533
1534         /*------------------------------------------------------------------
1535          * Set the SDRAM mode, SDRAM_MMODE
1536          *-----------------------------------------------------------------*/
1537         mfsdram(SDRAM_MMODE, mmode);
1538         mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1539
1540         /* add 10 here because of rounding problems */
1541         cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1542         cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1543         cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1544         cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1545         cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1546         debug("cycle_3_0_clk=%d\n", cycle_3_0_clk);
1547         debug("cycle_4_0_clk=%d\n", cycle_4_0_clk);
1548         debug("cycle_5_0_clk=%d\n", cycle_5_0_clk);
1549
1550         if (sdram_ddr1 == TRUE) { /* DDR1 */
1551                 if ((cas_2_0_available == TRUE) && (sdram_freq <= cycle_2_0_clk)) {
1552                         mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1553                         *selected_cas = DDR_CAS_2;
1554                 } else if ((cas_2_5_available == TRUE) && (sdram_freq <= cycle_2_5_clk)) {
1555                         mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1556                         *selected_cas = DDR_CAS_2_5;
1557                 } else if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1558                         mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1559                         *selected_cas = DDR_CAS_3;
1560                 } else {
1561                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1562                         printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1563                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1564                         spd_ddr_init_hang ();
1565                 }
1566         } else { /* DDR2 */
1567                 debug("cas_3_0_available=%d\n", cas_3_0_available);
1568                 debug("cas_4_0_available=%d\n", cas_4_0_available);
1569                 debug("cas_5_0_available=%d\n", cas_5_0_available);
1570                 if ((cas_3_0_available == TRUE) && (sdram_freq <= cycle_3_0_clk)) {
1571                         mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1572                         *selected_cas = DDR_CAS_3;
1573                 } else if ((cas_4_0_available == TRUE) && (sdram_freq <= cycle_4_0_clk)) {
1574                         mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1575                         *selected_cas = DDR_CAS_4;
1576                 } else if ((cas_5_0_available == TRUE) && (sdram_freq <= cycle_5_0_clk)) {
1577                         mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1578                         *selected_cas = DDR_CAS_5;
1579                 } else {
1580                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1581                         printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1582                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1583                         printf("cas3=%d cas4=%d cas5=%d\n",
1584                                cas_3_0_available, cas_4_0_available, cas_5_0_available);
1585                         printf("sdram_freq=%d cycle3=%d cycle4=%d cycle5=%d\n\n",
1586                                sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1587                         spd_ddr_init_hang ();
1588                 }
1589         }
1590
1591         if (sdram_ddr1 == TRUE)
1592                 mmode |= SDRAM_MMODE_WR_DDR1;
1593         else {
1594
1595                 /* loop through all the DIMM slots on the board */
1596                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1597                         /* If a dimm is installed in a particular slot ... */
1598                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1599                                 t_wr_ns = max(t_wr_ns,
1600                                               spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1601                 }
1602
1603                 /*
1604                  * convert from nanoseconds to ddr clocks
1605                  * round up if necessary
1606                  */
1607                 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1608                 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1609                 if (sdram_freq != ddr_check)
1610                         t_wr_clk++;
1611
1612                 switch (t_wr_clk) {
1613                 case 0:
1614                 case 1:
1615                 case 2:
1616                 case 3:
1617                         mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1618                         break;
1619                 case 4:
1620                         mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1621                         break;
1622                 case 5:
1623                         mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1624                         break;
1625                 default:
1626                         mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1627                         break;
1628                 }
1629                 *write_recovery = t_wr_clk;
1630         }
1631
1632         debug("CAS latency = %d\n", *selected_cas);
1633         debug("Write recovery = %d\n", *write_recovery);
1634
1635         mtsdram(SDRAM_MMODE, mmode);
1636 }
1637
1638 /*-----------------------------------------------------------------------------+
1639  * program_rtr.
1640  *-----------------------------------------------------------------------------*/
1641 static void program_rtr(unsigned long *dimm_populated,
1642                         unsigned char *iic0_dimm_addr,
1643                         unsigned long num_dimm_banks)
1644 {
1645         PPC440_SYS_INFO board_cfg;
1646         unsigned long max_refresh_rate;
1647         unsigned long dimm_num;
1648         unsigned long refresh_rate_type;
1649         unsigned long refresh_rate;
1650         unsigned long rint;
1651         unsigned long sdram_freq;
1652         unsigned long sdr_ddrpll;
1653         unsigned long val;
1654
1655         /*------------------------------------------------------------------
1656          * Get the board configuration info.
1657          *-----------------------------------------------------------------*/
1658         get_sys_info(&board_cfg);
1659
1660         /*------------------------------------------------------------------
1661          * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1662          *-----------------------------------------------------------------*/
1663         mfsdr(SDR0_DDR0, sdr_ddrpll);
1664         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1665
1666         max_refresh_rate = 0;
1667         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1668                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1669
1670                         refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1671                         refresh_rate_type &= 0x7F;
1672                         switch (refresh_rate_type) {
1673                         case 0:
1674                                 refresh_rate =  15625;
1675                                 break;
1676                         case 1:
1677                                 refresh_rate =   3906;
1678                                 break;
1679                         case 2:
1680                                 refresh_rate =   7812;
1681                                 break;
1682                         case 3:
1683                                 refresh_rate =  31250;
1684                                 break;
1685                         case 4:
1686                                 refresh_rate =  62500;
1687                                 break;
1688                         case 5:
1689                                 refresh_rate = 125000;
1690                                 break;
1691                         default:
1692                                 refresh_rate = 0;
1693                                 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1694                                        (unsigned int)dimm_num);
1695                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1696                                 spd_ddr_init_hang ();
1697                                 break;
1698                         }
1699
1700                         max_refresh_rate = max(max_refresh_rate, refresh_rate);
1701                 }
1702         }
1703
1704         rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1705         mfsdram(SDRAM_RTR, val);
1706         mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1707                 (SDRAM_RTR_RINT_ENCODE(rint)));
1708 }
1709
1710 /*------------------------------------------------------------------
1711  * This routine programs the SDRAM_TRx registers.
1712  *-----------------------------------------------------------------*/
1713 static void program_tr(unsigned long *dimm_populated,
1714                        unsigned char *iic0_dimm_addr,
1715                        unsigned long num_dimm_banks)
1716 {
1717         unsigned long dimm_num;
1718         unsigned long sdram_ddr1;
1719         unsigned long t_rp_ns;
1720         unsigned long t_rcd_ns;
1721         unsigned long t_rrd_ns;
1722         unsigned long t_ras_ns;
1723         unsigned long t_rc_ns;
1724         unsigned long t_rfc_ns;
1725         unsigned long t_wpc_ns;
1726         unsigned long t_wtr_ns;
1727         unsigned long t_rpc_ns;
1728         unsigned long t_rp_clk;
1729         unsigned long t_rcd_clk;
1730         unsigned long t_rrd_clk;
1731         unsigned long t_ras_clk;
1732         unsigned long t_rc_clk;
1733         unsigned long t_rfc_clk;
1734         unsigned long t_wpc_clk;
1735         unsigned long t_wtr_clk;
1736         unsigned long t_rpc_clk;
1737         unsigned long sdtr1, sdtr2, sdtr3;
1738         unsigned long ddr_check;
1739         unsigned long sdram_freq;
1740         unsigned long sdr_ddrpll;
1741
1742         PPC440_SYS_INFO board_cfg;
1743
1744         /*------------------------------------------------------------------
1745          * Get the board configuration info.
1746          *-----------------------------------------------------------------*/
1747         get_sys_info(&board_cfg);
1748
1749         mfsdr(SDR0_DDR0, sdr_ddrpll);
1750         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1751
1752         /*------------------------------------------------------------------
1753          * Handle the timing.  We need to find the worst case timing of all
1754          * the dimm modules installed.
1755          *-----------------------------------------------------------------*/
1756         t_rp_ns = 0;
1757         t_rrd_ns = 0;
1758         t_rcd_ns = 0;
1759         t_ras_ns = 0;
1760         t_rc_ns = 0;
1761         t_rfc_ns = 0;
1762         t_wpc_ns = 0;
1763         t_wtr_ns = 0;
1764         t_rpc_ns = 0;
1765         sdram_ddr1 = TRUE;
1766
1767         /* loop through all the DIMM slots on the board */
1768         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1769                 /* If a dimm is installed in a particular slot ... */
1770                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1771                         if (dimm_populated[dimm_num] == SDRAM_DDR2)
1772                                 sdram_ddr1 = TRUE;
1773                         else
1774                                 sdram_ddr1 = FALSE;
1775
1776                         t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1777                         t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1778                         t_rp_ns  = max(t_rp_ns,  spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1779                         t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1780                         t_rc_ns  = max(t_rc_ns,  spd_read(iic0_dimm_addr[dimm_num], 41));
1781                         t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1782                 }
1783         }
1784
1785         /*------------------------------------------------------------------
1786          * Set the SDRAM Timing Reg 1, SDRAM_TR1
1787          *-----------------------------------------------------------------*/
1788         mfsdram(SDRAM_SDTR1, sdtr1);
1789         sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1790                    SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1791
1792         /* default values */
1793         sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1794         sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1795
1796         /* normal operations */
1797         sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1798         sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1799
1800         mtsdram(SDRAM_SDTR1, sdtr1);
1801
1802         /*------------------------------------------------------------------
1803          * Set the SDRAM Timing Reg 2, SDRAM_TR2
1804          *-----------------------------------------------------------------*/
1805         mfsdram(SDRAM_SDTR2, sdtr2);
1806         sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK  | SDRAM_SDTR2_WTR_MASK |
1807                    SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1808                    SDRAM_SDTR2_RPC_MASK  | SDRAM_SDTR2_RP_MASK  |
1809                    SDRAM_SDTR2_RRD_MASK);
1810
1811         /*
1812          * convert t_rcd from nanoseconds to ddr clocks
1813          * round up if necessary
1814          */
1815         t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1816         ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1817         if (sdram_freq != ddr_check)
1818                 t_rcd_clk++;
1819
1820         switch (t_rcd_clk) {
1821         case 0:
1822         case 1:
1823                 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1824                 break;
1825         case 2:
1826                 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1827                 break;
1828         case 3:
1829                 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1830                 break;
1831         case 4:
1832                 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1833                 break;
1834         default:
1835                 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1836                 break;
1837         }
1838
1839         if (sdram_ddr1 == TRUE) { /* DDR1 */
1840                 if (sdram_freq < 200000000) {
1841                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1842                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1843                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1844                 } else {
1845                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1846                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1847                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1848                 }
1849         } else { /* DDR2 */
1850                 /* loop through all the DIMM slots on the board */
1851                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1852                         /* If a dimm is installed in a particular slot ... */
1853                         if (dimm_populated[dimm_num] != SDRAM_NONE) {
1854                                 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1855                                 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1856                                 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1857                         }
1858                 }
1859
1860                 /*
1861                  * convert from nanoseconds to ddr clocks
1862                  * round up if necessary
1863                  */
1864                 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1865                 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1866                 if (sdram_freq != ddr_check)
1867                         t_wpc_clk++;
1868
1869                 switch (t_wpc_clk) {
1870                 case 0:
1871                 case 1:
1872                 case 2:
1873                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1874                         break;
1875                 case 3:
1876                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1877                         break;
1878                 case 4:
1879                         sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1880                         break;
1881                 case 5:
1882                         sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1883                         break;
1884                 default:
1885                         sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1886                         break;
1887                 }
1888
1889                 /*
1890                  * convert from nanoseconds to ddr clocks
1891                  * round up if necessary
1892                  */
1893                 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1894                 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1895                 if (sdram_freq != ddr_check)
1896                         t_wtr_clk++;
1897
1898                 switch (t_wtr_clk) {
1899                 case 0:
1900                 case 1:
1901                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1902                         break;
1903                 case 2:
1904                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1905                         break;
1906                 case 3:
1907                         sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1908                         break;
1909                 default:
1910                         sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1911                         break;
1912                 }
1913
1914                 /*
1915                  * convert from nanoseconds to ddr clocks
1916                  * round up if necessary
1917                  */
1918                 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
1919                 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
1920                 if (sdram_freq != ddr_check)
1921                         t_rpc_clk++;
1922
1923                 switch (t_rpc_clk) {
1924                 case 0:
1925                 case 1:
1926                 case 2:
1927                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1928                         break;
1929                 case 3:
1930                         sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
1931                         break;
1932                 default:
1933                         sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
1934                         break;
1935                 }
1936         }
1937
1938         /* default value */
1939         sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
1940
1941         /*
1942          * convert t_rrd from nanoseconds to ddr clocks
1943          * round up if necessary
1944          */
1945         t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
1946         ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
1947         if (sdram_freq != ddr_check)
1948                 t_rrd_clk++;
1949
1950         if (t_rrd_clk == 3)
1951                 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
1952         else
1953                 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
1954
1955         /*
1956          * convert t_rp from nanoseconds to ddr clocks
1957          * round up if necessary
1958          */
1959         t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
1960         ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
1961         if (sdram_freq != ddr_check)
1962                 t_rp_clk++;
1963
1964         switch (t_rp_clk) {
1965         case 0:
1966         case 1:
1967         case 2:
1968         case 3:
1969                 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
1970                 break;
1971         case 4:
1972                 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
1973                 break;
1974         case 5:
1975                 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
1976                 break;
1977         case 6:
1978                 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
1979                 break;
1980         default:
1981                 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
1982                 break;
1983         }
1984
1985         mtsdram(SDRAM_SDTR2, sdtr2);
1986
1987         /*------------------------------------------------------------------
1988          * Set the SDRAM Timing Reg 3, SDRAM_TR3
1989          *-----------------------------------------------------------------*/
1990         mfsdram(SDRAM_SDTR3, sdtr3);
1991         sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK  | SDRAM_SDTR3_RC_MASK |
1992                    SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
1993
1994         /*
1995          * convert t_ras from nanoseconds to ddr clocks
1996          * round up if necessary
1997          */
1998         t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
1999         ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2000         if (sdram_freq != ddr_check)
2001                 t_ras_clk++;
2002
2003         sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2004
2005         /*
2006          * convert t_rc from nanoseconds to ddr clocks
2007          * round up if necessary
2008          */
2009         t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2010         ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2011         if (sdram_freq != ddr_check)
2012                 t_rc_clk++;
2013
2014         sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2015
2016         /* default xcs value */
2017         sdtr3 |= SDRAM_SDTR3_XCS;
2018
2019         /*
2020          * convert t_rfc from nanoseconds to ddr clocks
2021          * round up if necessary
2022          */
2023         t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2024         ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2025         if (sdram_freq != ddr_check)
2026                 t_rfc_clk++;
2027
2028         sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2029
2030         mtsdram(SDRAM_SDTR3, sdtr3);
2031 }
2032
2033 /*-----------------------------------------------------------------------------+
2034  * program_bxcf.
2035  *-----------------------------------------------------------------------------*/
2036 static void program_bxcf(unsigned long *dimm_populated,
2037                          unsigned char *iic0_dimm_addr,
2038                          unsigned long num_dimm_banks)
2039 {
2040         unsigned long dimm_num;
2041         unsigned long num_col_addr;
2042         unsigned long num_ranks;
2043         unsigned long num_banks;
2044         unsigned long mode;
2045         unsigned long ind_rank;
2046         unsigned long ind;
2047         unsigned long ind_bank;
2048         unsigned long bank_0_populated;
2049
2050         /*------------------------------------------------------------------
2051          * Set the BxCF regs.  First, wipe out the bank config registers.
2052          *-----------------------------------------------------------------*/
2053         mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF);
2054         mtdcr(SDRAMC_CFGDATA, 0x00000000);
2055         mtdcr(SDRAMC_CFGADDR, SDRAM_MB1CF);
2056         mtdcr(SDRAMC_CFGDATA, 0x00000000);
2057         mtdcr(SDRAMC_CFGADDR, SDRAM_MB2CF);
2058         mtdcr(SDRAMC_CFGDATA, 0x00000000);
2059         mtdcr(SDRAMC_CFGADDR, SDRAM_MB3CF);
2060         mtdcr(SDRAMC_CFGDATA, 0x00000000);
2061
2062         mode = SDRAM_BXCF_M_BE_ENABLE;
2063
2064         bank_0_populated = 0;
2065
2066         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2067                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2068                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2069                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2070                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2071                                 num_ranks = (num_ranks & 0x0F) +1;
2072                         else
2073                                 num_ranks = num_ranks & 0x0F;
2074
2075                         num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2076
2077                         for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2078                                 if (num_banks == 4)
2079                                         ind = 0;
2080                                 else
2081                                         ind = 5;
2082                                 switch (num_col_addr) {
2083                                 case 0x08:
2084                                         mode |= (SDRAM_BXCF_M_AM_0 + ind);
2085                                         break;
2086                                 case 0x09:
2087                                         mode |= (SDRAM_BXCF_M_AM_1 + ind);
2088                                         break;
2089                                 case 0x0A:
2090                                         mode |= (SDRAM_BXCF_M_AM_2 + ind);
2091                                         break;
2092                                 case 0x0B:
2093                                         mode |= (SDRAM_BXCF_M_AM_3 + ind);
2094                                         break;
2095                                 case 0x0C:
2096                                         mode |= (SDRAM_BXCF_M_AM_4 + ind);
2097                                         break;
2098                                 default:
2099                                         printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2100                                                (unsigned int)dimm_num);
2101                                         printf("ERROR: Unsupported value for number of "
2102                                                "column addresses: %d.\n", (unsigned int)num_col_addr);
2103                                         printf("Replace the DIMM module with a supported DIMM.\n\n");
2104                                         spd_ddr_init_hang ();
2105                                 }
2106                         }
2107
2108                         if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2109                                 bank_0_populated = 1;
2110
2111                         for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2112                                 mtdcr(SDRAMC_CFGADDR, SDRAM_MB0CF + ((dimm_num + bank_0_populated + ind_rank) << 2));
2113                                 mtdcr(SDRAMC_CFGDATA, mode);
2114                         }
2115                 }
2116         }
2117 }
2118
2119 /*------------------------------------------------------------------
2120  * program memory queue.
2121  *-----------------------------------------------------------------*/
2122 static void program_memory_queue(unsigned long *dimm_populated,
2123                                  unsigned char *iic0_dimm_addr,
2124                                  unsigned long num_dimm_banks)
2125 {
2126         unsigned long dimm_num;
2127         unsigned long rank_base_addr;
2128         unsigned long rank_reg;
2129         unsigned long rank_size_bytes;
2130         unsigned long rank_size_id;
2131         unsigned long num_ranks;
2132         unsigned long baseadd_size;
2133         unsigned long i;
2134         unsigned long bank_0_populated = 0;
2135
2136         /*------------------------------------------------------------------
2137          * Reset the rank_base_address.
2138          *-----------------------------------------------------------------*/
2139         rank_reg   = SDRAM_R0BAS;
2140
2141         rank_base_addr = 0x00000000;
2142
2143         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2144                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2145                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2146                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2147                                 num_ranks = (num_ranks & 0x0F) + 1;
2148                         else
2149                                 num_ranks = num_ranks & 0x0F;
2150
2151                         rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2152
2153                         /*------------------------------------------------------------------
2154                          * Set the sizes
2155                          *-----------------------------------------------------------------*/
2156                         baseadd_size = 0;
2157                         rank_size_bytes = 4 * 1024 * 1024 * rank_size_id;
2158                         switch (rank_size_id) {
2159                         case 0x02:
2160                                 baseadd_size |= SDRAM_RXBAS_SDSZ_8;
2161                                 break;
2162                         case 0x04:
2163                                 baseadd_size |= SDRAM_RXBAS_SDSZ_16;
2164                                 break;
2165                         case 0x08:
2166                                 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2167                                 break;
2168                         case 0x10:
2169                                 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2170                                 break;
2171                         case 0x20:
2172                                 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2173                                 break;
2174                         case 0x40:
2175                                 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2176                                 break;
2177                         case 0x80:
2178                                 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2179                                 break;
2180                         default:
2181                                 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2182                                        (unsigned int)dimm_num);
2183                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
2184                                        (unsigned int)rank_size_id);
2185                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
2186                                 spd_ddr_init_hang ();
2187                         }
2188
2189                         if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2190                                 bank_0_populated = 1;
2191
2192                         for (i = 0; i < num_ranks; i++) {
2193                                 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2194                                           (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2195                                            baseadd_size));
2196                                 rank_base_addr += rank_size_bytes;
2197                         }
2198                 }
2199         }
2200 }
2201
2202 /*-----------------------------------------------------------------------------+
2203  * is_ecc_enabled.
2204  *-----------------------------------------------------------------------------*/
2205 static unsigned long is_ecc_enabled(void)
2206 {
2207         unsigned long dimm_num;
2208         unsigned long ecc;
2209         unsigned long val;
2210
2211         ecc = 0;
2212         /* loop through all the DIMM slots on the board */
2213         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2214                 mfsdram(SDRAM_MCOPT1, val);
2215                 ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val));
2216         }
2217
2218         return ecc;
2219 }
2220
2221 static void blank_string(int size)
2222 {
2223         int i;
2224
2225         for (i=0; i<size; i++)
2226                 putc('\b');
2227         for (i=0; i<size; i++)
2228                 putc(' ');
2229         for (i=0; i<size; i++)
2230                 putc('\b');
2231 }
2232
2233 #ifdef CONFIG_DDR_ECC
2234 /*-----------------------------------------------------------------------------+
2235  * program_ecc.
2236  *-----------------------------------------------------------------------------*/
2237 static void program_ecc(unsigned long *dimm_populated,
2238                         unsigned char *iic0_dimm_addr,
2239                         unsigned long num_dimm_banks,
2240                         unsigned long tlb_word2_i_value)
2241 {
2242         unsigned long mcopt1;
2243         unsigned long mcopt2;
2244         unsigned long mcstat;
2245         unsigned long dimm_num;
2246         unsigned long ecc;
2247
2248         ecc = 0;
2249         /* loop through all the DIMM slots on the board */
2250         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2251                 /* If a dimm is installed in a particular slot ... */
2252                 if (dimm_populated[dimm_num] != SDRAM_NONE)
2253                         ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2254         }
2255         if (ecc == 0)
2256                 return;
2257
2258         mfsdram(SDRAM_MCOPT1, mcopt1);
2259         mfsdram(SDRAM_MCOPT2, mcopt2);
2260
2261         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2262                 /* DDR controller must be enabled and not in self-refresh. */
2263                 mfsdram(SDRAM_MCSTAT, mcstat);
2264                 if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
2265                     && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
2266                     && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
2267                         == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
2268
2269                         program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value);
2270                 }
2271         }
2272
2273         return;
2274 }
2275
2276 #ifdef CONFIG_ECC_ERROR_RESET
2277 /*
2278  * Check for ECC errors and reset board upon any error here
2279  *
2280  * On the Katmai 440SPe eval board, from time to time, the first
2281  * lword write access after DDR2 initializazion with ECC checking
2282  * enabled, leads to an ECC error. I couldn't find a configuration
2283  * without this happening. On my board with the current setup it
2284  * happens about 1 from 10 times.
2285  *
2286  * The ECC modules used for testing are:
2287  * - Kingston ValueRAM KVR667D2E5/512 (tested with 1 and 2 DIMM's)
2288  *
2289  * This has to get fixed for the Katmai and tested for the other
2290  * board (440SP/440SPe) that will eventually use this code in the
2291  * future.
2292  *
2293  * 2007-03-01, sr
2294  */
2295 static void check_ecc(void)
2296 {
2297         u32 val;
2298
2299         mfsdram(SDRAM_ECCCR, val);
2300         if (val != 0) {
2301                 printf("\nECC error: MCIF0_ECCES=%08lx MQ0_ESL=%08lx address=%08lx\n",
2302                        val, mfdcr(0x4c), mfdcr(0x4e));
2303                 printf("ECC error occured, resetting board...\n");
2304                 do_reset(NULL, 0, 0, NULL);
2305         }
2306 }
2307 #endif
2308
2309 static void wait_ddr_idle(void)
2310 {
2311         u32 val;
2312
2313         do {
2314                 mfsdram(SDRAM_MCSTAT, val);
2315         } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT);
2316 }
2317
2318 /*-----------------------------------------------------------------------------+
2319  * program_ecc_addr.
2320  *-----------------------------------------------------------------------------*/
2321 static void program_ecc_addr(unsigned long start_address,
2322                              unsigned long num_bytes,
2323                              unsigned long tlb_word2_i_value)
2324 {
2325         unsigned long current_address;
2326         unsigned long end_address;
2327         unsigned long address_increment;
2328         unsigned long mcopt1;
2329         char str[] = "ECC generation -";
2330         char slash[] = "\\|/-\\|/-";
2331         int loop = 0;
2332         int loopi = 0;
2333
2334         current_address = start_address;
2335         mfsdram(SDRAM_MCOPT1, mcopt1);
2336         if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) {
2337                 mtsdram(SDRAM_MCOPT1,
2338                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN);
2339                 sync();
2340                 eieio();
2341                 wait_ddr_idle();
2342
2343                 puts(str);
2344                 if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
2345                         /* ECC bit set method for non-cached memory */
2346                         if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32)
2347                                 address_increment = 4;
2348                         else
2349                                 address_increment = 8;
2350                         end_address = current_address + num_bytes;
2351
2352                         while (current_address < end_address) {
2353                                 *((unsigned long *)current_address) = 0x00000000;
2354                                 current_address += address_increment;
2355
2356                                 if ((loop++ % (2 << 20)) == 0) {
2357                                         putc('\b');
2358                                         putc(slash[loopi++ % 8]);
2359                                 }
2360                         }
2361
2362                 } else {
2363                         /* ECC bit set method for cached memory */
2364                         dcbz_area(start_address, num_bytes);
2365                         dflush();
2366                 }
2367
2368                 blank_string(strlen(str));
2369
2370                 sync();
2371                 eieio();
2372                 wait_ddr_idle();
2373
2374                 /* clear ECC error repoting registers */
2375                 mtsdram(SDRAM_ECCCR, 0xffffffff);
2376                 mtdcr(0x4c, 0xffffffff);
2377
2378                 mtsdram(SDRAM_MCOPT1,
2379                         (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP);
2380                 sync();
2381                 eieio();
2382                 wait_ddr_idle();
2383
2384 #ifdef CONFIG_ECC_ERROR_RESET
2385                 /*
2386                  * One write to 0 is enough to trigger this ECC error
2387                  * (see description above)
2388                  */
2389                 out_be32(0, 0x12345678);
2390                 check_ecc();
2391 #endif
2392         }
2393 }
2394 #endif
2395
2396 /*-----------------------------------------------------------------------------+
2397  * program_DQS_calibration.
2398  *-----------------------------------------------------------------------------*/
2399 static void program_DQS_calibration(unsigned long *dimm_populated,
2400                                     unsigned char *iic0_dimm_addr,
2401                                     unsigned long num_dimm_banks)
2402 {
2403         unsigned long val;
2404
2405 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2406         mtsdram(SDRAM_RQDC, 0x80000037);
2407         mtsdram(SDRAM_RDCC, 0x40000000);
2408         mtsdram(SDRAM_RFDC, 0x000001DF);
2409
2410         test();
2411 #else
2412         /*------------------------------------------------------------------
2413          * Program RDCC register
2414          * Read sample cycle auto-update enable
2415          *-----------------------------------------------------------------*/
2416
2417         /*
2418          * Modified for the Katmai platform:  with some DIMMs, the DDR2
2419          * controller automatically selects the T2 read cycle, but this
2420          * proves unreliable.  Go ahead and force the DDR2 controller
2421          * to use the T4 sample and disable the automatic update of the
2422          * RDSS field.
2423          */
2424         mfsdram(SDRAM_RDCC, val);
2425         mtsdram(SDRAM_RDCC,
2426                 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2427                 | (SDRAM_RDCC_RDSS_T4 | SDRAM_RDCC_RSAE_DISABLE));
2428
2429         /*------------------------------------------------------------------
2430          * Program RQDC register
2431          * Internal DQS delay mechanism enable
2432          *-----------------------------------------------------------------*/
2433         mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2434
2435         /*------------------------------------------------------------------
2436          * Program RFDC register
2437          * Set Feedback Fractional Oversample
2438          * Auto-detect read sample cycle enable
2439          *-----------------------------------------------------------------*/
2440         mfsdram(SDRAM_RFDC, val);
2441         mtsdram(SDRAM_RFDC,
2442                 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2443                          SDRAM_RFDC_RFFD_MASK))
2444                 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0) |
2445                    SDRAM_RFDC_RFFD_ENCODE(0)));
2446
2447         DQS_calibration_process();
2448 #endif
2449 }
2450
2451 static int short_mem_test(void)
2452 {
2453         u32 *membase;
2454         u32 bxcr_num;
2455         u32 bxcf;
2456         int i;
2457         int j;
2458         u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2459                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2460                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2461                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2462                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2463                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2464                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2465                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2466                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2467                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2468                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2469                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2470                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2471                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2472                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2473                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2474                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2475         int l;
2476
2477         for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2478                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2479
2480                 /* Banks enabled */
2481                 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2482                         /* Bank is enabled */
2483
2484                         /*------------------------------------------------------------------
2485                          * Run the short memory test.
2486                          *-----------------------------------------------------------------*/
2487                         membase = (u32 *)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num)));
2488
2489                         for (i = 0; i < NUMMEMTESTS; i++) {
2490                                 for (j = 0; j < NUMMEMWORDS; j++) {
2491                                         membase[j] = test[i][j];
2492                                         ppcDcbf((u32)&(membase[j]));
2493                                 }
2494                                 sync();
2495                                 for (l=0; l<NUMLOOPS; l++) {
2496                                         for (j = 0; j < NUMMEMWORDS; j++) {
2497                                                 if (membase[j] != test[i][j]) {
2498                                                         ppcDcbf((u32)&(membase[j]));
2499                                                         return 0;
2500                                                 }
2501                                                 ppcDcbf((u32)&(membase[j]));
2502                                         }
2503                                         sync();
2504                                 }
2505                         }
2506                 }       /* if bank enabled */
2507         }               /* for bxcf_num */
2508
2509         return 1;
2510 }
2511
2512 #ifndef HARD_CODED_DQS
2513 /*-----------------------------------------------------------------------------+
2514  * DQS_calibration_process.
2515  *-----------------------------------------------------------------------------*/
2516 static void DQS_calibration_process(void)
2517 {
2518         unsigned long rfdc_reg;
2519         unsigned long rffd;
2520         unsigned long rqdc_reg;
2521         unsigned long rqfd;
2522         unsigned long val;
2523         long rqfd_average;
2524         long rffd_average;
2525         long max_start;
2526         long min_end;
2527         unsigned long begin_rqfd[MAXRANKS];
2528         unsigned long begin_rffd[MAXRANKS];
2529         unsigned long end_rqfd[MAXRANKS];
2530         unsigned long end_rffd[MAXRANKS];
2531         char window_found;
2532         unsigned long dlycal;
2533         unsigned long dly_val;
2534         unsigned long max_pass_length;
2535         unsigned long current_pass_length;
2536         unsigned long current_fail_length;
2537         unsigned long current_start;
2538         long max_end;
2539         unsigned char fail_found;
2540         unsigned char pass_found;
2541         u32 rqfd_start;
2542         char str[] = "Auto calibration -";
2543         char slash[] = "\\|/-\\|/-";
2544         int loopi = 0;
2545
2546         /*------------------------------------------------------------------
2547          * Test to determine the best read clock delay tuning bits.
2548          *
2549          * Before the DDR controller can be used, the read clock delay needs to be
2550          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2551          * This value cannot be hardcoded into the program because it changes
2552          * depending on the board's setup and environment.
2553          * To do this, all delay values are tested to see if they
2554          * work or not.  By doing this, you get groups of fails with groups of
2555          * passing values.  The idea is to find the start and end of a passing
2556          * window and take the center of it to use as the read clock delay.
2557          *
2558          * A failure has to be seen first so that when we hit a pass, we know
2559          * that it is truely the start of the window.  If we get passing values
2560          * to start off with, we don't know if we are at the start of the window.
2561          *
2562          * The code assumes that a failure will always be found.
2563          * If a failure is not found, there is no easy way to get the middle
2564          * of the passing window.  I guess we can pretty much pick any value
2565          * but some values will be better than others.  Since the lowest speed
2566          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2567          * from experimentation it is safe to say you will always have a failure.
2568          *-----------------------------------------------------------------*/
2569
2570         /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2571         rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2572
2573         puts(str);
2574
2575 calibration_loop:
2576         mfsdram(SDRAM_RQDC, rqdc_reg);
2577         mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2578                 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2579
2580         max_start = 0;
2581         min_end = 0;
2582         begin_rqfd[0] = 0;
2583         begin_rffd[0] = 0;
2584         begin_rqfd[1] = 0;
2585         begin_rffd[1] = 0;
2586         end_rqfd[0] = 0;
2587         end_rffd[0] = 0;
2588         end_rqfd[1] = 0;
2589         end_rffd[1] = 0;
2590         window_found = FALSE;
2591
2592         max_pass_length = 0;
2593         max_start = 0;
2594         max_end = 0;
2595         current_pass_length = 0;
2596         current_fail_length = 0;
2597         current_start = 0;
2598         window_found = FALSE;
2599         fail_found = FALSE;
2600         pass_found = FALSE;
2601
2602         /*
2603          * get the delay line calibration register value
2604          */
2605         mfsdram(SDRAM_DLCR, dlycal);
2606         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2607
2608         for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2609                 mfsdram(SDRAM_RFDC, rfdc_reg);
2610                 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2611
2612                 /*------------------------------------------------------------------
2613                  * Set the timing reg for the test.
2614                  *-----------------------------------------------------------------*/
2615                 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2616
2617                 /*------------------------------------------------------------------
2618                  * See if the rffd value passed.
2619                  *-----------------------------------------------------------------*/
2620                 if (short_mem_test()) {
2621                         if (fail_found == TRUE) {
2622                                 pass_found = TRUE;
2623                                 if (current_pass_length == 0)
2624                                         current_start = rffd;
2625
2626                                 current_fail_length = 0;
2627                                 current_pass_length++;
2628
2629                                 if (current_pass_length > max_pass_length) {
2630                                         max_pass_length = current_pass_length;
2631                                         max_start = current_start;
2632                                         max_end = rffd;
2633                                 }
2634                         }
2635                 } else {
2636                         current_pass_length = 0;
2637                         current_fail_length++;
2638
2639                         if (current_fail_length >= (dly_val >> 2)) {
2640                                 if (fail_found == FALSE) {
2641                                         fail_found = TRUE;
2642                                 } else if (pass_found == TRUE) {
2643                                         window_found = TRUE;
2644                                         break;
2645                                 }
2646                         }
2647                 }
2648         }               /* for rffd */
2649
2650         /*------------------------------------------------------------------
2651          * Set the average RFFD value
2652          *-----------------------------------------------------------------*/
2653         rffd_average = ((max_start + max_end) >> 1);
2654
2655         if (rffd_average < 0)
2656                 rffd_average = 0;
2657
2658         if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2659                 rffd_average = SDRAM_RFDC_RFFD_MAX;
2660         /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2661         mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2662
2663         max_pass_length = 0;
2664         max_start = 0;
2665         max_end = 0;
2666         current_pass_length = 0;
2667         current_fail_length = 0;
2668         current_start = 0;
2669         window_found = FALSE;
2670         fail_found = FALSE;
2671         pass_found = FALSE;
2672
2673         for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2674                 mfsdram(SDRAM_RQDC, rqdc_reg);
2675                 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2676
2677                 /*------------------------------------------------------------------
2678                  * Set the timing reg for the test.
2679                  *-----------------------------------------------------------------*/
2680                 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2681
2682                 /*------------------------------------------------------------------
2683                  * See if the rffd value passed.
2684                  *-----------------------------------------------------------------*/
2685                 if (short_mem_test()) {
2686                         if (fail_found == TRUE) {
2687                                 pass_found = TRUE;
2688                                 if (current_pass_length == 0)
2689                                         current_start = rqfd;
2690
2691                                 current_fail_length = 0;
2692                                 current_pass_length++;
2693
2694                                 if (current_pass_length > max_pass_length) {
2695                                         max_pass_length = current_pass_length;
2696                                         max_start = current_start;
2697                                         max_end = rqfd;
2698                                 }
2699                         }
2700                 } else {
2701                         current_pass_length = 0;
2702                         current_fail_length++;
2703
2704                         if (fail_found == FALSE) {
2705                                 fail_found = TRUE;
2706                         } else if (pass_found == TRUE) {
2707                                 window_found = TRUE;
2708                                 break;
2709                         }
2710                 }
2711         }
2712
2713         rqfd_average = ((max_start + max_end) >> 1);
2714
2715         /*------------------------------------------------------------------
2716          * Make sure we found the valid read passing window.  Halt if not
2717          *-----------------------------------------------------------------*/
2718         if (window_found == FALSE) {
2719                 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2720                         putc('\b');
2721                         putc(slash[loopi++ % 8]);
2722
2723                         /* try again from with a different RQFD start value */
2724                         rqfd_start++;
2725                         goto calibration_loop;
2726                 }
2727
2728                 printf("\nERROR: Cannot determine a common read delay for the "
2729                        "DIMM(s) installed.\n");
2730                 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2731                 ppc440sp_sdram_register_dump();
2732                 spd_ddr_init_hang ();
2733         }
2734
2735         blank_string(strlen(str));
2736
2737         if (rqfd_average < 0)
2738                 rqfd_average = 0;
2739
2740         if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2741                 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2742
2743         mtsdram(SDRAM_RQDC,
2744                 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2745                 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2746
2747         mfsdram(SDRAM_DLCR, val);
2748         debug("%s[%d] DLCR: 0x%08X\n", __FUNCTION__, __LINE__, val);
2749         mfsdram(SDRAM_RQDC, val);
2750         debug("%s[%d] RQDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2751         mfsdram(SDRAM_RFDC, val);
2752         debug("%s[%d] RFDC: 0x%08X\n", __FUNCTION__, __LINE__, val);
2753 }
2754 #else /* calibration test with hardvalues */
2755 /*-----------------------------------------------------------------------------+
2756  * DQS_calibration_process.
2757  *-----------------------------------------------------------------------------*/
2758 static void test(void)
2759 {
2760         unsigned long dimm_num;
2761         unsigned long ecc_temp;
2762         unsigned long i, j;
2763         unsigned long *membase;
2764         unsigned long bxcf[MAXRANKS];
2765         unsigned long val;
2766         char window_found;
2767         char begin_found[MAXDIMMS];
2768         char end_found[MAXDIMMS];
2769         char search_end[MAXDIMMS];
2770         unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2771                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2772                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2773                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2774                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2775                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2776                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2777                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2778                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2779                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2780                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2781                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2782                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2783                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2784                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2785                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2786                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2787
2788         /*------------------------------------------------------------------
2789          * Test to determine the best read clock delay tuning bits.
2790          *
2791          * Before the DDR controller can be used, the read clock delay needs to be
2792          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2793          * This value cannot be hardcoded into the program because it changes
2794          * depending on the board's setup and environment.
2795          * To do this, all delay values are tested to see if they
2796          * work or not.  By doing this, you get groups of fails with groups of
2797          * passing values.  The idea is to find the start and end of a passing
2798          * window and take the center of it to use as the read clock delay.
2799          *
2800          * A failure has to be seen first so that when we hit a pass, we know
2801          * that it is truely the start of the window.  If we get passing values
2802          * to start off with, we don't know if we are at the start of the window.
2803          *
2804          * The code assumes that a failure will always be found.
2805          * If a failure is not found, there is no easy way to get the middle
2806          * of the passing window.  I guess we can pretty much pick any value
2807          * but some values will be better than others.  Since the lowest speed
2808          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2809          * from experimentation it is safe to say you will always have a failure.
2810          *-----------------------------------------------------------------*/
2811         mfsdram(SDRAM_MCOPT1, ecc_temp);
2812         ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2813         mfsdram(SDRAM_MCOPT1, val);
2814         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2815                 SDRAM_MCOPT1_MCHK_NON);
2816
2817         window_found = FALSE;
2818         begin_found[0] = FALSE;
2819         end_found[0] = FALSE;
2820         search_end[0] = FALSE;
2821         begin_found[1] = FALSE;
2822         end_found[1] = FALSE;
2823         search_end[1] = FALSE;
2824
2825         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2826                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2827
2828                 /* Banks enabled */
2829                 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2830
2831                         /* Bank is enabled */
2832                         membase =
2833                                 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2834
2835                         /*------------------------------------------------------------------
2836                          * Run the short memory test.
2837                          *-----------------------------------------------------------------*/
2838                         for (i = 0; i < NUMMEMTESTS; i++) {
2839                                 for (j = 0; j < NUMMEMWORDS; j++) {
2840                                         membase[j] = test[i][j];
2841                                         ppcDcbf((u32)&(membase[j]));
2842                                 }
2843                                 sync();
2844                                 for (j = 0; j < NUMMEMWORDS; j++) {
2845                                         if (membase[j] != test[i][j]) {
2846                                                 ppcDcbf((u32)&(membase[j]));
2847                                                 break;
2848                                         }
2849                                         ppcDcbf((u32)&(membase[j]));
2850                                 }
2851                                 sync();
2852                                 if (j < NUMMEMWORDS)
2853                                         break;
2854                         }
2855
2856                         /*------------------------------------------------------------------
2857                          * See if the rffd value passed.
2858                          *-----------------------------------------------------------------*/
2859                         if (i < NUMMEMTESTS) {
2860                                 if ((end_found[dimm_num] == FALSE) &&
2861                                     (search_end[dimm_num] == TRUE)) {
2862                                         end_found[dimm_num] = TRUE;
2863                                 }
2864                                 if ((end_found[0] == TRUE) &&
2865                                     (end_found[1] == TRUE))
2866                                         break;
2867                         } else {
2868                                 if (begin_found[dimm_num] == FALSE) {
2869                                         begin_found[dimm_num] = TRUE;
2870                                         search_end[dimm_num] = TRUE;
2871                                 }
2872                         }
2873                 } else {
2874                         begin_found[dimm_num] = TRUE;
2875                         end_found[dimm_num] = TRUE;
2876                 }
2877         }
2878
2879         if ((begin_found[0] == TRUE) && (begin_found[1] == TRUE))
2880                 window_found = TRUE;
2881
2882         /*------------------------------------------------------------------
2883          * Make sure we found the valid read passing window.  Halt if not
2884          *-----------------------------------------------------------------*/
2885         if (window_found == FALSE) {
2886                 printf("ERROR: Cannot determine a common read delay for the "
2887                        "DIMM(s) installed.\n");
2888                 spd_ddr_init_hang ();
2889         }
2890
2891         /*------------------------------------------------------------------
2892          * Restore the ECC variable to what it originally was
2893          *-----------------------------------------------------------------*/
2894         mtsdram(SDRAM_MCOPT1,
2895                 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2896                 | ecc_temp);
2897 }
2898 #endif
2899
2900 #if defined(DEBUG)
2901 static void ppc440sp_sdram_register_dump(void)
2902 {
2903         unsigned int sdram_reg;
2904         unsigned int sdram_data;
2905         unsigned int dcr_data;
2906
2907         printf("\n  Register Dump:\n");
2908         sdram_reg = SDRAM_MCSTAT;
2909         mfsdram(sdram_reg, sdram_data);
2910         printf("        SDRAM_MCSTAT    = 0x%08X", sdram_data);
2911         sdram_reg = SDRAM_MCOPT1;
2912         mfsdram(sdram_reg, sdram_data);
2913         printf("        SDRAM_MCOPT1    = 0x%08X\n", sdram_data);
2914         sdram_reg = SDRAM_MCOPT2;
2915         mfsdram(sdram_reg, sdram_data);
2916         printf("        SDRAM_MCOPT2    = 0x%08X", sdram_data);
2917         sdram_reg = SDRAM_MODT0;
2918         mfsdram(sdram_reg, sdram_data);
2919         printf("        SDRAM_MODT0     = 0x%08X\n", sdram_data);
2920         sdram_reg = SDRAM_MODT1;
2921         mfsdram(sdram_reg, sdram_data);
2922         printf("        SDRAM_MODT1     = 0x%08X", sdram_data);
2923         sdram_reg = SDRAM_MODT2;
2924         mfsdram(sdram_reg, sdram_data);
2925         printf("        SDRAM_MODT2     = 0x%08X\n", sdram_data);
2926         sdram_reg = SDRAM_MODT3;
2927         mfsdram(sdram_reg, sdram_data);
2928         printf("        SDRAM_MODT3     = 0x%08X", sdram_data);
2929         sdram_reg = SDRAM_CODT;
2930         mfsdram(sdram_reg, sdram_data);
2931         printf("        SDRAM_CODT      = 0x%08X\n", sdram_data);
2932         sdram_reg = SDRAM_VVPR;
2933         mfsdram(sdram_reg, sdram_data);
2934         printf("        SDRAM_VVPR      = 0x%08X", sdram_data);
2935         sdram_reg = SDRAM_OPARS;
2936         mfsdram(sdram_reg, sdram_data);
2937         printf("        SDRAM_OPARS     = 0x%08X\n", sdram_data);
2938         /*
2939          * OPAR2 is only used as a trigger register.
2940          * No data is contained in this register, and reading or writing
2941          * to is can cause bad things to happen (hangs).  Just skip it
2942          * and report NA
2943          * sdram_reg = SDRAM_OPAR2;
2944          * mfsdram(sdram_reg, sdram_data);
2945          * printf("        SDRAM_OPAR2     = 0x%08X\n", sdram_data);
2946          */
2947         printf("        SDRAM_OPART     = N/A       ");
2948         sdram_reg = SDRAM_RTR;
2949         mfsdram(sdram_reg, sdram_data);
2950         printf("        SDRAM_RTR       = 0x%08X\n", sdram_data);
2951         sdram_reg = SDRAM_MB0CF;
2952         mfsdram(sdram_reg, sdram_data);
2953         printf("        SDRAM_MB0CF     = 0x%08X", sdram_data);
2954         sdram_reg = SDRAM_MB1CF;
2955         mfsdram(sdram_reg, sdram_data);
2956         printf("        SDRAM_MB1CF     = 0x%08X\n", sdram_data);
2957         sdram_reg = SDRAM_MB2CF;
2958         mfsdram(sdram_reg, sdram_data);
2959         printf("        SDRAM_MB2CF     = 0x%08X", sdram_data);
2960         sdram_reg = SDRAM_MB3CF;
2961         mfsdram(sdram_reg, sdram_data);
2962         printf("        SDRAM_MB3CF     = 0x%08X\n", sdram_data);
2963         sdram_reg = SDRAM_INITPLR0;
2964         mfsdram(sdram_reg, sdram_data);
2965         printf("        SDRAM_INITPLR0  = 0x%08X", sdram_data);
2966         sdram_reg = SDRAM_INITPLR1;
2967         mfsdram(sdram_reg, sdram_data);
2968         printf("        SDRAM_INITPLR1  = 0x%08X\n", sdram_data);
2969         sdram_reg = SDRAM_INITPLR2;
2970         mfsdram(sdram_reg, sdram_data);
2971         printf("        SDRAM_INITPLR2  = 0x%08X", sdram_data);
2972         sdram_reg = SDRAM_INITPLR3;
2973         mfsdram(sdram_reg, sdram_data);
2974         printf("        SDRAM_INITPLR3  = 0x%08X\n", sdram_data);
2975         sdram_reg = SDRAM_INITPLR4;
2976         mfsdram(sdram_reg, sdram_data);
2977         printf("        SDRAM_INITPLR4  = 0x%08X", sdram_data);
2978         sdram_reg = SDRAM_INITPLR5;
2979         mfsdram(sdram_reg, sdram_data);
2980         printf("        SDRAM_INITPLR5  = 0x%08X\n", sdram_data);
2981         sdram_reg = SDRAM_INITPLR6;
2982         mfsdram(sdram_reg, sdram_data);
2983         printf("        SDRAM_INITPLR6  = 0x%08X", sdram_data);
2984         sdram_reg = SDRAM_INITPLR7;
2985         mfsdram(sdram_reg, sdram_data);
2986         printf("        SDRAM_INITPLR7  = 0x%08X\n", sdram_data);
2987         sdram_reg = SDRAM_INITPLR8;
2988         mfsdram(sdram_reg, sdram_data);
2989         printf("        SDRAM_INITPLR8  = 0x%08X", sdram_data);
2990         sdram_reg = SDRAM_INITPLR9;
2991         mfsdram(sdram_reg, sdram_data);
2992         printf("        SDRAM_INITPLR9  = 0x%08X\n", sdram_data);
2993         sdram_reg = SDRAM_INITPLR10;
2994         mfsdram(sdram_reg, sdram_data);
2995         printf("        SDRAM_INITPLR10 = 0x%08X", sdram_data);
2996         sdram_reg = SDRAM_INITPLR11;
2997         mfsdram(sdram_reg, sdram_data);
2998         printf("        SDRAM_INITPLR11 = 0x%08X\n", sdram_data);
2999         sdram_reg = SDRAM_INITPLR12;
3000         mfsdram(sdram_reg, sdram_data);
3001         printf("        SDRAM_INITPLR12 = 0x%08X", sdram_data);
3002         sdram_reg = SDRAM_INITPLR13;
3003         mfsdram(sdram_reg, sdram_data);
3004         printf("        SDRAM_INITPLR13 = 0x%08X\n", sdram_data);
3005         sdram_reg = SDRAM_INITPLR14;
3006         mfsdram(sdram_reg, sdram_data);
3007         printf("        SDRAM_INITPLR14 = 0x%08X", sdram_data);
3008         sdram_reg = SDRAM_INITPLR15;
3009         mfsdram(sdram_reg, sdram_data);
3010         printf("        SDRAM_INITPLR15 = 0x%08X\n", sdram_data);
3011         sdram_reg = SDRAM_RQDC;
3012         mfsdram(sdram_reg, sdram_data);
3013         printf("        SDRAM_RQDC      = 0x%08X", sdram_data);
3014         sdram_reg = SDRAM_RFDC;
3015         mfsdram(sdram_reg, sdram_data);
3016         printf("        SDRAM_RFDC      = 0x%08X\n", sdram_data);
3017         sdram_reg = SDRAM_RDCC;
3018         mfsdram(sdram_reg, sdram_data);
3019         printf("        SDRAM_RDCC      = 0x%08X", sdram_data);
3020         sdram_reg = SDRAM_DLCR;
3021         mfsdram(sdram_reg, sdram_data);
3022         printf("        SDRAM_DLCR      = 0x%08X\n", sdram_data);
3023         sdram_reg = SDRAM_CLKTR;
3024         mfsdram(sdram_reg, sdram_data);
3025         printf("        SDRAM_CLKTR     = 0x%08X", sdram_data);
3026         sdram_reg = SDRAM_WRDTR;
3027         mfsdram(sdram_reg, sdram_data);
3028         printf("        SDRAM_WRDTR     = 0x%08X\n", sdram_data);
3029         sdram_reg = SDRAM_SDTR1;
3030         mfsdram(sdram_reg, sdram_data);
3031         printf("        SDRAM_SDTR1     = 0x%08X", sdram_data);
3032         sdram_reg = SDRAM_SDTR2;
3033         mfsdram(sdram_reg, sdram_data);
3034         printf("        SDRAM_SDTR2     = 0x%08X\n", sdram_data);
3035         sdram_reg = SDRAM_SDTR3;
3036         mfsdram(sdram_reg, sdram_data);
3037         printf("        SDRAM_SDTR3     = 0x%08X", sdram_data);
3038         sdram_reg = SDRAM_MMODE;
3039         mfsdram(sdram_reg, sdram_data);
3040         printf("        SDRAM_MMODE     = 0x%08X\n", sdram_data);
3041         sdram_reg = SDRAM_MEMODE;
3042         mfsdram(sdram_reg, sdram_data);
3043         printf("        SDRAM_MEMODE    = 0x%08X", sdram_data);
3044         sdram_reg = SDRAM_ECCCR;
3045         mfsdram(sdram_reg, sdram_data);
3046         printf("        SDRAM_ECCCR     = 0x%08X\n\n", sdram_data);
3047
3048         dcr_data = mfdcr(SDRAM_R0BAS);
3049         printf("        MQ0_B0BAS       = 0x%08X", dcr_data);
3050         dcr_data = mfdcr(SDRAM_R1BAS);
3051         printf("        MQ1_B0BAS       = 0x%08X\n", dcr_data);
3052         dcr_data = mfdcr(SDRAM_R2BAS);
3053         printf("        MQ2_B0BAS       = 0x%08X", dcr_data);
3054         dcr_data = mfdcr(SDRAM_R3BAS);
3055         printf("        MQ3_B0BAS       = 0x%08X\n", dcr_data);
3056 }
3057 #else
3058 static void ppc440sp_sdram_register_dump(void)
3059 {
3060 }
3061 #endif
3062 #endif /* CONFIG_SPD_EEPROM */