1 /*-----------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
23 * File Name: enetemac.c
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
49 * - Receive buffer descriptor ring is used to send buffers
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 *-----------------------------------------------------------------------------*
71 * 17-Nov-03 travis.sawyer@sandburst.com
72 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
73 * in the 440GX. This port should work with the 440GP
75 *-----------------------------------------------------------------------------*/
78 #if defined(CONFIG_440) && defined(CONFIG_NET_MULTI)
82 #include <asm/processor.h>
85 #include <440gx_enet.h>
92 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
93 #define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
96 /* Ethernet Transmit and Receive Buffers */
98 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
99 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
101 #define ENET_MAX_MTU PKTSIZE
102 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
105 /* define the number of channels implemented */
106 #define EMAC_RXCHL EMAC_NUM_DEV
107 #define EMAC_TXCHL EMAC_NUM_DEV
109 /*-----------------------------------------------------------------------------+
110 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
111 * Interrupt Controller).
112 *-----------------------------------------------------------------------------*/
113 #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
114 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
115 #define EMAC_UIC_DEF UIC_ENET
119 #define BI_PHYMODE_NONE 0
120 #define BI_PHYMODE_ZMII 1
121 #define BI_PHYMODE_RGMII 2
123 /*-----------------------------------------------------------------------------+
124 * Global variables. TX and RX descriptors and buffers.
125 *-----------------------------------------------------------------------------*/
127 static uint32_t mal_ier;
129 /*-----------------------------------------------------------------------------+
130 * Prototypes and externals.
131 *-----------------------------------------------------------------------------*/
132 static void enet_rcv (struct eth_device *dev, unsigned long malisr);
134 int enetInt (struct eth_device *dev);
135 static void mal_err (struct eth_device *dev, unsigned long isr,
136 unsigned long uic, unsigned long maldef,
137 unsigned long mal_errr);
138 static void emac_err (struct eth_device *dev, unsigned long isr);
140 /*-----------------------------------------------------------------------------+
142 | Disable MAL channel, and EMACn
145 +-----------------------------------------------------------------------------*/
146 static void ppc_440x_eth_halt (struct eth_device *dev)
148 EMAC_440GX_HW_PST hw_p = dev->priv;
149 uint32_t failsafe = 10000;
151 out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
153 /* 1st reset MAL channel */
154 /* Note: writing a 0 to a channel has no effect */
155 mtdcr (maltxcarr, (MAL_CR_MMSR >> hw_p->devnum));
156 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
159 while (mfdcr (maltxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
160 udelay (1000); /* Delay 1 MS so as not to hammer the register */
168 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
170 hw_p->print_speed = 1; /* print speed message again next time */
175 extern int phy_setup_aneg (unsigned char addr);
176 extern int miiphy_reset (unsigned char addr);
178 #if defined (CONFIG_440GX)
179 int ppc_440x_eth_setup_bridge(int devnum, bd_t * bis)
182 unsigned long zmiifer;
183 unsigned long rmiifer;
185 mfsdr(sdr_pfc1, pfc1);
186 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
193 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
194 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
195 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
196 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
197 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
198 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
199 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
200 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
203 zmiifer = ZMII_FER_SMII << ZMII_FER_V(0);
204 zmiifer = ZMII_FER_SMII << ZMII_FER_V(1);
205 zmiifer = ZMII_FER_SMII << ZMII_FER_V(2);
206 zmiifer = ZMII_FER_SMII << ZMII_FER_V(3);
207 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
208 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
209 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
210 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
213 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
214 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
215 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
216 bis->bi_phymode[1] = BI_PHYMODE_NONE;
217 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
218 bis->bi_phymode[3] = BI_PHYMODE_NONE;
221 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
222 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
223 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
224 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
225 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
226 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
227 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
228 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
231 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
232 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
233 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
234 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
235 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
236 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
237 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
238 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
241 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
242 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
243 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
244 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
245 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
246 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
250 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
252 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
253 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
254 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
255 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
259 /* Ensure we setup mdio for this devnum and ONLY this devnum */
260 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
262 out32 (ZMII_FER, zmiifer);
263 out32 (RGMII_FER, rmiifer);
270 static int ppc_440x_eth_init (struct eth_device *dev, bd_t * bis)
276 unsigned long duplex;
277 unsigned long failsafe;
279 unsigned short devnum;
280 unsigned short reg_short;
282 #if defined(CONFIG_440GX)
286 EMAC_440GX_HW_PST hw_p = dev->priv;
288 /* before doing anything, figure out if we have a MAC address */
290 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0)
293 /* Need to get the OPB frequency so we can access the PHY */
294 get_sys_info (&sysinfo);
297 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
299 devnum = hw_p->devnum;
304 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
305 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
306 * is possible that new packets (without relationship with
307 * current transfer) have got the time to arrived before
308 * netloop calls eth_halt
310 printf ("About preceeding transfer (eth%d):\n"
311 "- Sent packet number %d\n"
312 "- Received packet number %d\n"
313 "- Handled packet number %d\n",
316 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
318 hw_p->stats.pkts_tx = 0;
319 hw_p->stats.pkts_rx = 0;
320 hw_p->stats.pkts_handled = 0;
323 /* MAL Channel RESET */
324 /* 1st reset MAL channel */
325 /* Note: writing a 0 to a channel has no effect */
326 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
327 mtdcr (maltxcarr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
329 mtdcr (maltxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
332 mtdcr (malrxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
335 /* TBS: should have udelay and failsafe here */
338 while (mfdcr (maltxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
339 udelay (1000); /* Delay 1 MS so as not to hammer the register */
346 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
347 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
349 hw_p->rx_slot = 0; /* MAL Receive Slot */
350 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
351 hw_p->rx_u_index = 0; /* Receive User Queue Index */
353 hw_p->tx_slot = 0; /* MAL Transmit Slot */
354 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
355 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
358 /* NOTE: 440GX spec states that mode is mutually exclusive */
359 /* NOTE: Therefore, disable all other EMACS, since we handle */
360 /* NOTE: only one emac at a time */
365 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
366 out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
367 #elif defined(CONFIG_440GX)
368 ethgroup = ppc_440x_eth_setup_bridge(devnum, bis);
370 if ((devnum == 0) || (devnum == 1)) {
371 out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
373 else { /* ((devnum == 2) || (devnum == 3)) */
374 out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
375 out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
376 (RGMII_FER_RGMII << RGMII_FER_V (3))));
380 out32 (ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum));
381 __asm__ volatile ("eieio");
383 /* reset emac so we have access to the phy */
385 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
386 __asm__ volatile ("eieio");
389 while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
394 #if defined(CONFIG_440GX)
395 /* Whack the M1 register */
397 mode_reg &= ~0x00000038;
398 if (sysinfo.freqOPB <= 50000000);
399 else if (sysinfo.freqOPB <= 66666667)
400 mode_reg |= EMAC_M1_OBCI_66;
401 else if (sysinfo.freqOPB <= 83333333)
402 mode_reg |= EMAC_M1_OBCI_83;
403 else if (sysinfo.freqOPB <= 100000000)
404 mode_reg |= EMAC_M1_OBCI_100;
406 mode_reg |= EMAC_M1_OBCI_GT100;
408 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
409 #endif /* defined(CONFIG_440GX) */
411 /* wait for PHY to complete auto negotiation */
413 #ifndef CONFIG_CS8952_PHY
416 reg = CONFIG_PHY_ADDR;
419 reg = CONFIG_PHY1_ADDR;
421 #if defined (CONFIG_440GX)
423 reg = CONFIG_PHY2_ADDR;
426 reg = CONFIG_PHY3_ADDR;
430 reg = CONFIG_PHY_ADDR;
434 bis->bi_phynum[devnum] = reg;
436 #ifndef CONFIG_NO_PHY_RESET
438 * Reset the phy, only if its the first time through
439 * otherwise, just check the speeds & feeds
441 if (hw_p->first_init == 0) {
444 #if defined(CONFIG_440GX)
445 #if defined(CONFIG_CIS8201_PHY)
447 * Cicada 8201 PHY needs to have an extended register whacked
450 if ( ((devnum == 2) || (devnum ==3)) && (4 == ethgroup) ) {
451 miiphy_write (reg, 23, 0x1200);
453 * Vitesse VSC8201/Cicada CIS8201 errata:
454 * Interoperability problem with Intel 82547EI phys
455 * This work around (provided by Vitesse) changes
456 * the default timer convergence from 8ms to 12ms
458 miiphy_write (reg, 0x1f, 0x2a30);
459 miiphy_write (reg, 0x08, 0x0200);
460 miiphy_write (reg, 0x1f, 0x52b5);
461 miiphy_write (reg, 0x02, 0x0004);
462 miiphy_write (reg, 0x01, 0x0671);
463 miiphy_write (reg, 0x00, 0x8fae);
464 miiphy_write (reg, 0x1f, 0x2a30);
465 miiphy_write (reg, 0x08, 0x0000);
466 miiphy_write (reg, 0x1f, 0x0000);
467 /* end Vitesse/Cicada errata */
471 /* Start/Restart autonegotiation */
472 phy_setup_aneg (reg);
475 #endif /* CONFIG_NO_PHY_RESET */
477 miiphy_read (reg, PHY_BMSR, ®_short);
480 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
482 if ((reg_short & PHY_BMSR_AUTN_ABLE)
483 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
484 puts ("Waiting for PHY auto negotiation to complete");
486 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
490 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
491 puts (" TIMEOUT !\n");
495 if ((i++ % 1000) == 0) {
498 udelay (1000); /* 1 ms */
499 miiphy_read (reg, PHY_BMSR, ®_short);
503 udelay (500000); /* another 500 ms (results in faster booting) */
506 speed = miiphy_speed (reg);
507 duplex = miiphy_duplex (reg);
509 if (hw_p->print_speed) {
510 hw_p->print_speed = 0;
511 printf ("ENET Speed is %d Mbps - %s duplex connection\n",
512 (int) speed, (duplex == HALF) ? "HALF" : "FULL");
515 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
518 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
520 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
525 /* Set ZMII/RGMII speed according to the phy link speed */
526 reg = in32 (ZMII_SSR);
527 if ( (speed == 100) || (speed == 1000) )
528 out32 (ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum)));
530 out32 (ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum))));
532 if ((devnum == 2) || (devnum == 3)) {
534 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
535 else if (speed == 100)
536 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
538 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
540 out32 (RGMII_SSR, reg);
543 /* set the Mal configuration reg */
544 #if defined(CONFIG_440GX)
545 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
546 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
548 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
549 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
550 if (get_pvr() == PVR_440GP_RB) {
551 mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
555 /* Free "old" buffers */
556 if (hw_p->alloc_tx_buf)
557 free (hw_p->alloc_tx_buf);
558 if (hw_p->alloc_rx_buf)
559 free (hw_p->alloc_rx_buf);
562 * Malloc MAL buffer desciptors, make sure they are
563 * aligned on cache line boundary size
564 * (401/403/IOP480 = 16, 405 = 32)
565 * and doesn't cross cache block boundaries.
568 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
569 ((2 * CFG_CACHELINE_SIZE) - 2));
570 if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
572 (mal_desc_t *) ((int) hw_p->alloc_tx_buf +
575 alloc_tx_buf & CACHELINE_MASK));
577 hw_p->tx = hw_p->alloc_tx_buf;
581 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
582 ((2 * CFG_CACHELINE_SIZE) - 2));
583 if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
585 (mal_desc_t *) ((int) hw_p->alloc_rx_buf +
588 alloc_rx_buf & CACHELINE_MASK));
590 hw_p->rx = hw_p->alloc_rx_buf;
593 for (i = 0; i < NUM_TX_BUFF; i++) {
594 hw_p->tx[i].ctrl = 0;
595 hw_p->tx[i].data_len = 0;
596 if (hw_p->first_init == 0)
598 (char *) malloc (ENET_MAX_MTU_ALIGNED);
599 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
600 if ((NUM_TX_BUFF - 1) == i)
601 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
602 hw_p->tx_run[i] = -1;
604 printf ("TX_BUFF %d @ 0x%08lx\n", i,
605 (ulong) hw_p->tx[i].data_ptr);
609 for (i = 0; i < NUM_RX_BUFF; i++) {
610 hw_p->rx[i].ctrl = 0;
611 hw_p->rx[i].data_len = 0;
612 /* rx[i].data_ptr = (char *) &rx_buff[i]; */
613 hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
614 if ((NUM_RX_BUFF - 1) == i)
615 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
616 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
617 hw_p->rx_ready[i] = -1;
619 printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
625 reg |= dev->enetaddr[0]; /* set high address */
627 reg |= dev->enetaddr[1];
629 out32 (EMAC_IAH + hw_p->hw_addr, reg);
632 reg |= dev->enetaddr[2]; /* set low address */
634 reg |= dev->enetaddr[3];
636 reg |= dev->enetaddr[4];
638 reg |= dev->enetaddr[5];
640 out32 (EMAC_IAL + hw_p->hw_addr, reg);
644 /* setup MAL tx & rx channel pointers */
645 #if defined (CONFIG_440EP) || defined (CONFIG_440GR)
646 mtdcr (maltxctp2r, hw_p->tx);
648 mtdcr (maltxctp1r, hw_p->tx);
650 mtdcr (maltxbattr, 0x0);
651 mtdcr (malrxbattr, 0x0);
652 mtdcr (malrxctp1r, hw_p->rx);
653 /* set RX buffer size */
654 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
656 #if defined (CONFIG_440GX)
658 /* setup MAL tx & rx channel pointers */
659 mtdcr (maltxbattr, 0x0);
660 mtdcr (maltxctp2r, hw_p->tx);
661 mtdcr (malrxbattr, 0x0);
662 mtdcr (malrxctp2r, hw_p->rx);
663 /* set RX buffer size */
664 mtdcr (malrcbs2, ENET_MAX_MTU_ALIGNED / 16);
667 /* setup MAL tx & rx channel pointers */
668 mtdcr (maltxbattr, 0x0);
669 mtdcr (maltxctp3r, hw_p->tx);
670 mtdcr (malrxbattr, 0x0);
671 mtdcr (malrxctp3r, hw_p->rx);
672 /* set RX buffer size */
673 mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16);
675 #endif /* CONFIG_440GX */
678 /* setup MAL tx & rx channel pointers */
679 mtdcr (maltxbattr, 0x0);
680 mtdcr (maltxctp0r, hw_p->tx);
681 mtdcr (malrxbattr, 0x0);
682 mtdcr (malrxctp0r, hw_p->rx);
683 /* set RX buffer size */
684 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
688 /* Enable MAL transmit and receive channels */
689 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
690 mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
692 mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
694 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
696 /* set transmit enable & receive enable */
697 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
699 /* set receive fifo to 4k and tx fifo to 2k */
700 mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
701 mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
704 if (speed == _1000BASET)
705 mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST;
706 else if (speed == _100BASET)
707 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
709 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
711 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
713 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
715 /* Enable broadcast and indvidual address */
716 /* TBS: enabling runts as some misbehaved nics will send runts */
717 out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
719 /* we probably need to set the tx mode1 reg? maybe at tx time */
721 /* set transmit request threshold register */
722 out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
724 /* set receive low/high water mark register */
725 /* 440GP has a 64 byte burst length */
726 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
727 out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
729 /* Set fifo limit entry in tx mode 0 */
730 out32 (EMAC_TXM0 + hw_p->hw_addr, 0x00000003);
732 out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
735 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS |
736 EMAC_ISR_PTLE | EMAC_ISR_ORE | EMAC_ISR_IRE;
737 if (speed == _100BASET)
738 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
740 out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
741 out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
743 if (hw_p->first_init == 0) {
745 * Connect interrupt service routines
747 irq_install_handler (VECNUM_EWU0 + (hw_p->devnum * 2),
748 (interrupt_handler_t *) enetInt, dev);
749 irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
750 (interrupt_handler_t *) enetInt, dev);
753 mtmsr (msr); /* enable interrupts again */
756 hw_p->first_init = 1;
762 static int ppc_440x_eth_send (struct eth_device *dev, volatile void *ptr,
765 struct enet_frame *ef_ptr;
766 ulong time_start, time_now;
767 unsigned long temp_txm0;
768 EMAC_440GX_HW_PST hw_p = dev->priv;
770 ef_ptr = (struct enet_frame *) ptr;
772 /*-----------------------------------------------------------------------+
773 * Copy in our address into the frame.
774 *-----------------------------------------------------------------------*/
775 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
777 /*-----------------------------------------------------------------------+
778 * If frame is too long or too short, modify length.
779 *-----------------------------------------------------------------------*/
780 /* TBS: where does the fragment go???? */
781 if (len > ENET_MAX_MTU)
784 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
785 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
787 /*-----------------------------------------------------------------------+
788 * set TX Buffer busy, and send it
789 *-----------------------------------------------------------------------*/
790 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
791 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
792 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
793 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
794 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
796 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
797 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
799 __asm__ volatile ("eieio");
801 out32 (EMAC_TXM0 + hw_p->hw_addr,
802 in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
804 hw_p->stats.pkts_tx++;
807 /*-----------------------------------------------------------------------+
808 * poll unitl the packet is sent and then make sure it is OK
809 *-----------------------------------------------------------------------*/
810 time_start = get_timer (0);
812 temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr);
813 /* loop until either TINT turns on or 3 seconds elapse */
814 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
815 /* transmit is done, so now check for errors
816 * If there is an error, an interrupt should
817 * happen when we return
819 time_now = get_timer (0);
820 if ((time_now - time_start) > 3000) {
830 int enetInt (struct eth_device *dev)
833 int rc = -1; /* default to not us */
834 unsigned long mal_isr;
835 unsigned long emac_isr = 0;
836 unsigned long mal_rx_eob;
837 unsigned long my_uic0msr, my_uic1msr;
839 #if defined(CONFIG_440GX)
840 unsigned long my_uic2msr;
842 EMAC_440GX_HW_PST hw_p;
845 * Because the mal is generic, we need to get the current
848 dev = eth_get_dev ();
853 /* enter loop that stays in interrupt code until nothing to service */
857 my_uic0msr = mfdcr (uic0msr);
858 my_uic1msr = mfdcr (uic1msr);
859 #if defined(CONFIG_440GX)
860 my_uic2msr = mfdcr (uic2msr);
862 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
864 (UIC_ETH0 | UIC_ETH1 | UIC_MS | UIC_MTDE |
869 #if defined (CONFIG_440GX)
870 if (!(my_uic0msr & (UIC_MRE | UIC_MTE))
871 && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) {
876 /* get and clear controller status interrupts */
877 /* look at Mal and EMAC interrupts */
878 if ((my_uic0msr & (UIC_MRE | UIC_MTE))
879 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
880 /* we have a MAL interrupt */
881 mal_isr = mfdcr (malesr);
882 /* look for mal error */
883 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
884 mal_err (dev, mal_isr, my_uic0msr,
885 MAL_UIC_DEF, MAL_UIC_ERR);
891 /* port by port dispatch of emac interrupts */
892 if (hw_p->devnum == 0) {
893 if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */
894 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
895 if ((hw_p->emac_ier & emac_isr) != 0) {
896 emac_err (dev, emac_isr);
901 if ((hw_p->emac_ier & emac_isr)
902 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
903 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
904 mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
905 return (rc); /* we had errors so get out */
909 if (hw_p->devnum == 1) {
910 if (UIC_ETH1 & my_uic1msr) { /* look for EMAC errors */
911 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
912 if ((hw_p->emac_ier & emac_isr) != 0) {
913 emac_err (dev, emac_isr);
918 if ((hw_p->emac_ier & emac_isr)
919 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
920 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
921 mtdcr (uic1sr, UIC_ETH1 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
922 return (rc); /* we had errors so get out */
925 #if defined (CONFIG_440GX)
926 if (hw_p->devnum == 2) {
927 if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */
928 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
929 if ((hw_p->emac_ier & emac_isr) != 0) {
930 emac_err (dev, emac_isr);
935 if ((hw_p->emac_ier & emac_isr)
936 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
937 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
938 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
939 mtdcr (uic2sr, UIC_ETH2);
940 return (rc); /* we had errors so get out */
944 if (hw_p->devnum == 3) {
945 if (UIC_ETH3 & my_uic2msr) { /* look for EMAC errors */
946 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
947 if ((hw_p->emac_ier & emac_isr) != 0) {
948 emac_err (dev, emac_isr);
953 if ((hw_p->emac_ier & emac_isr)
954 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
955 mtdcr (uic0sr, UIC_MRE | UIC_MTE); /* Clear */
956 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
957 mtdcr (uic2sr, UIC_ETH3);
958 return (rc); /* we had errors so get out */
961 #endif /* CONFIG_440GX */
962 /* handle MAX TX EOB interrupt from a tx */
963 if (my_uic0msr & UIC_MTE) {
964 mal_rx_eob = mfdcr (maltxeobisr);
965 mtdcr (maltxeobisr, mal_rx_eob);
966 mtdcr (uic0sr, UIC_MTE);
968 /* handle MAL RX EOB interupt from a receive */
969 /* check for EOB on valid channels */
970 if (my_uic0msr & UIC_MRE) {
971 mal_rx_eob = mfdcr (malrxeobisr);
972 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
974 mtdcr(malrxeobisr, mal_rx_eob); */
975 enet_rcv (dev, emac_isr);
976 /* indicate that we serviced an interrupt */
981 mtdcr (uic0sr, UIC_MRE); /* Clear */
982 mtdcr (uic1sr, UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
983 switch (hw_p->devnum) {
985 mtdcr (uic1sr, UIC_ETH0);
988 mtdcr (uic1sr, UIC_ETH1);
990 #if defined (CONFIG_440GX)
992 mtdcr (uic2sr, UIC_ETH2);
995 mtdcr (uic2sr, UIC_ETH3);
997 #endif /* CONFIG_440GX */
1006 /*-----------------------------------------------------------------------------+
1008 *-----------------------------------------------------------------------------*/
1009 static void mal_err (struct eth_device *dev, unsigned long isr,
1010 unsigned long uic, unsigned long maldef,
1011 unsigned long mal_errr)
1013 EMAC_440GX_HW_PST hw_p = dev->priv;
1015 mtdcr (malesr, isr); /* clear interrupt */
1017 /* clear DE interrupt */
1018 mtdcr (maltxdeir, 0xC0000000);
1019 mtdcr (malrxdeir, 0x80000000);
1021 #ifdef INFO_440_ENET
1022 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
1025 eth_init (hw_p->bis); /* start again... */
1028 /*-----------------------------------------------------------------------------+
1029 * EMAC Error Routine
1030 *-----------------------------------------------------------------------------*/
1031 static void emac_err (struct eth_device *dev, unsigned long isr)
1033 EMAC_440GX_HW_PST hw_p = dev->priv;
1035 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
1036 out32 (EMAC_ISR + hw_p->hw_addr, isr);
1039 /*-----------------------------------------------------------------------------+
1040 * enet_rcv() handles the ethernet receive data
1041 *-----------------------------------------------------------------------------*/
1042 static void enet_rcv (struct eth_device *dev, unsigned long malisr)
1044 struct enet_frame *ef_ptr;
1045 unsigned long data_len;
1046 unsigned long rx_eob_isr;
1047 EMAC_440GX_HW_PST hw_p = dev->priv;
1053 rx_eob_isr = mfdcr (malrxeobisr);
1054 if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
1056 mtdcr (malrxeobisr, rx_eob_isr);
1059 while (1) { /* do all */
1062 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
1063 || (loop_count >= NUM_RX_BUFF))
1067 if (NUM_RX_BUFF == hw_p->rx_slot)
1070 data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
1072 if (data_len > ENET_MAX_MTU) /* Check len */
1075 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
1077 hw_p->stats.rx_err_log[hw_p->
1080 hw_p->rx_err_index++;
1081 if (hw_p->rx_err_index ==
1083 hw_p->rx_err_index =
1086 } /* data_len < max mtu */
1088 if (!data_len) { /* no data */
1089 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
1091 hw_p->stats.data_len_err++; /* Error at Rx */
1096 /* Check if user has already eaten buffer */
1097 /* if not => ERROR */
1098 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
1099 if (hw_p->is_receiving)
1100 printf ("ERROR : Receive buffers are full!\n");
1103 hw_p->stats.rx_frames++;
1104 hw_p->stats.rx += data_len;
1105 ef_ptr = (struct enet_frame *) hw_p->rx[i].
1107 #ifdef INFO_440_ENET
1108 hw_p->stats.pkts_rx++;
1113 hw_p->rx_ready[hw_p->rx_i_index] = i;
1115 if (NUM_RX_BUFF == hw_p->rx_i_index)
1116 hw_p->rx_i_index = 0;
1118 /* printf("X"); /|* test-only *|/ */
1121 * free receive buffer only when
1122 * buffer has been handled (eth_rx)
1123 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1127 } /* if EMACK_RXCHL */
1131 static int ppc_440x_eth_rx (struct eth_device *dev)
1136 EMAC_440GX_HW_PST hw_p = dev->priv;
1138 hw_p->is_receiving = 1; /* tell driver */
1142 * use ring buffer and
1143 * get index from rx buffer desciptor queue
1145 user_index = hw_p->rx_ready[hw_p->rx_u_index];
1146 if (user_index == -1) {
1148 break; /* nothing received - leave for() loop */
1152 mtmsr (msr & ~(MSR_EE));
1154 length = hw_p->rx[user_index].data_len;
1156 /* Pass the packet up to the protocol layers. */
1157 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1158 /* NetReceive(NetRxPackets[i], length); */
1159 NetReceive (NetRxPackets[user_index], length - 4);
1160 /* Free Recv Buffer */
1161 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
1162 /* Free rx buffer descriptor queue */
1163 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1165 if (NUM_RX_BUFF == hw_p->rx_u_index)
1166 hw_p->rx_u_index = 0;
1168 #ifdef INFO_440_ENET
1169 hw_p->stats.pkts_handled++;
1172 mtmsr (msr); /* Enable IRQ's */
1175 hw_p->is_receiving = 0; /* tell driver */
1180 int ppc_440x_eth_initialize (bd_t * bis)
1182 static int virgin = 0;
1183 struct eth_device *dev;
1185 EMAC_440GX_HW_PST hw = NULL;
1187 #if defined(CONFIG_440GX)
1190 mfsdr (sdr_pfc1, pfc1);
1191 pfc1 &= ~(0x01e00000);
1193 mtsdr (sdr_pfc1, pfc1);
1195 /* set phy num and mode */
1196 bis->bi_phynum[0] = CONFIG_PHY_ADDR;
1197 #if defined(CONFIG_PHY1_ADDR)
1198 bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
1200 #if defined(CONFIG_440GX)
1201 bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
1202 bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
1203 bis->bi_phymode[0] = 0;
1204 bis->bi_phymode[1] = 0;
1205 bis->bi_phymode[2] = 2;
1206 bis->bi_phymode[3] = 2;
1208 #if defined (CONFIG_440GX)
1209 ppc_440x_eth_setup_bridge(0, bis);
1213 for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) {
1215 /* See if we can actually bring up the interface, otherwise, skip it */
1217 default: /* fall through */
1219 if (memcmp (bis->bi_enetaddr, "\0\0\0\0\0\0", 6) == 0) {
1220 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1224 #ifdef CONFIG_HAS_ETH1
1226 if (memcmp (bis->bi_enet1addr, "\0\0\0\0\0\0", 6) == 0) {
1227 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1232 #ifdef CONFIG_HAS_ETH2
1234 if (memcmp (bis->bi_enet2addr, "\0\0\0\0\0\0", 6) == 0) {
1235 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1240 #ifdef CONFIG_HAS_ETH3
1242 if (memcmp (bis->bi_enet3addr, "\0\0\0\0\0\0", 6) == 0) {
1243 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1250 /* Allocate device structure */
1251 dev = (struct eth_device *) malloc (sizeof (*dev));
1253 printf ("ppc_440x_eth_initialize: "
1254 "Cannot allocate eth_device %d\n", eth_num);
1257 memset(dev, 0, sizeof(*dev));
1259 /* Allocate our private use data */
1260 hw = (EMAC_440GX_HW_PST) malloc (sizeof (*hw));
1262 printf ("ppc_440x_eth_initialize: "
1263 "Cannot allocate private hw data for eth_device %d",
1268 memset(hw, 0, sizeof(*hw));
1271 default: /* fall through */
1274 memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
1276 #ifdef CONFIG_HAS_ETH1
1278 hw->hw_addr = 0x100;
1279 memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
1282 #ifdef CONFIG_HAS_ETH2
1284 hw->hw_addr = 0x400;
1285 memcpy (dev->enetaddr, bis->bi_enet2addr, 6);
1288 #ifdef CONFIG_HAS_ETH3
1290 hw->hw_addr = 0x600;
1291 memcpy (dev->enetaddr, bis->bi_enet3addr, 6);
1296 hw->devnum = eth_num;
1297 hw->print_speed = 1;
1299 sprintf (dev->name, "ppc_440x_eth%d", eth_num);
1300 dev->priv = (void *) hw;
1301 dev->init = ppc_440x_eth_init;
1302 dev->halt = ppc_440x_eth_halt;
1303 dev->send = ppc_440x_eth_send;
1304 dev->recv = ppc_440x_eth_rx;
1307 /* set the MAL IER ??? names may change with new spec ??? */
1309 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
1310 MAL_IER_OPBE | MAL_IER_PLBE;
1311 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
1312 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
1313 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
1314 mtdcr (malier, mal_ier);
1316 /* install MAL interrupt handler */
1317 irq_install_handler (VECNUM_MS,
1318 (interrupt_handler_t *) enetInt,
1320 irq_install_handler (VECNUM_MTE,
1321 (interrupt_handler_t *) enetInt,
1323 irq_install_handler (VECNUM_MRE,
1324 (interrupt_handler_t *) enetInt,
1326 irq_install_handler (VECNUM_TXDE,
1327 (interrupt_handler_t *) enetInt,
1329 irq_install_handler (VECNUM_RXDE,
1330 (interrupt_handler_t *) enetInt,
1337 } /* end for each supported device */
1340 #endif /* CONFIG_440 && CONFIG_NET_MULTI */