1 /*-----------------------------------------------------------------------------+
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-----------------------------------------------------------------------------*/
21 /*-----------------------------------------------------------------------------+
23 * File Name: enetemac.c
25 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
31 * Date Description of Change BY
32 * --------- --------------------- ---
33 * 05-May-99 Created MKW
34 * 27-Jun-99 Clean up JWB
35 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
36 * 29-Jul-99 Added Full duplex support MKW
37 * 06-Aug-99 Changed names for Mal CR reg MKW
38 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
39 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
40 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
41 * to avoid chaining maximum sized packets. Push starting
42 * RX descriptor address up to the next cache line boundary.
43 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
44 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
45 * EMAC_RXM register. JWB
46 * 12-Mar-01 anne-sophie.harnois@nextream.fr
47 * - Variables are compatible with those already defined in
49 * - Receive buffer descriptor ring is used to send buffers
51 * - Info print about send/received/handled packet number if
52 * INFO_405_ENET is set
53 * 17-Apr-01 stefan.roese@esd-electronics.com
54 * - MAL reset in "eth_halt" included
55 * - Enet speed and duplex output now in one line
56 * 08-May-01 stefan.roese@esd-electronics.com
57 * - MAL error handling added (eth_init called again)
58 * 13-Nov-01 stefan.roese@esd-electronics.com
59 * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
60 * 04-Jan-02 stefan.roese@esd-electronics.com
61 * - Wait for PHY auto negotiation to complete added
62 * 06-Feb-02 stefan.roese@esd-electronics.com
63 * - Bug fixed in waiting for auto negotiation to complete
64 * 26-Feb-02 stefan.roese@esd-electronics.com
65 * - rx and tx buffer descriptors now allocated (no fixed address
67 * 17-Jun-02 stefan.roese@esd-electronics.com
68 * - MAL error debug printf 'M' removed (rx de interrupt may
69 * occur upon many incoming packets with only 4 rx buffers).
70 * 21-Nov-03 pavel.bartusek@sysgo.com
71 * - set ZMII bridge speed on 440
73 *-----------------------------------------------------------------------------*/
76 #include <asm/processor.h>
79 #include <405gp_enet.h>
86 #if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \
87 ( defined(CONFIG_440) && !defined(CONFIG_NET_MULTI))
89 #if !defined(CONFIG_NET_MULTI) || !defined(CONFIG_405EP)
90 /* 405GP, 440 with !CONFIG_NET_MULTI. For 440 only EMAC0 is supported */
91 #define EMAC_NUM_DEV 1
93 /* 440EP && CONFIG_NET_MULTI */
94 #define EMAC_NUM_DEV 2
97 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
98 #define PHY_AUTONEGOTIATE_TIMEOUT 4000 /* 4000 ms autonegotiate timeout */
100 /* Ethernet Transmit and Receive Buffers */
102 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
103 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
105 #define ENET_MAX_MTU PKTSIZE
106 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
108 /* define the number of channels implemented */
109 #define EMAC_RXCHL EMAC_NUM_DEV
110 #define EMAC_TXCHL EMAC_NUM_DEV
112 /*-----------------------------------------------------------------------------+
113 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
114 * Interrupt Controller).
115 *-----------------------------------------------------------------------------*/
116 #define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
117 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
118 #define EMAC_UIC_DEF UIC_ENET
119 #define EMAC_UIC_DEF1 UIC_ENET1
120 #define SEL_UIC_DEF(p) (p ? UIC_ENET1 : UIC_ENET )
123 /*-----------------------------------------------------------------------------+
124 * Global variables. TX and RX descriptors and buffers.
125 *-----------------------------------------------------------------------------*/
127 static uint32_t mal_ier;
129 #if !defined(CONFIG_NET_MULTI)
130 struct eth_device *emac0_dev;
133 /*-----------------------------------------------------------------------------+
134 * Prototypes and externals.
135 *-----------------------------------------------------------------------------*/
136 static void enet_rcv (struct eth_device *dev, unsigned long malisr);
138 int enetInt (struct eth_device *dev);
139 static void mal_err (struct eth_device *dev, unsigned long isr,
140 unsigned long uic, unsigned long maldef,
141 unsigned long mal_errr);
142 static void emac_err (struct eth_device *dev, unsigned long isr);
144 /*-----------------------------------------------------------------------------+
146 | Disable MAL channel, and EMACn
149 +-----------------------------------------------------------------------------*/
150 static void ppc_4xx_eth_halt (struct eth_device *dev)
152 EMAC_405_HW_PST hw_p = dev->priv;
153 uint32_t failsafe = 10000;
155 mtdcr (malier, 0x00000000); /* disable mal interrupts */
156 out32 (EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
158 /* 1st reset MAL channel */
159 /* Note: writing a 0 to a channel has no effect */
160 mtdcr (maltxcarr, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
161 mtdcr (malrxcarr, (MAL_CR_MMSR >> hw_p->devnum));
164 while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
165 udelay (1000); /* Delay 1 MS so as not to hammer the register */
173 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
175 hw_p->print_speed = 1; /* print speed message again next time */
180 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
186 unsigned long duplex;
187 unsigned long failsafe;
189 unsigned short devnum;
190 unsigned short reg_short;
192 EMAC_405_HW_PST hw_p = dev->priv;
193 /* before doing anything, figure out if we have a MAC address */
195 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0)
199 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
201 devnum = hw_p->devnum;
206 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
207 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
208 * is possible that new packets (without relationship with
209 * current transfer) have got the time to arrived before
210 * netloop calls eth_halt
212 printf ("About preceeding transfer (eth%d):\n"
213 "- Sent packet number %d\n"
214 "- Received packet number %d\n"
215 "- Handled packet number %d\n",
218 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
220 hw_p->stats.pkts_tx = 0;
221 hw_p->stats.pkts_rx = 0;
222 hw_p->stats.pkts_handled = 0;
226 mtdcr (malmcr, MAL_CR_MMSR);
228 while (mfdcr (malmcr) & MAL_CR_MMSR) {
230 #if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
234 out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
235 #elif defined(CONFIG_440)
237 out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
238 #endif /* CONFIG_440 */
240 /* MAL Channel RESET */
241 /* 1st reset MAL channel */
242 /* Note: writing a 0 to a channel has no effect */
243 mtdcr (maltxcarr, (MAL_TXRX_CASR >> (hw_p->devnum * 2)));
244 mtdcr (malrxcarr, (MAL_TXRX_CASR >> hw_p->devnum));
247 /* TBS: should have udelay and failsafe here */
250 while (mfdcr (malrxcasr) & (MAL_CR_MMSR >> hw_p->devnum)) {
251 udelay (1000); /* Delay 1 MS so as not to hammer the register */
258 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
259 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
261 hw_p->rx_slot = 0; /* MAL Receive Slot */
262 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
263 hw_p->rx_u_index = 0; /* Receive User Queue Index */
265 hw_p->tx_slot = 0; /* MAL Transmit Slot */
266 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
267 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
269 __asm__ volatile ("eieio");
271 /* reset emac so we have access to the phy */
273 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST);
274 __asm__ volatile ("eieio");
277 while ((in32 (EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) {
282 #if defined(CONFIG_NET_MULTI)
283 reg = hw_p->devnum ? CONFIG_PHY1_ADDR : CONFIG_PHY_ADDR;
285 reg = CONFIG_PHY_ADDR;
287 /* wait for PHY to complete auto negotiation */
289 #ifndef CONFIG_CS8952_PHY
290 miiphy_read (reg, PHY_BMSR, ®_short);
293 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
295 if ((reg_short & PHY_BMSR_AUTN_ABLE)
296 && !(reg_short & PHY_BMSR_AUTN_COMP)) {
297 puts ("Waiting for PHY auto negotiation to complete");
299 while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
303 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
304 puts (" TIMEOUT !\n");
308 if ((i++ % 1000) == 0) {
311 udelay (1000); /* 1 ms */
312 miiphy_read (reg, PHY_BMSR, ®_short);
315 udelay (500000); /* another 500 ms (results in faster booting) */
318 speed = miiphy_speed (reg);
319 duplex = miiphy_duplex (reg);
321 if (hw_p->print_speed) {
322 hw_p->print_speed = 0;
323 printf ("ENET Speed is %d Mbps - %s duplex connection\n",
324 (int) speed, (duplex == HALF) ? "HALF" : "FULL");
327 #if defined(CONFIG_440)
328 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
329 if( get_pvr() == PVR_440GP_RB)
330 mtdcr (malmcr, MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
333 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
336 /* Free "old" buffers */
337 if (hw_p->alloc_tx_buf)
338 free (hw_p->alloc_tx_buf);
339 if (hw_p->alloc_rx_buf)
340 free (hw_p->alloc_rx_buf);
343 * Malloc MAL buffer desciptors, make sure they are
344 * aligned on cache line boundary size
345 * (401/403/IOP480 = 16, 405 = 32)
346 * and doesn't cross cache block boundaries.
349 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_TX_BUFF) +
350 ((2 * CFG_CACHELINE_SIZE) - 2));
351 if (((int) hw_p->alloc_tx_buf & CACHELINE_MASK) != 0) {
353 (mal_desc_t *) ((int) hw_p->alloc_tx_buf +
356 alloc_tx_buf & CACHELINE_MASK));
358 hw_p->tx = hw_p->alloc_tx_buf;
362 (mal_desc_t *) malloc ((sizeof (mal_desc_t) * NUM_RX_BUFF) +
363 ((2 * CFG_CACHELINE_SIZE) - 2));
364 if (((int) hw_p->alloc_rx_buf & CACHELINE_MASK) != 0) {
366 (mal_desc_t *) ((int) hw_p->alloc_rx_buf +
369 alloc_rx_buf & CACHELINE_MASK));
371 hw_p->rx = hw_p->alloc_rx_buf;
374 for (i = 0; i < NUM_TX_BUFF; i++) {
375 hw_p->tx[i].ctrl = 0;
376 hw_p->tx[i].data_len = 0;
377 if (hw_p->first_init == 0)
379 (char *) malloc (ENET_MAX_MTU_ALIGNED);
380 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
381 if ((NUM_TX_BUFF - 1) == i)
382 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
383 hw_p->tx_run[i] = -1;
385 printf ("TX_BUFF %d @ 0x%08lx\n", i,
386 (ulong) hw_p->tx[i].data_ptr);
390 for (i = 0; i < NUM_RX_BUFF; i++) {
391 hw_p->rx[i].ctrl = 0;
392 hw_p->rx[i].data_len = 0;
393 /* rx[i].data_ptr = (char *) &rx_buff[i]; */
394 hw_p->rx[i].data_ptr = (char *) NetRxPackets[i];
395 if ((NUM_RX_BUFF - 1) == i)
396 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
397 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
398 hw_p->rx_ready[i] = -1;
400 printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
405 reg |= dev->enetaddr[0]; /* set high address */
407 reg |= dev->enetaddr[1];
409 out32 (EMAC_IAH + hw_p->hw_addr, reg);
412 reg |= dev->enetaddr[2]; /* set low address */
414 reg |= dev->enetaddr[3];
416 reg |= dev->enetaddr[4];
418 reg |= dev->enetaddr[5];
420 out32 (EMAC_IAL + hw_p->hw_addr, reg);
422 #if defined(CONFIG_NET_MULTI)
424 /* setup MAL tx & rx channel pointers */
425 /* For 405EP, the EMAC1 tx channel 0 is MAL tx channel 2 */
426 mtdcr (maltxctp2r, hw_p->tx);
427 mtdcr (malrxctp1r, hw_p->rx);
428 /* set RX buffer size */
429 mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16);
434 /* setup MAL tx & rx channel pointers */
435 mtdcr (maltxctp0r, hw_p->tx);
436 mtdcr (malrxctp0r, hw_p->rx);
437 /* set RX buffer size */
438 mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
442 /* Enable MAL transmit and receive channels */
443 mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum * 2)));
444 mtdcr (malrxcasr, (MAL_TXRX_CASR >> hw_p->devnum));
446 /* set transmit enable & receive enable */
447 out32 (EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
449 /* set receive fifo to 4k and tx fifo to 2k */
450 mode_reg = in32 (EMAC_M1 + hw_p->hw_addr);
451 mode_reg |= EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
454 if (speed == _100BASET)
455 mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
457 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
459 mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
461 out32 (EMAC_M1 + hw_p->hw_addr, mode_reg);
463 #if defined(CONFIG_440)
464 /* set speed in the ZMII bridge */
465 if (speed == _100BASET)
466 out32(ZMII_SSR, in32(ZMII_SSR) | 0x10000000);
468 out32(ZMII_SSR, in32(ZMII_SSR) & ~0x10000000);
469 #if defined(CONFIG_440_EP) || defined(CONFIG_440_GR)
472 if (speed == _100BASET) {
473 out32(ZMII_SSR, in32(ZMII_SSR) | 0x10000000);
474 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
476 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
477 out32(ZMII_SSR, in32(ZMII_SSR) & ~0x10000000);
483 /* Enable broadcast and indvidual address */
484 /* TBS: enabling runts as some misbehaved nics will send runts */
485 out32 (EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
487 /* we probably need to set the tx mode1 reg? maybe at tx time */
489 /* set transmit request threshold register */
490 out32 (EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
492 #if defined(CONFIG_440)
493 /* 440GP has a 64 byte burst length */
494 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
495 out32 (EMAC_TXM1 + hw_p->hw_addr, 0xf8640000);
497 /* 405s have a 16 byte burst length */
498 out32 (EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
503 out32 (EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
506 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS |
507 EMAC_ISR_ORE | EMAC_ISR_IRE;
508 if (speed == _100BASET)
509 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
511 out32 (EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
512 out32 (EMAC_IER + hw_p->hw_addr, hw_p->emac_ier);
514 if (hw_p->first_init == 0) {
516 * Connect interrupt service routines
518 irq_install_handler (VECNUM_ETH0 + (hw_p->devnum * 2),
519 (interrupt_handler_t *) enetInt, dev);
522 mtmsr (msr); /* enable interrupts again */
525 hw_p->first_init = 1;
531 static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, int len)
533 struct enet_frame *ef_ptr;
534 ulong time_start, time_now;
535 unsigned long temp_txm0;
536 EMAC_405_HW_PST hw_p = dev->priv;
538 ef_ptr = (struct enet_frame *) ptr;
540 /*-----------------------------------------------------------------------+
541 * Copy in our address into the frame.
542 *-----------------------------------------------------------------------*/
543 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
545 /*-----------------------------------------------------------------------+
546 * If frame is too long or too short, modify length.
547 *-----------------------------------------------------------------------*/
548 /* TBS: where does the fragment go???? */
549 if (len > ENET_MAX_MTU)
552 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
553 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
555 /*-----------------------------------------------------------------------+
556 * set TX Buffer busy, and send it
557 *-----------------------------------------------------------------------*/
558 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
559 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
560 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
561 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
562 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
564 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
565 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
567 __asm__ volatile ("eieio");
569 out32 (EMAC_TXM0 + hw_p->hw_addr,
570 in32 (EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0);
572 hw_p->stats.pkts_tx++;
575 /*-----------------------------------------------------------------------+
576 * poll unitl the packet is sent and then make sure it is OK
577 *-----------------------------------------------------------------------*/
578 time_start = get_timer (0);
580 temp_txm0 = in32 (EMAC_TXM0 + hw_p->hw_addr);
581 /* loop until either TINT turns on or 3 seconds elapse */
582 if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
583 /* transmit is done, so now check for errors
584 * If there is an error, an interrupt should
585 * happen when we return
587 time_now = get_timer (0);
588 if ((time_now - time_start) > 3000) {
597 #if defined(CONFIG_440)
598 int enetInt (struct eth_device *dev)
601 int rc = -1; /* default to not us */
602 unsigned long mal_isr;
603 unsigned long emac_isr = 0;
604 unsigned long mal_rx_eob;
605 unsigned long my_uic0msr, my_uic1msr;
606 EMAC_405_HW_PST hw_p;
609 * Because the mal is generic, we need to get the current
612 #if defined(CONFIG_NET_MULTI)
619 /* enter loop that stays in interrupt code until nothing to service */
623 my_uic0msr = mfdcr (uic0msr);
624 my_uic1msr = mfdcr (uic1msr);
626 if (!(my_uic0msr & UIC_MRE)
627 && !(my_uic1msr & (UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
632 /* get and clear controller status interrupts */
633 /* look at Mal and EMAC interrupts */
634 if ((my_uic0msr & UIC_MRE)
635 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
636 /* we have a MAL interrupt */
637 mal_isr = mfdcr (malesr);
638 /* look for mal error */
639 if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
640 mal_err (dev, mal_isr, my_uic0msr, MAL_UIC_DEF, MAL_UIC_ERR);
645 if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */
646 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
647 if ((hw_p->emac_ier & emac_isr) != 0) {
648 emac_err (dev, emac_isr);
653 if ((hw_p->emac_ier & emac_isr)
654 || (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
655 mtdcr (uic0sr, UIC_MRE); /* Clear */
656 mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
657 return (rc); /* we had errors so get out */
660 /* handle MAL RX EOB interupt from a receive */
661 /* check for EOB on valid channels */
662 if (my_uic0msr & UIC_MRE) {
663 mal_rx_eob = mfdcr (malrxeobisr);
664 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel 0 */
666 mtdcr(malrxeobisr, mal_rx_eob); */
667 enet_rcv (dev, emac_isr);
668 /* indicate that we serviced an interrupt */
673 mtdcr (uic0sr, UIC_MRE); /* Clear */
674 mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
680 #else /* CONFIG_440 */
682 int enetInt (struct eth_device *dev)
685 int rc = -1; /* default to not us */
686 unsigned long mal_isr;
687 unsigned long emac_isr = 0;
688 unsigned long mal_rx_eob;
689 unsigned long my_uicmsr;
691 EMAC_405_HW_PST hw_p;
694 * Because the mal is generic, we need to get the current
697 #if defined(CONFIG_NET_MULTI)
705 /* enter loop that stays in interrupt code until nothing to service */
709 my_uicmsr = mfdcr (uicmsr);
711 if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
714 /* get and clear controller status interrupts */
715 /* look at Mal and EMAC interrupts */
716 if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
717 mal_isr = mfdcr (malesr);
718 /* look for mal error */
719 if ((my_uicmsr & MAL_UIC_ERR) != 0) {
720 mal_err (dev, mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
726 /* port by port dispatch of emac interrupts */
728 if ((SEL_UIC_DEF(hw_p->devnum) & my_uicmsr) != 0) { /* look for EMAC errors */
729 emac_isr = in32 (EMAC_ISR + hw_p->hw_addr);
730 if ((hw_p->emac_ier & emac_isr) != 0) {
731 emac_err (dev, emac_isr);
736 if (((hw_p->emac_ier & emac_isr) != 0) || ((MAL_UIC_ERR & my_uicmsr) != 0)) {
737 mtdcr (uicsr, MAL_UIC_DEF | SEL_UIC_DEF(hw_p->devnum)); /* Clear */
738 return (rc); /* we had errors so get out */
741 /* handle MAX TX EOB interrupt from a tx */
742 if (my_uicmsr & UIC_MAL_TXEOB) {
743 mal_rx_eob = mfdcr (maltxeobisr);
744 mtdcr (maltxeobisr, mal_rx_eob);
745 mtdcr (uicsr, UIC_MAL_TXEOB);
747 /* handle MAL RX EOB interupt from a receive */
748 /* check for EOB on valid channels */
749 if (my_uicmsr & UIC_MAL_RXEOB)
751 mal_rx_eob = mfdcr (malrxeobisr);
752 if ((mal_rx_eob & (0x80000000 >> hw_p->devnum)) != 0) { /* call emac routine for channel x */
754 mtdcr(malrxeobisr, mal_rx_eob); */
755 enet_rcv (dev, emac_isr);
756 /* indicate that we serviced an interrupt */
761 mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */
768 /*-----------------------------------------------------------------------------+
770 *-----------------------------------------------------------------------------*/
771 static void mal_err (struct eth_device *dev, unsigned long isr,
772 unsigned long uic, unsigned long maldef,
773 unsigned long mal_errr)
775 EMAC_405_HW_PST hw_p = dev->priv;
777 mtdcr (malesr, isr); /* clear interrupt */
779 /* clear DE interrupt */
780 mtdcr (maltxdeir, 0xC0000000);
781 mtdcr (malrxdeir, 0x80000000);
784 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
787 eth_init (hw_p->bis); /* start again... */
790 /*-----------------------------------------------------------------------------+
792 *-----------------------------------------------------------------------------*/
793 static void emac_err (struct eth_device *dev, unsigned long isr)
795 EMAC_405_HW_PST hw_p = dev->priv;
797 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
798 out32 (EMAC_ISR + hw_p->hw_addr, isr);
801 /*-----------------------------------------------------------------------------+
802 * enet_rcv() handles the ethernet receive data
803 *-----------------------------------------------------------------------------*/
804 static void enet_rcv (struct eth_device *dev, unsigned long malisr)
806 struct enet_frame *ef_ptr;
807 unsigned long data_len;
808 unsigned long rx_eob_isr;
809 EMAC_405_HW_PST hw_p = dev->priv;
815 rx_eob_isr = mfdcr (malrxeobisr);
816 if ((0x80000000 >> hw_p->devnum) & rx_eob_isr) {
818 mtdcr (malrxeobisr, rx_eob_isr);
821 while (1) { /* do all */
824 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
825 || (loop_count >= NUM_RX_BUFF))
829 if (NUM_RX_BUFF == hw_p->rx_slot)
832 data_len = (unsigned long) hw_p->rx[i].data_len; /* Get len */
834 if (data_len > ENET_MAX_MTU) /* Check len */
837 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
839 hw_p->stats.rx_err_log[hw_p->
842 hw_p->rx_err_index++;
843 if (hw_p->rx_err_index ==
848 } /* data_len < max mtu */
850 if (!data_len) { /* no data */
851 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
853 hw_p->stats.data_len_err++; /* Error at Rx */
858 /* Check if user has already eaten buffer */
859 /* if not => ERROR */
860 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
861 if (hw_p->is_receiving)
862 printf ("ERROR : Receive buffers are full!\n");
865 hw_p->stats.rx_frames++;
866 hw_p->stats.rx += data_len;
867 ef_ptr = (struct enet_frame *) hw_p->rx[i].
870 hw_p->stats.pkts_rx++;
875 hw_p->rx_ready[hw_p->rx_i_index] = i;
877 if (NUM_RX_BUFF == hw_p->rx_i_index)
878 hw_p->rx_i_index = 0;
880 /* printf("X"); /|* test-only *|/ */
883 * free receive buffer only when
884 * buffer has been handled (eth_rx)
885 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
889 } /* if EMACK_RXCHL */
893 static int ppc_4xx_eth_rx (struct eth_device *dev)
898 EMAC_405_HW_PST hw_p = dev->priv;
900 hw_p->is_receiving = 1; /* tell driver */
904 * use ring buffer and
905 * get index from rx buffer desciptor queue
907 user_index = hw_p->rx_ready[hw_p->rx_u_index];
908 if (user_index == -1) {
910 break; /* nothing received - leave for() loop */
914 mtmsr (msr & ~(MSR_EE));
916 length = hw_p->rx[user_index].data_len;
918 /* Pass the packet up to the protocol layers. */
919 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
920 /* NetReceive(NetRxPackets[i], length); */
921 NetReceive (NetRxPackets[user_index], length - 4);
922 /* Free Recv Buffer */
923 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
924 /* Free rx buffer descriptor queue */
925 hw_p->rx_ready[hw_p->rx_u_index] = -1;
927 if (NUM_RX_BUFF == hw_p->rx_u_index)
928 hw_p->rx_u_index = 0;
931 hw_p->stats.pkts_handled++;
934 mtmsr (msr); /* Enable IRQ's */
937 hw_p->is_receiving = 0; /* tell driver */
942 static int virgin = 0;
943 int ppc_4xx_eth_initialize (bd_t * bis)
945 struct eth_device *dev;
948 EMAC_405_HW_PST hw = NULL;
950 for (eth_num = 0; eth_num < EMAC_NUM_DEV; eth_num++) {
952 /* Allocate device structure */
953 dev = (struct eth_device *) malloc (sizeof (*dev));
955 printf ("ppc_405x_eth_initialize: "
956 "Cannot allocate eth_device %d\n", eth_num);
959 memset(dev, 0, sizeof(*dev));
960 /* Allocate our private use data */
961 hw = (EMAC_405_HW_PST) malloc (sizeof (*hw));
963 printf ("ppc_405x_eth_initialize: "
964 "Cannot allocate private hw data for eth_device %d",
969 memset(hw, 0, sizeof(*hw));
974 memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
976 #if defined(CONFIG_NET_MULTI)
979 memcpy (dev->enetaddr, bis->bi_enet1addr, 6);
984 memcpy (dev->enetaddr, bis->bi_enetaddr, 6);
988 hw->devnum = eth_num;
991 sprintf (dev->name, "ppc_405x_eth%d", eth_num);
992 dev->priv = (void *) hw;
993 dev->init = ppc_4xx_eth_init;
994 dev->halt = ppc_4xx_eth_halt;
995 dev->send = ppc_4xx_eth_send;
996 dev->recv = ppc_4xx_eth_rx;
999 /* set the MAL IER ??? names may change with new spec ??? */
1001 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
1002 MAL_IER_OPBE | MAL_IER_PLBE;
1003 mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
1004 mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
1005 mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
1006 mtdcr (malier, mal_ier);
1008 /* install MAL interrupt handler */
1009 irq_install_handler (VECNUM_MS,
1010 (interrupt_handler_t *) enetInt,
1012 irq_install_handler (VECNUM_MTE,
1013 (interrupt_handler_t *) enetInt,
1015 irq_install_handler (VECNUM_MRE,
1016 (interrupt_handler_t *) enetInt,
1018 irq_install_handler (VECNUM_TXDE,
1019 (interrupt_handler_t *) enetInt,
1021 irq_install_handler (VECNUM_RXDE,
1022 (interrupt_handler_t *) enetInt,
1027 #if defined(CONFIG_NET_MULTI)
1033 } /* end for each supported device */
1038 #if !defined(CONFIG_NET_MULTI)
1039 void eth_halt (void) {
1041 ppc_4xx_eth_halt(emac0_dev);
1047 int eth_init (bd_t *bis)
1049 ppc_4xx_eth_initialize(bis);
1050 return(ppc_4xx_eth_init(emac0_dev, bis));
1053 int eth_send(volatile void *packet, int length)
1056 return (ppc_4xx_eth_send(emac0_dev, packet, length));
1061 return (ppc_4xx_eth_rx(emac0_dev));
1065 #endif /* CONFIG_405 */