cpu/mpc8xxx/ddr/options.c

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/fsl_ddr_sdram.h>
  11
  12 #include "ddr.h"
  13
  14 /* Board-specific functions defined in each board's ddr.c */
  15 extern void fsl_ddr_board_options(memctl_options_t *popts,
  16                 dimm_params_t *pdimm,
  17                 unsigned int ctrl_num);
  18
  19 unsigned int populate_memctl_options(int all_DIMMs_registered,
  20                         memctl_options_t *popts,
  21                         dimm_params_t *pdimm,
  22                         unsigned int ctrl_num)
  23 {
  24         unsigned int i;
  25         const char *p;
  26
  27         /* Chip select options. */
  28
  29         /* Pick chip-select local options. */
  30         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  31                 /* If not DDR2, odt_rd_cfg and odt_wr_cfg need to be 0. */
  32
  33                 /* only for single CS? */
  34                 popts->cs_local_opts[i].odt_rd_cfg = 0;
  35
  36                 popts->cs_local_opts[i].odt_wr_cfg = 1;
  37                 popts->cs_local_opts[i].auto_precharge = 0;
  38         }
  39
  40         /* Pick interleaving mode. */
  41
  42         /*
  43          * 0 = no interleaving
  44          * 1 = interleaving between 2 controllers
  45          */
  46         popts->memctl_interleaving = 0;
  47
  48         /*
  49          * 0 = cacheline
  50          * 1 = page
  51          * 2 = (logical) bank
  52          * 3 = superbank (only if CS interleaving is enabled)
  53          */
  54         popts->memctl_interleaving_mode = 0;
  55
  56         /*
  57          * 0: cacheline: bit 30 of the 36-bit physical addr selects the memctl
  58          * 1: page:      bit to the left of the column bits selects the memctl
  59          * 2: bank:      bit to the left of the bank bits selects the memctl
  60          * 3: superbank: bit to the left of the chip select selects the memctl
  61          *
  62          * NOTE: ba_intlv (rank interleaving) is independent of memory
  63          * controller interleaving; it is only within a memory controller.
  64          * Must use superbank interleaving if rank interleaving is used and
  65          * memory controller interleaving is enabled.
  66          */
  67
  68         /*
  69          * 0 = no
  70          * 0x40 = CS0,CS1
  71          * 0x20 = CS2,CS3
  72          * 0x60 = CS0,CS1 + CS2,CS3
  73          * 0x04 = CS0,CS1,CS2,CS3
  74          */
  75         popts->ba_intlv_ctl = 0;
  76
  77         /* Memory Organization Parameters */
  78         popts->registered_dimm_en = all_DIMMs_registered;
  79
  80         /* Operational Mode Paramters */
  81
  82         /* Pick ECC modes */
  83 #ifdef CONFIG_DDR_ECC
  84         popts->ECC_mode = 1;              /* 0 = disabled, 1 = enabled */
  85 #else
  86         popts->ECC_mode = 0;              /* 0 = disabled, 1 = enabled */
  87 #endif
  88         popts->ECC_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
  89
  90         /*
  91          * Choose DQS config
  92          * 0 for DDR1
  93          * 1 for DDR2
  94          */
  95 #if defined(CONFIG_FSL_DDR1)
  96         popts->DQS_config = 0;
  97 #elif defined(CONFIG_FSL_DDR2) || defined(CONFIG_FSL_DDR3)
  98         popts->DQS_config = 1;
  99 #endif
 100
 101         /* Choose self-refresh during sleep. */
 102         popts->self_refresh_in_sleep = 1;
 103
 104         /* Choose dynamic power management mode. */
 105         popts->dynamic_power = 0;
 106
 107         /* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */
 108         popts->data_bus_width = 0;
 109
 110         /* Choose burst length. */
 111 #if defined(CONFIG_FSL_DDR3)
 112         popts->OTF_burst_chop_en = 1;   /* on-the-fly burst chop */
 113         popts->burst_length = DDR_OTF;  /* on-the-fly BC4 and BL8 */
 114 #else
 115         popts->burst_length = DDR_BL4;  /* has to be 4 for DDR2 */
 116 #endif
 117
 118         /* Choose ddr controller address mirror mode */
 119 #if defined(CONFIG_FSL_DDR3)
 120         popts->mirrored_dimm = pdimm[0].mirrored_dimm;
 121 #endif
 122
 123         /* Global Timing Parameters. */
 124         debug("mclk_ps = %u ps\n", get_memory_clk_period_ps());
 125
 126         /* Pick a caslat override. */
 127         popts->cas_latency_override = 0;
 128         popts->cas_latency_override_value = 3;
 129         if (popts->cas_latency_override) {
 130                 debug("using caslat override value = %u\n",
 131                        popts->cas_latency_override_value);
 132         }
 133
 134         /* Decide whether to use the computed derated latency */
 135         popts->use_derated_caslat = 0;
 136
 137         /* Choose an additive latency. */
 138         popts->additive_latency_override = 0;
 139         popts->additive_latency_override_value = 3;
 140         if (popts->additive_latency_override) {
 141                 debug("using additive latency override value = %u\n",
 142                        popts->additive_latency_override_value);
 143         }
 144
 145         /*
 146          * 2T_EN setting
 147          *
 148          * Factors to consider for 2T_EN:
 149          *      - number of DIMMs installed
 150          *      - number of components, number of active ranks
 151          *      - how much time you want to spend playing around
 152          */
 153         popts->twoT_en = 0;
 154         popts->threeT_en = 0;
 155
 156         /*
 157          * BSTTOPRE precharge interval
 158          *
 159          * Set this to 0 for global auto precharge
 160          *
 161          * FIXME: Should this be configured in picoseconds?
 162          * Why it should be in ps:  better understanding of this
 163          * relative to actual DRAM timing parameters such as tRAS.
 164          * e.g. tRAS(min) = 40 ns
 165          */
 166         popts->bstopre = 0x100;
 167
 168         /* Minimum CKE pulse width -- tCKE(MIN) */
 169         popts->tCKE_clock_pulse_width_ps
 170                 = mclk_to_picos(FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR);
 171
 172         /*
 173          * Window for four activates -- tFAW
 174          *
 175          * FIXME: UM: applies only to DDR2/DDR3 with eight logical banks only
 176          * FIXME: varies depending upon number of column addresses or data
 177          * FIXME: width, was considering looking at pdimm->primary_sdram_width
 178          */
 179 #if defined(CONFIG_FSL_DDR1)
 180         popts->tFAW_window_four_activates_ps = mclk_to_picos(1);
 181
 182 #elif defined(CONFIG_FSL_DDR2)
 183         /*
 184          * x4/x8;  some datasheets have 35000
 185          * x16 wide columns only?  Use 50000?
 186          */
 187         popts->tFAW_window_four_activates_ps = 37500;
 188
 189 #elif defined(CONFIG_FSL_DDR3)
 190         popts->tFAW_window_four_activates_ps = pdimm[0].tFAW_ps;
 191 #endif
 192         popts->zq_en = 0;
 193         popts->wrlvl_en = 0;
 194 #if defined(CONFIG_FSL_DDR3)
 195         /*
 196          * due to ddr3 dimm is fly-by topology
 197          * we suggest to enable write leveling to
 198          * meet the tQDSS under different loading.
 199          */
 200         popts->wrlvl_en = 1;
 201 #endif
 202
 203         /*
 204          * Check interleaving configuration from environment.
 205          * Please refer to doc/README.fsl-ddr for the detail.
 206          *
 207          * If memory controller interleaving is enabled, then the data
 208          * bus widths must be programmed identically for the 2 memory
 209          * controllers.
 210          *
 211          * XXX: Attempt to set both controllers to the same chip select
 212          * interleaving mode. It will do a best effort to get the
 213          * requested ranks interleaved together such that the result
 214          * should be a subset of the requested configuration.
 215          */
 216 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 217         if ((p = getenv("memctl_intlv_ctl")) != NULL) {
 218                 if (pdimm[0].n_ranks == 0) {
 219                         printf("There is no rank on CS0. Because only rank on "
 220                                 "CS0 and ranks chip-select interleaved with CS0"
 221                                 " are controller interleaved, force non memory "
 222                                 "controller interleaving\n");
 223                         popts->memctl_interleaving = 0;
 224                 } else {
 225                         popts->memctl_interleaving = 1;
 226                         if (strcmp(p, "cacheline") == 0)
 227                                 popts->memctl_interleaving_mode =
 228                                         FSL_DDR_CACHE_LINE_INTERLEAVING;
 229                         else if (strcmp(p, "page") == 0)
 230                                 popts->memctl_interleaving_mode =
 231                                         FSL_DDR_PAGE_INTERLEAVING;
 232                         else if (strcmp(p, "bank") == 0)
 233                                 popts->memctl_interleaving_mode =
 234                                         FSL_DDR_BANK_INTERLEAVING;
 235                         else if (strcmp(p, "superbank") == 0)
 236                                 popts->memctl_interleaving_mode =
 237                                         FSL_DDR_SUPERBANK_INTERLEAVING;
 238                         else
 239                                 popts->memctl_interleaving_mode =
 240                                                 simple_strtoul(p, NULL, 0);
 241                 }
 242         }
 243 #endif
 244
 245         if( ((p = getenv("ba_intlv_ctl")) != NULL) &&
 246                 (CONFIG_CHIP_SELECTS_PER_CTRL > 1)) {
 247                 if (strcmp(p, "cs0_cs1") == 0)
 248                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1;
 249                 else if (strcmp(p, "cs2_cs3") == 0)
 250                         popts->ba_intlv_ctl = FSL_DDR_CS2_CS3;
 251                 else if (strcmp(p, "cs0_cs1_and_cs2_cs3") == 0)
 252                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_AND_CS2_CS3;
 253                 else if (strcmp(p, "cs0_cs1_cs2_cs3") == 0)
 254                         popts->ba_intlv_ctl = FSL_DDR_CS0_CS1_CS2_CS3;
 255                 else
 256                         popts->ba_intlv_ctl = simple_strtoul(p, NULL, 0);
 257
 258                 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
 259                 case FSL_DDR_CS0_CS1_CS2_CS3:
 260                 case FSL_DDR_CS0_CS1:
 261                         if (pdimm[0].n_ranks != 2) {
 262                                 popts->ba_intlv_ctl = 0;
 263                                 printf("Not enough bank(chip-select) for "
 264                                         "CS0+CS1, force non-interleaving!\n");
 265                         }
 266                         break;
 267                 case FSL_DDR_CS2_CS3:
 268                         if (pdimm[1].n_ranks !=2){
 269                                 popts->ba_intlv_ctl = 0;
 270                                 printf("Not enough bank(CS) for CS2+CS3, "
 271                                         "force non-interleaving!\n");
 272                         }
 273                         break;
 274                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 275                         if ((pdimm[0].n_ranks != 2)||(pdimm[1].n_ranks != 2)) {
 276                                 popts->ba_intlv_ctl = 0;
 277                                 printf("Not enough bank(CS) for CS0+CS1 or "
 278                                         "CS2+CS3, force non-interleaving!\n");
 279                         }
 280                         break;
 281                 default:
 282                         popts->ba_intlv_ctl = 0;
 283                         break;
 284                 }
 285         }
 286
 287         fsl_ddr_board_options(popts, pdimm, ctrl_num);
 288
 289         return 0;
 290 }