cpu/mpc8xxx/ddr/main.c

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
  11  * Based on code from spd_sdram.c
  12  * Author: James Yang [at freescale.com]
  13  */
  14
  15 #include <common.h>
  16 #include <asm/fsl_ddr_sdram.h>
  17
  18 #include "ddr.h"
  19
  20 extern void fsl_ddr_set_lawbar(
  21                 const common_timing_params_t *memctl_common_params,
  22                 unsigned int memctl_interleaved,
  23                 unsigned int ctrl_num);
  24
  25 /* processor specific function */
  26 extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  27                                    unsigned int ctrl_num);
  28
  29 /* Board-specific functions defined in each board's ddr.c */
  30 extern void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  31                            unsigned int ctrl_num);
  32
  33 /*
  34  * ASSUMPTIONS:
  35  *    - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
  36  *    - Same memory data bus width on all controllers
  37  *
  38  * NOTES:
  39  *
  40  * The memory controller and associated documentation use confusing
  41  * terminology when referring to the orgranization of DRAM.
  42  *
  43  * Here is a terminology translation table:
  44  *
  45  * memory controller/documention  |industry   |this code  |signals
  46  * -------------------------------|-----------|-----------|-----------------
  47  * physical bank/bank             |rank       |rank       |chip select (CS)
  48  * logical bank/sub-bank          |bank       |bank       |bank address (BA)
  49  * page/row                       |row        |page       |row address
  50  * ???                            |column     |column     |column address
  51  *
  52  * The naming confusion is further exacerbated by the descriptions of the
  53  * memory controller interleaving feature, where accesses are interleaved
  54  * _BETWEEN_ two seperate memory controllers.  This is configured only in
  55  * CS0_CONFIG[INTLV_CTL] of each memory controller.
  56  *
  57  * memory controller documentation | number of chip selects
  58  *                                 | per memory controller supported
  59  * --------------------------------|-----------------------------------------
  60  * cache line interleaving         | 1 (CS0 only)
  61  * page interleaving               | 1 (CS0 only)
  62  * bank interleaving               | 1 (CS0 only)
  63  * superbank interleraving         | depends on bank (chip select)
  64  *                                 |   interleraving [rank interleaving]
  65  *                                 |   mode used on every memory controller
  66  *
  67  * Even further confusing is the existence of the interleaving feature
  68  * _WITHIN_ each memory controller.  The feature is referred to in
  69  * documentation as chip select interleaving or bank interleaving,
  70  * although it is configured in the DDR_SDRAM_CFG field.
  71  *
  72  * Name of field                | documentation name    | this code
  73  * -----------------------------|-----------------------|------------------
  74  * DDR_SDRAM_CFG[BA_INTLV_CTL]  | Bank (chip select)    | rank interleaving
  75  *                              |  interleaving
  76  */
  77
  78 #ifdef DEBUG
  79 const char *step_string_tbl[] = {
  80         "STEP_GET_SPD",
  81         "STEP_COMPUTE_DIMM_PARMS",
  82         "STEP_COMPUTE_COMMON_PARMS",
  83         "STEP_GATHER_OPTS",
  84         "STEP_ASSIGN_ADDRESSES",
  85         "STEP_COMPUTE_REGS",
  86         "STEP_PROGRAM_REGS",
  87         "STEP_ALL"
  88 };
  89
  90 const char * step_to_string(unsigned int step) {
  91
  92         unsigned int s = __ilog2(step);
  93
  94         if ((1 << s) != step)
  95                 return step_string_tbl[7];
  96
  97         return step_string_tbl[s];
  98 }
  99 #endif
 100
 101 int step_assign_addresses(fsl_ddr_info_t *pinfo,
 102                           unsigned int dbw_cap_adj[],
 103                           unsigned int *memctl_interleaving,
 104                           unsigned int *rank_interleaving)
 105 {
 106         int i, j;
 107
 108         /*
 109          * If a reduced data width is requested, but the SPD
 110          * specifies a physically wider device, adjust the
 111          * computed dimm capacities accordingly before
 112          * assigning addresses.
 113          */
 114         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 115                 unsigned int found = 0;
 116
 117                 switch (pinfo->memctl_opts[i].data_bus_width) {
 118                 case 2:
 119                         /* 16-bit */
 120                         printf("can't handle 16-bit mode yet\n");
 121                         break;
 122
 123                 case 1:
 124                         /* 32-bit */
 125                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 126                                 unsigned int dw;
 127                                 dw = pinfo->dimm_params[i][j].data_width;
 128                                 if (pinfo->dimm_params[i][j].n_ranks
 129                                     && (dw == 72 || dw == 64)) {
 130                                         /*
 131                                          * FIXME: can't really do it
 132                                          * like this because this just
 133                                          * further reduces the memory
 134                                          */
 135                                         found = 1;
 136                                         break;
 137                                 }
 138                         }
 139                         if (found) {
 140                                 dbw_cap_adj[i] = 1;
 141                         }
 142                         break;
 143
 144                 case 0:
 145                         /* 64-bit */
 146                         break;
 147
 148                 default:
 149                         printf("unexpected data bus width "
 150                                 "specified controller %u\n", i);
 151                         return 1;
 152                 }
 153         }
 154
 155         /*
 156          * Check if all controllers are configured for memory
 157          * controller interleaving.
 158          */
 159         j = 0;
 160         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 161                 if (pinfo->memctl_opts[i].memctl_interleaving) {
 162                         j++;
 163                 }
 164         }
 165         if (j == 2) {
 166                 *memctl_interleaving = 1;
 167
 168                 printf("\nMemory controller interleaving enabled: ");
 169
 170                 switch (pinfo->memctl_opts[0].memctl_interleaving_mode) {
 171                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
 172                         printf("Cache-line interleaving!\n");
 173                         break;
 174                 case FSL_DDR_PAGE_INTERLEAVING:
 175                         printf("Page interleaving!\n");
 176                         break;
 177                 case FSL_DDR_BANK_INTERLEAVING:
 178                         printf("Bank interleaving!\n");
 179                         break;
 180                 case FSL_DDR_SUPERBANK_INTERLEAVING:
 181                         printf("Super bank interleaving\n");
 182                 default:
 183                         break;
 184                 }
 185         }
 186
 187         /* Check that all controllers are rank interleaving. */
 188         j = 0;
 189         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 190                 if (pinfo->memctl_opts[i].ba_intlv_ctl) {
 191                         j++;
 192                 }
 193         }
 194         if (j == 2) {
 195                 *rank_interleaving = 1;
 196
 197                 printf("Bank(chip-select) interleaving enabled: ");
 198
 199                 switch (pinfo->memctl_opts[0].ba_intlv_ctl &
 200                                                 FSL_DDR_CS0_CS1_CS2_CS3) {
 201                 case FSL_DDR_CS0_CS1_CS2_CS3:
 202                         printf("CS0+CS1+CS2+CS3\n");
 203                         break;
 204                 case FSL_DDR_CS0_CS1:
 205                         printf("CS0+CS1\n");
 206                         break;
 207                 case FSL_DDR_CS2_CS3:
 208                         printf("CS2+CS3\n");
 209                         break;
 210                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 211                         printf("CS0+CS1 and CS2+CS3\n");
 212                 default:
 213                         break;
 214                 }
 215         }
 216
 217         if (*memctl_interleaving) {
 218                 unsigned long long addr, total_mem_per_ctlr = 0;
 219                 /*
 220                  * If interleaving between memory controllers,
 221                  * make each controller start at a base address
 222                  * of 0.
 223                  *
 224                  * Also, if bank interleaving (chip select
 225                  * interleaving) is enabled on each memory
 226                  * controller, CS0 needs to be programmed to
 227                  * cover the entire memory range on that memory
 228                  * controller
 229                  *
 230                  * Bank interleaving also implies that each
 231                  * addressed chip select is identical in size.
 232                  */
 233
 234                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 235                         addr = 0;
 236                         pinfo->common_timing_params[i].base_address = 0ull;
 237                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 238                                 unsigned long long cap
 239                                         = pinfo->dimm_params[i][j].capacity;
 240
 241                                 pinfo->dimm_params[i][j].base_address = addr;
 242                                 addr += cap >> dbw_cap_adj[i];
 243                                 total_mem_per_ctlr += cap >> dbw_cap_adj[i];
 244                         }
 245                 }
 246                 pinfo->common_timing_params[0].total_mem = total_mem_per_ctlr;
 247         } else {
 248                 /*
 249                  * Simple linear assignment if memory
 250                  * controllers are not interleaved.
 251                  */
 252                 unsigned long long cur_memsize = 0;
 253                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 254                         u64 total_mem_per_ctlr = 0;
 255                         pinfo->common_timing_params[i].base_address =
 256                                                 cur_memsize;
 257                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 258                                 /* Compute DIMM base addresses. */
 259                                 unsigned long long cap =
 260                                         pinfo->dimm_params[i][j].capacity;
 261                                 pinfo->dimm_params[i][j].base_address =
 262                                         cur_memsize;
 263                                 cur_memsize += cap >> dbw_cap_adj[i];
 264                                 total_mem_per_ctlr += cap >> dbw_cap_adj[i];
 265                         }
 266                         pinfo->common_timing_params[i].total_mem =
 267                                                         total_mem_per_ctlr;
 268                 }
 269         }
 270
 271         return 0;
 272 }
 273
 274 unsigned long long
 275 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step)
 276 {
 277         unsigned int i, j;
 278         unsigned int all_controllers_memctl_interleaving = 0;
 279         unsigned int all_controllers_rank_interleaving = 0;
 280         unsigned long long total_mem = 0;
 281
 282         fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
 283         common_timing_params_t *timing_params = pinfo->common_timing_params;
 284
 285         /* data bus width capacity adjust shift amount */
 286         unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
 287
 288         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 289                 dbw_capacity_adjust[i] = 0;
 290         }
 291
 292         debug("starting at step %u (%s)\n",
 293               start_step, step_to_string(start_step));
 294
 295         switch (start_step) {
 296         case STEP_GET_SPD:
 297                 /* STEP 1:  Gather all DIMM SPD data */
 298                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 299                         fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
 300                 }
 301
 302         case STEP_COMPUTE_DIMM_PARMS:
 303                 /* STEP 2:  Compute DIMM parameters from SPD data */
 304
 305                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 306                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 307                                 unsigned int retval;
 308                                 generic_spd_eeprom_t *spd =
 309                                         &(pinfo->spd_installed_dimms[i][j]);
 310                                 dimm_params_t *pdimm =
 311                                         &(pinfo->dimm_params[i][j]);
 312
 313                                 retval = compute_dimm_parameters(spd, pdimm, i);
 314                                 if (retval == 2) {
 315                                         printf("Error: compute_dimm_parameters"
 316                                         " non-zero returned FATAL value "
 317                                         "for memctl=%u dimm=%u\n", i, j);
 318                                         return 0;
 319                                 }
 320                                 if (retval) {
 321                                         debug("Warning: compute_dimm_parameters"
 322                                         " non-zero return value for memctl=%u "
 323                                         "dimm=%u\n", i, j);
 324                                 }
 325                         }
 326                 }
 327
 328         case STEP_COMPUTE_COMMON_PARMS:
 329                 /*
 330                  * STEP 3: Compute a common set of timing parameters
 331                  * suitable for all of the DIMMs on each memory controller
 332                  */
 333                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 334                         debug("Computing lowest common DIMM"
 335                                 " parameters for memctl=%u\n", i);
 336                         compute_lowest_common_dimm_parameters(
 337                                 pinfo->dimm_params[i],
 338                                 &timing_params[i],
 339                                 CONFIG_DIMM_SLOTS_PER_CTLR);
 340                 }
 341
 342         case STEP_GATHER_OPTS:
 343                 /* STEP 4:  Gather configuration requirements from user */
 344                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 345                         debug("Reloading memory controller "
 346                                 "configuration options for memctl=%u\n", i);
 347                         /*
 348                          * This "reloads" the memory controller options
 349                          * to defaults.  If the user "edits" an option,
 350                          * next_step points to the step after this,
 351                          * which is currently STEP_ASSIGN_ADDRESSES.
 352                          */
 353                         populate_memctl_options(
 354                                         timing_params[i].all_DIMMs_registered,
 355                                         &pinfo->memctl_opts[i],
 356                                         pinfo->dimm_params[i], i);
 357                 }
 358
 359         case STEP_ASSIGN_ADDRESSES:
 360                 /* STEP 5:  Assign addresses to chip selects */
 361                 step_assign_addresses(pinfo,
 362                                 dbw_capacity_adjust,
 363                                 &all_controllers_memctl_interleaving,
 364                                 &all_controllers_rank_interleaving);
 365
 366         case STEP_COMPUTE_REGS:
 367                 /* STEP 6:  compute controller register values */
 368                 debug("FSL Memory ctrl cg register computation\n");
 369                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 370                         if (timing_params[i].ndimms_present == 0) {
 371                                 memset(&ddr_reg[i], 0,
 372                                         sizeof(fsl_ddr_cfg_regs_t));
 373                                 continue;
 374                         }
 375
 376                         compute_fsl_memctl_config_regs(
 377                                         &pinfo->memctl_opts[i],
 378                                         &ddr_reg[i], &timing_params[i],
 379                                         pinfo->dimm_params[i],
 380                                         dbw_capacity_adjust[i]);
 381                 }
 382
 383         default:
 384                 break;
 385         }
 386
 387         /* Compute the total amount of memory. */
 388
 389         /*
 390          * If bank interleaving but NOT memory controller interleaving
 391          * CS_BNDS describe the quantity of memory on each memory
 392          * controller, so the total is the sum across.
 393          */
 394         if (!all_controllers_memctl_interleaving
 395             && all_controllers_rank_interleaving) {
 396                 total_mem = 0;
 397                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 398                         total_mem += timing_params[i].total_mem;
 399                 }
 400
 401         } else {
 402                 /*
 403                  * Compute the amount of memory available just by
 404                  * looking for the highest valid CSn_BNDS value.
 405                  * This allows us to also experiment with using
 406                  * only CS0 when using dual-rank DIMMs.
 407                  */
 408                 unsigned int max_end = 0;
 409
 410                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 411                         for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
 412                                 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
 413                                 if (reg->cs[j].config & 0x80000000) {
 414                                         unsigned int end;
 415                                         end = reg->cs[j].bnds & 0xFFF;
 416                                         if (end > max_end) {
 417                                                 max_end = end;
 418                                         }
 419                                 }
 420                         }
 421                 }
 422
 423                 total_mem = 1 + (((unsigned long long)max_end << 24ULL)
 424                                     | 0xFFFFFFULL);
 425         }
 426
 427         return total_mem;
 428 }
 429
 430 /*
 431  * fsl_ddr_sdram() -- this is the main function to be called by
 432  *      initdram() in the board file.
 433  *
 434  * It returns amount of memory configured in bytes.
 435  */
 436 phys_size_t fsl_ddr_sdram(void)
 437 {
 438         unsigned int i;
 439         unsigned int memctl_interleaved;
 440         unsigned long long total_memory;
 441         fsl_ddr_info_t info;
 442
 443         /* Reset info structure. */
 444         memset(&info, 0, sizeof(fsl_ddr_info_t));
 445
 446         /* Compute it once normally. */
 447         total_memory = fsl_ddr_compute(&info, STEP_GET_SPD);
 448
 449         /* Check for memory controller interleaving. */
 450         memctl_interleaved = 0;
 451         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 452                 memctl_interleaved +=
 453                         info.memctl_opts[i].memctl_interleaving;
 454         }
 455
 456         if (memctl_interleaved) {
 457                 if (memctl_interleaved == CONFIG_NUM_DDR_CONTROLLERS) {
 458                         debug("memctl interleaving\n");
 459                         /*
 460                          * Change the meaning of memctl_interleaved
 461                          * to be "boolean".
 462                          */
 463                         memctl_interleaved = 1;
 464                 } else {
 465                         printf("Warning: memctl interleaving not "
 466                                 "properly configured on all controllers\n");
 467                         memctl_interleaved = 0;
 468                         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++)
 469                                 info.memctl_opts[i].memctl_interleaving = 0;
 470                         debug("Recomputing with memctl_interleaving off.\n");
 471                         total_memory = fsl_ddr_compute(&info,
 472                                                        STEP_ASSIGN_ADDRESSES);
 473                 }
 474         }
 475
 476         /* Program configuration registers. */
 477         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 478                 debug("Programming controller %u\n", i);
 479                 if (info.common_timing_params[i].ndimms_present == 0) {
 480                         debug("No dimms present on controller %u; "
 481                                         "skipping programming\n", i);
 482                         continue;
 483                 }
 484
 485                 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i);
 486         }
 487
 488         if (memctl_interleaved) {
 489                 const unsigned int ctrl_num = 0;
 490
 491                 /* Only set LAWBAR1 if memory controller interleaving is on. */
 492                 fsl_ddr_set_lawbar(&info.common_timing_params[0],
 493                                          memctl_interleaved, ctrl_num);
 494         } else {
 495                 /*
 496                  * Memory controller interleaving is NOT on;
 497                  * set each lawbar individually.
 498                  */
 499                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 500                         fsl_ddr_set_lawbar(&info.common_timing_params[i],
 501                                                  0, i);
 502                 }
 503         }
 504
 505         debug("total_memory = %llu\n", total_memory);
 506
 507 #if !defined(CONFIG_PHYS_64BIT)
 508         /* Check for 4G or more.  Bad. */
 509         if (total_memory >= (1ull << 32)) {
 510                 printf("Detected %lld MB of memory\n", total_memory >> 20);
 511                 printf("This U-Boot only supports < 4G of DDR\n");
 512                 printf("You could rebuild it with CONFIG_PHYS_64BIT\n");
 513                 total_memory = CONFIG_MAX_MEM_MAPPED;
 514         }
 515 #endif
 516
 517         return total_memory;
 518 }