2 * Copyright 2008-2009 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
10 * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
11 * Based on code from spd_sdram.c
12 * Author: James Yang [at freescale.com]
16 #include <asm/fsl_ddr_sdram.h>
20 extern unsigned int picos_to_mclk(unsigned int picos);
22 * Determine Rtt value.
24 * This should likely be either board or controller specific.
26 * Rtt(nominal) - DDR2:
31 * Rtt(nominal) - DDR3:
39 * FIXME: Apparently 8641 needs a value of 2
40 * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
42 * FIXME: There was some effort down this line earlier:
45 * for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
46 * if (popts->dimmslot[i].num_valid_cs
47 * && (popts->cs_local_opts[2*i].odt_rd_cfg
48 * || popts->cs_local_opts[2*i].odt_wr_cfg)) {
54 static inline int fsl_ddr_get_rtt(void)
58 #if defined(CONFIG_FSL_DDR1)
60 #elif defined(CONFIG_FSL_DDR2)
70 * compute the CAS write latency according to DDR3 spec
71 * CWL = 5 if tCK >= 2.5ns
72 * 6 if 2.5ns > tCK >= 1.875ns
73 * 7 if 1.875ns > tCK >= 1.5ns
74 * 8 if 1.5ns > tCK >= 1.25ns
76 static inline unsigned int compute_cas_write_latency(void)
79 const unsigned int mclk_ps = get_memory_clk_period_ps();
83 else if (mclk_ps >= 1875)
85 else if (mclk_ps >= 1500)
87 else if (mclk_ps >= 1250)
94 /* Chip Select Configuration (CSn_CONFIG) */
95 static void set_csn_config(int i, fsl_ddr_cfg_regs_t *ddr,
96 const memctl_options_t *popts,
97 const dimm_params_t *dimm_params)
99 unsigned int cs_n_en = 0; /* Chip Select enable */
100 unsigned int intlv_en = 0; /* Memory controller interleave enable */
101 unsigned int intlv_ctl = 0; /* Interleaving control */
102 unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
103 unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
104 unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
105 unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
106 unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
107 unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
109 /* Compute CS_CONFIG only for existing ranks of each DIMM. */
111 && (dimm_params[i/2].n_ranks == 1))
112 || (dimm_params[i/2].n_ranks == 2)) {
113 unsigned int n_banks_per_sdram_device;
116 /* These fields only available in CS0_CONFIG */
117 intlv_en = popts->memctl_interleaving;
118 intlv_ctl = popts->memctl_interleaving_mode;
120 ap_n_en = popts->cs_local_opts[i].auto_precharge;
121 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
122 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
123 n_banks_per_sdram_device
124 = dimm_params[i/2].n_banks_per_sdram_device;
125 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
126 row_bits_cs_n = dimm_params[i/2].n_row_addr - 12;
127 col_bits_cs_n = dimm_params[i/2].n_col_addr - 8;
130 ddr->cs[i].config = (0
131 | ((cs_n_en & 0x1) << 31)
132 | ((intlv_en & 0x3) << 29)
133 | ((intlv_ctl & 0xf) << 24)
134 | ((ap_n_en & 0x1) << 23)
136 /* XXX: some implementation only have 1 bit starting at left */
137 | ((odt_rd_cfg & 0x7) << 20)
139 /* XXX: Some implementation only have 1 bit starting at left */
140 | ((odt_wr_cfg & 0x7) << 16)
142 | ((ba_bits_cs_n & 0x3) << 14)
143 | ((row_bits_cs_n & 0x7) << 8)
144 | ((col_bits_cs_n & 0x7) << 0)
146 debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
149 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
151 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
153 unsigned int pasr_cfg = 0; /* Partial array self refresh config */
155 ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
156 debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
159 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
161 #if !defined(CONFIG_FSL_DDR1)
163 * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
165 * Avoid writing for DDR I. The new PQ38 DDR controller
166 * dreams up non-zero default values to be backwards compatible.
168 static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr)
170 unsigned char trwt_mclk = 0; /* Read-to-write turnaround */
171 unsigned char twrt_mclk = 0; /* Write-to-read turnaround */
172 /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
173 unsigned char trrt_mclk = 0; /* Read-to-read turnaround */
174 unsigned char twwt_mclk = 0; /* Write-to-write turnaround */
176 /* Active powerdown exit timing (tXARD and tXARDS). */
177 unsigned char act_pd_exit_mclk;
178 /* Precharge powerdown exit timing (tXP). */
179 unsigned char pre_pd_exit_mclk;
180 /* Precharge powerdown exit timing (tAXPD). */
181 unsigned char taxpd_mclk;
182 /* Mode register set cycle time (tMRD). */
183 unsigned char tmrd_mclk;
185 #if defined(CONFIG_FSL_DDR3)
187 * (tXARD and tXARDS). Empirical?
188 * The DDR3 spec has not tXARD,
189 * we use the tXP instead of it.
190 * tXP=max(3nCK, 7.5ns) for DDR3.
191 * spec has not the tAXPD, we use
192 * tAXPD=8, need design to confirm.
194 int tXP = max((get_memory_clk_period_ps() * 3), 7500); /* unit=ps */
195 act_pd_exit_mclk = picos_to_mclk(tXP);
196 /* Mode register MR0[A12] is '1' - fast exit */
197 pre_pd_exit_mclk = act_pd_exit_mclk;
200 #else /* CONFIG_FSL_DDR2 */
202 * (tXARD and tXARDS). Empirical?
207 act_pd_exit_mclk = 2;
208 pre_pd_exit_mclk = 2;
213 ddr->timing_cfg_0 = (0
214 | ((trwt_mclk & 0x3) << 30) /* RWT */
215 | ((twrt_mclk & 0x3) << 28) /* WRT */
216 | ((trrt_mclk & 0x3) << 26) /* RRT */
217 | ((twwt_mclk & 0x3) << 24) /* WWT */
218 | ((act_pd_exit_mclk & 0x7) << 20) /* ACT_PD_EXIT */
219 | ((pre_pd_exit_mclk & 0xF) << 16) /* PRE_PD_EXIT */
220 | ((taxpd_mclk & 0xf) << 8) /* ODT_PD_EXIT */
221 | ((tmrd_mclk & 0xf) << 0) /* MRS_CYC */
223 debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
225 #endif /* defined(CONFIG_FSL_DDR2) */
227 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
228 static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,
229 const common_timing_params_t *common_dimm,
230 unsigned int cas_latency)
232 /* Extended Activate to precharge interval (tRAS) */
233 unsigned int ext_acttopre = 0;
234 unsigned int ext_refrec; /* Extended refresh recovery time (tRFC) */
235 unsigned int ext_caslat = 0; /* Extended MCAS latency from READ cmd */
236 unsigned int cntl_adj = 0; /* Control Adjust */
238 /* If the tRAS > 19 MCLK, we use the ext mode */
239 if (picos_to_mclk(common_dimm->tRAS_ps) > 0x13)
242 ext_refrec = (picos_to_mclk(common_dimm->tRFC_ps) - 8) >> 4;
244 /* If the CAS latency more than 8, use the ext mode */
248 ddr->timing_cfg_3 = (0
249 | ((ext_acttopre & 0x1) << 24)
250 | ((ext_refrec & 0xF) << 16)
251 | ((ext_caslat & 0x1) << 12)
252 | ((cntl_adj & 0x7) << 0)
254 debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
257 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
258 static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr,
259 const memctl_options_t *popts,
260 const common_timing_params_t *common_dimm,
261 unsigned int cas_latency)
263 /* Precharge-to-activate interval (tRP) */
264 unsigned char pretoact_mclk;
265 /* Activate to precharge interval (tRAS) */
266 unsigned char acttopre_mclk;
267 /* Activate to read/write interval (tRCD) */
268 unsigned char acttorw_mclk;
270 unsigned char caslat_ctrl;
271 /* Refresh recovery time (tRFC) ; trfc_low */
272 unsigned char refrec_ctrl;
273 /* Last data to precharge minimum interval (tWR) */
274 unsigned char wrrec_mclk;
275 /* Activate-to-activate interval (tRRD) */
276 unsigned char acttoact_mclk;
277 /* Last write data pair to read command issue interval (tWTR) */
278 unsigned char wrtord_mclk;
280 pretoact_mclk = picos_to_mclk(common_dimm->tRP_ps);
281 acttopre_mclk = picos_to_mclk(common_dimm->tRAS_ps);
282 acttorw_mclk = picos_to_mclk(common_dimm->tRCD_ps);
285 * Translate CAS Latency to a DDR controller field value:
287 * CAS Lat DDR I DDR II Ctrl
288 * Clocks SPD Bit SPD Bit Value
289 * ------- ------- ------- -----
300 #if defined(CONFIG_FSL_DDR1)
301 caslat_ctrl = (cas_latency + 1) & 0x07;
302 #elif defined(CONFIG_FSL_DDR2)
303 caslat_ctrl = 2 * cas_latency - 1;
306 * if the CAS latency more than 8 cycle,
307 * we need set extend bit for it at
308 * TIMING_CFG_3[EXT_CASLAT]
312 caslat_ctrl = 2 * cas_latency - 1;
315 refrec_ctrl = picos_to_mclk(common_dimm->tRFC_ps) - 8;
316 wrrec_mclk = picos_to_mclk(common_dimm->tWR_ps);
317 if (popts->OTF_burst_chop_en)
320 acttoact_mclk = picos_to_mclk(common_dimm->tRRD_ps);
322 * JEDEC has min requirement for tRRD
324 #if defined(CONFIG_FSL_DDR3)
325 if (acttoact_mclk < 4)
328 wrtord_mclk = picos_to_mclk(common_dimm->tWTR_ps);
330 * JEDEC has some min requirements for tWTR
332 #if defined(CONFIG_FSL_DDR2)
335 #elif defined(CONFIG_FSL_DDR3)
339 if (popts->OTF_burst_chop_en)
342 ddr->timing_cfg_1 = (0
343 | ((pretoact_mclk & 0x0F) << 28)
344 | ((acttopre_mclk & 0x0F) << 24)
345 | ((acttorw_mclk & 0xF) << 20)
346 | ((caslat_ctrl & 0xF) << 16)
347 | ((refrec_ctrl & 0xF) << 12)
348 | ((wrrec_mclk & 0x0F) << 8)
349 | ((acttoact_mclk & 0x07) << 4)
350 | ((wrtord_mclk & 0x07) << 0)
352 debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
355 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
356 static void set_timing_cfg_2(fsl_ddr_cfg_regs_t *ddr,
357 const memctl_options_t *popts,
358 const common_timing_params_t *common_dimm,
359 unsigned int cas_latency,
360 unsigned int additive_latency)
362 /* Additive latency */
363 unsigned char add_lat_mclk;
364 /* CAS-to-preamble override */
367 unsigned char wr_lat;
368 /* Read to precharge (tRTP) */
369 unsigned char rd_to_pre;
370 /* Write command to write data strobe timing adjustment */
371 unsigned char wr_data_delay;
372 /* Minimum CKE pulse width (tCKE) */
373 unsigned char cke_pls;
374 /* Window for four activates (tFAW) */
375 unsigned short four_act;
377 /* FIXME add check that this must be less than acttorw_mclk */
378 add_lat_mclk = additive_latency;
379 cpo = popts->cpo_override;
381 #if defined(CONFIG_FSL_DDR1)
383 * This is a lie. It should really be 1, but if it is
384 * set to 1, bits overlap into the old controller's
385 * otherwise unused ACSM field. If we leave it 0, then
386 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
389 #elif defined(CONFIG_FSL_DDR2)
390 wr_lat = cas_latency - 1;
392 wr_lat = compute_cas_write_latency();
395 rd_to_pre = picos_to_mclk(common_dimm->tRTP_ps);
397 * JEDEC has some min requirements for tRTP
399 #if defined(CONFIG_FSL_DDR2)
402 #elif defined(CONFIG_FSL_DDR3)
406 if (additive_latency)
407 rd_to_pre += additive_latency;
408 if (popts->OTF_burst_chop_en)
409 rd_to_pre += 2; /* according to UM */
411 wr_data_delay = popts->write_data_delay;
412 cke_pls = picos_to_mclk(popts->tCKE_clock_pulse_width_ps);
413 four_act = picos_to_mclk(popts->tFAW_window_four_activates_ps);
415 ddr->timing_cfg_2 = (0
416 | ((add_lat_mclk & 0xf) << 28)
417 | ((cpo & 0x1f) << 23)
418 | ((wr_lat & 0xf) << 19)
419 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
420 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
421 | ((cke_pls & 0x7) << 6)
422 | ((four_act & 0x3f) << 0)
424 debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
427 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
428 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
429 const memctl_options_t *popts,
430 const common_timing_params_t *common_dimm)
432 unsigned int mem_en; /* DDR SDRAM interface logic enable */
433 unsigned int sren; /* Self refresh enable (during sleep) */
434 unsigned int ecc_en; /* ECC enable. */
435 unsigned int rd_en; /* Registered DIMM enable */
436 unsigned int sdram_type; /* Type of SDRAM */
437 unsigned int dyn_pwr; /* Dynamic power management mode */
438 unsigned int dbw; /* DRAM dta bus width */
439 unsigned int eight_be = 0; /* 8-beat burst enable, DDR2 is zero */
440 unsigned int ncap = 0; /* Non-concurrent auto-precharge */
441 unsigned int threeT_en; /* Enable 3T timing */
442 unsigned int twoT_en; /* Enable 2T timing */
443 unsigned int ba_intlv_ctl; /* Bank (CS) interleaving control */
444 unsigned int x32_en = 0; /* x32 enable */
445 unsigned int pchb8 = 0; /* precharge bit 8 enable */
446 unsigned int hse; /* Global half strength override */
447 unsigned int mem_halt = 0; /* memory controller halt */
448 unsigned int bi = 0; /* Bypass initialization */
451 sren = popts->self_refresh_in_sleep;
452 if (common_dimm->all_DIMMs_ECC_capable) {
453 /* Allow setting of ECC only if all DIMMs are ECC. */
454 ecc_en = popts->ECC_mode;
459 rd_en = (common_dimm->all_DIMMs_registered
460 && !common_dimm->all_DIMMs_unbuffered);
462 sdram_type = CONFIG_FSL_SDRAM_TYPE;
464 dyn_pwr = popts->dynamic_power;
465 dbw = popts->data_bus_width;
466 /* 8-beat burst enable DDR-III case
467 * we must clear it when use the on-the-fly mode,
468 * must set it when use the 32-bits bus mode.
470 if (sdram_type == SDRAM_TYPE_DDR3) {
471 if (popts->burst_length == DDR_BL8)
473 if (popts->burst_length == DDR_OTF)
479 threeT_en = popts->threeT_en;
480 twoT_en = popts->twoT_en;
481 ba_intlv_ctl = popts->ba_intlv_ctl;
482 hse = popts->half_strength_driver_enable;
484 ddr->ddr_sdram_cfg = (0
485 | ((mem_en & 0x1) << 31)
486 | ((sren & 0x1) << 30)
487 | ((ecc_en & 0x1) << 29)
488 | ((rd_en & 0x1) << 28)
489 | ((sdram_type & 0x7) << 24)
490 | ((dyn_pwr & 0x1) << 21)
491 | ((dbw & 0x3) << 19)
492 | ((eight_be & 0x1) << 18)
493 | ((ncap & 0x1) << 17)
494 | ((threeT_en & 0x1) << 16)
495 | ((twoT_en & 0x1) << 15)
496 | ((ba_intlv_ctl & 0x7F) << 8)
497 | ((x32_en & 0x1) << 5)
498 | ((pchb8 & 0x1) << 4)
500 | ((mem_halt & 0x1) << 1)
503 debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
506 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
507 static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
508 const memctl_options_t *popts)
510 unsigned int frc_sr = 0; /* Force self refresh */
511 unsigned int sr_ie = 0; /* Self-refresh interrupt enable */
512 unsigned int dll_rst_dis; /* DLL reset disable */
513 unsigned int dqs_cfg; /* DQS configuration */
514 unsigned int odt_cfg; /* ODT configuration */
515 unsigned int num_pr; /* Number of posted refreshes */
516 unsigned int obc_cfg; /* On-The-Fly Burst Chop Cfg */
517 unsigned int ap_en; /* Address Parity Enable */
518 unsigned int d_init; /* DRAM data initialization */
519 unsigned int rcw_en = 0; /* Register Control Word Enable */
520 unsigned int md_en = 0; /* Mirrored DIMM Enable */
522 dll_rst_dis = 1; /* Make this configurable */
523 dqs_cfg = popts->DQS_config;
524 if (popts->cs_local_opts[0].odt_rd_cfg
525 || popts->cs_local_opts[0].odt_wr_cfg) {
532 num_pr = 1; /* Make this configurable */
536 * {TIMING_CFG_1[PRETOACT]
537 * + [DDR_SDRAM_CFG_2[NUM_PR]
538 * * ({EXT_REFREC || REFREC} + 8 + 2)]}
539 * << DDR_SDRAM_INTERVAL[REFINT]
541 #if defined(CONFIG_FSL_DDR3)
542 obc_cfg = popts->OTF_burst_chop_en;
547 ap_en = 0; /* Make this configurable? */
549 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
550 /* Use the DDR controller to auto initialize memory. */
552 ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
553 debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
555 /* Memory will be initialized via DMA, or not at all. */
559 #if defined(CONFIG_FSL_DDR3)
560 md_en = popts->mirrored_dimm;
562 ddr->ddr_sdram_cfg_2 = (0
563 | ((frc_sr & 0x1) << 31)
564 | ((sr_ie & 0x1) << 30)
565 | ((dll_rst_dis & 0x1) << 29)
566 | ((dqs_cfg & 0x3) << 26)
567 | ((odt_cfg & 0x3) << 21)
568 | ((num_pr & 0xf) << 12)
569 | ((obc_cfg & 0x1) << 6)
570 | ((ap_en & 0x1) << 5)
571 | ((d_init & 0x1) << 4)
572 | ((rcw_en & 0x1) << 2)
573 | ((md_en & 0x1) << 0)
575 debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
578 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
579 static void set_ddr_sdram_mode_2(fsl_ddr_cfg_regs_t *ddr,
580 const memctl_options_t *popts)
582 unsigned short esdmode2 = 0; /* Extended SDRAM mode 2 */
583 unsigned short esdmode3 = 0; /* Extended SDRAM mode 3 */
585 #if defined(CONFIG_FSL_DDR3)
586 unsigned int rtt_wr = 0; /* Rtt_WR - dynamic ODT off */
587 unsigned int srt = 0; /* self-refresh temerature, normal range */
588 unsigned int asr = 0; /* auto self-refresh disable */
589 unsigned int cwl = compute_cas_write_latency() - 5;
590 unsigned int pasr = 0; /* partial array self refresh disable */
592 if (popts->rtt_override)
593 rtt_wr = popts->rtt_wr_override_value;
596 | ((rtt_wr & 0x3) << 9)
600 | ((pasr & 0x7) << 0));
602 ddr->ddr_sdram_mode_2 = (0
603 | ((esdmode2 & 0xFFFF) << 16)
604 | ((esdmode3 & 0xFFFF) << 0)
606 debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
609 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
610 static void set_ddr_sdram_interval(fsl_ddr_cfg_regs_t *ddr,
611 const memctl_options_t *popts,
612 const common_timing_params_t *common_dimm)
614 unsigned int refint; /* Refresh interval */
615 unsigned int bstopre; /* Precharge interval */
617 refint = picos_to_mclk(common_dimm->refresh_rate_ps);
619 bstopre = popts->bstopre;
621 /* refint field used 0x3FFF in earlier controllers */
622 ddr->ddr_sdram_interval = (0
623 | ((refint & 0xFFFF) << 16)
624 | ((bstopre & 0x3FFF) << 0)
626 debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
629 #if defined(CONFIG_FSL_DDR3)
630 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
631 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
632 const memctl_options_t *popts,
633 const common_timing_params_t *common_dimm,
634 unsigned int cas_latency,
635 unsigned int additive_latency)
637 unsigned short esdmode; /* Extended SDRAM mode */
638 unsigned short sdmode; /* SDRAM mode */
640 /* Mode Register - MR1 */
641 unsigned int qoff = 0; /* Output buffer enable 0=yes, 1=no */
642 unsigned int tdqs_en = 0; /* TDQS Enable: 0=no, 1=yes */
644 unsigned int wrlvl_en = 0; /* Write level enable: 0=no, 1=yes */
645 unsigned int al = 0; /* Posted CAS# additive latency (AL) */
646 unsigned int dic = 1; /* Output driver impedance, 34ohm */
647 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
648 1=Disable (Test/Debug) */
650 /* Mode Register - MR0 */
651 unsigned int dll_on; /* DLL control for precharge PD, 0=off, 1=on */
652 unsigned int wr; /* Write Recovery */
653 unsigned int dll_rst; /* DLL Reset */
654 unsigned int mode; /* Normal=0 or Test=1 */
655 unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
656 /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
658 unsigned int bl; /* BL: Burst Length */
660 unsigned int wr_mclk;
662 const unsigned int mclk_ps = get_memory_clk_period_ps();
664 rtt = fsl_ddr_get_rtt();
665 if (popts->rtt_override)
666 rtt = popts->rtt_override_value;
668 if (additive_latency == (cas_latency - 1))
670 if (additive_latency == (cas_latency - 2))
674 * The esdmode value will also be used for writing
675 * MR1 during write leveling for DDR3, although the
676 * bits specifically related to the write leveling
677 * scheme will be handled automatically by the DDR
678 * controller. so we set the wrlvl_en = 0 here.
681 | ((qoff & 0x1) << 12)
682 | ((tdqs_en & 0x1) << 11)
683 | ((rtt & 0x4) << 7) /* rtt field is split */
684 | ((wrlvl_en & 0x1) << 7)
685 | ((rtt & 0x2) << 5) /* rtt field is split */
686 | ((dic & 0x2) << 4) /* DIC field is split */
688 | ((rtt & 0x1) << 2) /* rtt field is split */
689 | ((dic & 0x1) << 1) /* DIC field is split */
690 | ((dll_en & 0x1) << 0)
694 * DLL control for precharge PD
695 * 0=slow exit DLL off (tXPDLL)
696 * 1=fast exit DLL on (tXP)
699 wr_mclk = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps;
702 else if (wr_mclk >= 9)
706 dll_rst = 0; /* dll no reset */
707 mode = 0; /* normal mode */
709 /* look up table to get the cas latency bits */
710 if (cas_latency >= 5 && cas_latency <= 11) {
711 unsigned char cas_latency_table[7] = {
720 caslat = cas_latency_table[cas_latency - 5];
722 bt = 0; /* Nibble sequential */
724 switch (popts->burst_length) {
735 printf("Error: invalid burst length of %u specified. "
736 " Defaulting to on-the-fly BC4 or BL8 beats.\n",
737 popts->burst_length);
743 | ((dll_on & 0x1) << 12)
745 | ((dll_rst & 0x1) << 8)
746 | ((mode & 0x1) << 7)
747 | (((caslat >> 1) & 0x7) << 4)
752 ddr->ddr_sdram_mode = (0
753 | ((esdmode & 0xFFFF) << 16)
754 | ((sdmode & 0xFFFF) << 0)
757 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
760 #else /* !CONFIG_FSL_DDR3 */
762 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
763 static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
764 const memctl_options_t *popts,
765 const common_timing_params_t *common_dimm,
766 unsigned int cas_latency,
767 unsigned int additive_latency)
769 unsigned short esdmode; /* Extended SDRAM mode */
770 unsigned short sdmode; /* SDRAM mode */
773 * FIXME: This ought to be pre-calculated in a
774 * technology-specific routine,
775 * e.g. compute_DDR2_mode_register(), and then the
776 * sdmode and esdmode passed in as part of common_dimm.
779 /* Extended Mode Register */
780 unsigned int mrs = 0; /* Mode Register Set */
781 unsigned int outputs = 0; /* 0=Enabled, 1=Disabled */
782 unsigned int rdqs_en = 0; /* RDQS Enable: 0=no, 1=yes */
783 unsigned int dqs_en = 0; /* DQS# Enable: 0=enable, 1=disable */
784 unsigned int ocd = 0; /* 0x0=OCD not supported,
785 0x7=OCD default state */
787 unsigned int al; /* Posted CAS# additive latency (AL) */
788 unsigned int ods = 0; /* Output Drive Strength:
789 0 = Full strength (18ohm)
790 1 = Reduced strength (4ohm) */
791 unsigned int dll_en = 0; /* DLL Enable 0=Enable (Normal),
792 1=Disable (Test/Debug) */
794 /* Mode Register (MR) */
795 unsigned int mr; /* Mode Register Definition */
796 unsigned int pd; /* Power-Down Mode */
797 unsigned int wr; /* Write Recovery */
798 unsigned int dll_res; /* DLL Reset */
799 unsigned int mode; /* Normal=0 or Test=1 */
800 unsigned int caslat = 0;/* CAS# latency */
801 /* BT: Burst Type (0=Sequential, 1=Interleaved) */
803 unsigned int bl; /* BL: Burst Length */
805 #if defined(CONFIG_FSL_DDR2)
806 const unsigned int mclk_ps = get_memory_clk_period_ps();
809 rtt = fsl_ddr_get_rtt();
811 al = additive_latency;
814 | ((mrs & 0x3) << 14)
815 | ((outputs & 0x1) << 12)
816 | ((rdqs_en & 0x1) << 11)
817 | ((dqs_en & 0x1) << 10)
819 | ((rtt & 0x2) << 5) /* rtt field is split */
821 | ((rtt & 0x1) << 2) /* rtt field is split */
823 | ((dll_en & 0x1) << 0)
826 mr = 0; /* FIXME: CHECKME */
829 * 0 = Fast Exit (Normal)
830 * 1 = Slow Exit (Low Power)
834 #if defined(CONFIG_FSL_DDR1)
835 wr = 0; /* Historical */
836 #elif defined(CONFIG_FSL_DDR2)
837 wr = (common_dimm->tWR_ps + mclk_ps - 1) / mclk_ps - 1;
842 #if defined(CONFIG_FSL_DDR1)
843 if (1 <= cas_latency && cas_latency <= 4) {
844 unsigned char mode_caslat_table[4] = {
845 0x5, /* 1.5 clocks */
846 0x2, /* 2.0 clocks */
847 0x6, /* 2.5 clocks */
850 caslat = mode_caslat_table[cas_latency - 1];
852 printf("Warning: unknown cas_latency %d\n", cas_latency);
854 #elif defined(CONFIG_FSL_DDR2)
855 caslat = cas_latency;
859 switch (popts->burst_length) {
867 printf("Error: invalid burst length of %u specified. "
868 " Defaulting to 4 beats.\n",
869 popts->burst_length);
878 | ((dll_res & 0x1) << 8)
879 | ((mode & 0x1) << 7)
880 | ((caslat & 0x7) << 4)
885 ddr->ddr_sdram_mode = (0
886 | ((esdmode & 0xFFFF) << 16)
887 | ((sdmode & 0xFFFF) << 0)
889 debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
893 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
894 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
896 unsigned int init_value; /* Initialization value */
898 init_value = 0xDEADBEEF;
899 ddr->ddr_data_init = init_value;
903 * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
904 * The old controller on the 8540/60 doesn't have this register.
905 * Hope it's OK to set it (to 0) anyway.
907 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
908 const memctl_options_t *popts)
910 unsigned int clk_adjust; /* Clock adjust */
912 clk_adjust = popts->clk_adjust;
913 ddr->ddr_sdram_clk_cntl = (clk_adjust & 0xF) << 23;
916 /* DDR Initialization Address (DDR_INIT_ADDR) */
917 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
919 unsigned int init_addr = 0; /* Initialization address */
921 ddr->ddr_init_addr = init_addr;
924 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
925 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
927 unsigned int uia = 0; /* Use initialization address */
928 unsigned int init_ext_addr = 0; /* Initialization address */
930 ddr->ddr_init_ext_addr = (0
931 | ((uia & 0x1) << 31)
932 | (init_ext_addr & 0xF)
936 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
937 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr)
939 unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
940 unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
941 unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
942 unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
943 unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
945 #if defined(CONFIG_FSL_DDR3)
946 /* We need set BL/2 + 4 for BC4 or OTF */
947 rrt = 4; /* BL/2 + 4 clocks */
948 wwt = 4; /* BL/2 + 4 clocks */
949 dll_lock = 1; /* tDLLK = 512 clocks from spec */
951 ddr->timing_cfg_4 = (0
952 | ((rwt & 0xf) << 28)
953 | ((wrt & 0xf) << 24)
954 | ((rrt & 0xf) << 20)
955 | ((wwt & 0xf) << 16)
958 debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
961 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
962 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr)
964 unsigned int rodt_on = 0; /* Read to ODT on */
965 unsigned int rodt_off = 0; /* Read to ODT off */
966 unsigned int wodt_on = 0; /* Write to ODT on */
967 unsigned int wodt_off = 0; /* Write to ODT off */
969 #if defined(CONFIG_FSL_DDR3)
970 rodt_on = 3; /* 2 clocks */
971 rodt_off = 4; /* 4 clocks */
972 wodt_on = 2; /* 1 clocks */
973 wodt_off = 4; /* 4 clocks */
976 ddr->timing_cfg_5 = (0
977 | ((rodt_on & 0x1f) << 24)
978 | ((rodt_off & 0x7) << 20)
979 | ((wodt_on & 0x1f) << 12)
980 | ((wodt_off & 0x7) << 8)
982 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
985 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
986 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
988 unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
989 /* Normal Operation Full Calibration Time (tZQoper) */
990 unsigned int zqoper = 0;
991 /* Normal Operation Short Calibration Time (tZQCS) */
992 unsigned int zqcs = 0;
995 zqinit = 9; /* 512 clocks */
996 zqoper = 8; /* 256 clocks */
997 zqcs = 6; /* 64 clocks */
1000 ddr->ddr_zq_cntl = (0
1001 | ((zq_en & 0x1) << 31)
1002 | ((zqinit & 0xF) << 24)
1003 | ((zqoper & 0xF) << 16)
1004 | ((zqcs & 0xF) << 8)
1008 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
1009 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
1010 const memctl_options_t *popts)
1013 * First DQS pulse rising edge after margining mode
1014 * is programmed (tWL_MRD)
1016 unsigned int wrlvl_mrd = 0;
1017 /* ODT delay after margining mode is programmed (tWL_ODTEN) */
1018 unsigned int wrlvl_odten = 0;
1019 /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
1020 unsigned int wrlvl_dqsen = 0;
1021 /* WRLVL_SMPL: Write leveling sample time */
1022 unsigned int wrlvl_smpl = 0;
1023 /* WRLVL_WLR: Write leveling repeition time */
1024 unsigned int wrlvl_wlr = 0;
1025 /* WRLVL_START: Write leveling start time */
1026 unsigned int wrlvl_start = 0;
1028 /* suggest enable write leveling for DDR3 due to fly-by topology */
1030 /* tWL_MRD min = 40 nCK, we set it 64 */
1034 /* tWL_DQSEN min = 25 nCK, we set it 32 */
1037 * Write leveling sample time at least need 6 clocks
1038 * higher than tWLO to allow enough time for progagation
1039 * delay and sampling the prime data bits.
1043 * Write leveling repetition time
1044 * at least tWLO + 6 clocks clocks
1049 * Write leveling start time
1050 * The value use for the DQS_ADJUST for the first sample
1051 * when write leveling is enabled.
1055 * Override the write leveling sample and start time
1056 * according to specific board
1058 if (popts->wrlvl_override) {
1059 wrlvl_smpl = popts->wrlvl_sample;
1060 wrlvl_start = popts->wrlvl_start;
1064 ddr->ddr_wrlvl_cntl = (0
1065 | ((wrlvl_en & 0x1) << 31)
1066 | ((wrlvl_mrd & 0x7) << 24)
1067 | ((wrlvl_odten & 0x7) << 20)
1068 | ((wrlvl_dqsen & 0x7) << 16)
1069 | ((wrlvl_smpl & 0xf) << 12)
1070 | ((wrlvl_wlr & 0x7) << 8)
1071 | ((wrlvl_start & 0x1F) << 0)
1075 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
1076 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
1078 /* Self Refresh Idle Threshold */
1079 ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
1082 /* DDR SDRAM Register Control Word 1 (DDR_SDRAM_RCW_1) */
1083 static void set_ddr_sdram_rcw_1(fsl_ddr_cfg_regs_t *ddr)
1085 unsigned int rcw0 = 0; /* RCW0: Register Control Word 0 */
1086 unsigned int rcw1 = 0; /* RCW1: Register Control Word 1 */
1087 unsigned int rcw2 = 0; /* RCW2: Register Control Word 2 */
1088 unsigned int rcw3 = 0; /* RCW3: Register Control Word 3 */
1089 unsigned int rcw4 = 0; /* RCW4: Register Control Word 4 */
1090 unsigned int rcw5 = 0; /* RCW5: Register Control Word 5 */
1091 unsigned int rcw6 = 0; /* RCW6: Register Control Word 6 */
1092 unsigned int rcw7 = 0; /* RCW7: Register Control Word 7 */
1094 ddr->ddr_sdram_rcw_1 = (0
1095 | ((rcw0 & 0xF) << 28)
1096 | ((rcw1 & 0xF) << 24)
1097 | ((rcw2 & 0xF) << 20)
1098 | ((rcw3 & 0xF) << 16)
1099 | ((rcw4 & 0xF) << 12)
1100 | ((rcw5 & 0xF) << 8)
1101 | ((rcw6 & 0xF) << 4)
1102 | ((rcw7 & 0xF) << 0)
1106 /* DDR SDRAM Register Control Word 2 (DDR_SDRAM_RCW_2) */
1107 static void set_ddr_sdram_rcw_2(fsl_ddr_cfg_regs_t *ddr)
1109 unsigned int rcw8 = 0; /* RCW0: Register Control Word 8 */
1110 unsigned int rcw9 = 0; /* RCW1: Register Control Word 9 */
1111 unsigned int rcw10 = 0; /* RCW2: Register Control Word 10 */
1112 unsigned int rcw11 = 0; /* RCW3: Register Control Word 11 */
1113 unsigned int rcw12 = 0; /* RCW4: Register Control Word 12 */
1114 unsigned int rcw13 = 0; /* RCW5: Register Control Word 13 */
1115 unsigned int rcw14 = 0; /* RCW6: Register Control Word 14 */
1116 unsigned int rcw15 = 0; /* RCW7: Register Control Word 15 */
1118 ddr->ddr_sdram_rcw_2 = (0
1119 | ((rcw8 & 0xF) << 28)
1120 | ((rcw9 & 0xF) << 24)
1121 | ((rcw10 & 0xF) << 20)
1122 | ((rcw11 & 0xF) << 16)
1123 | ((rcw12 & 0xF) << 12)
1124 | ((rcw13 & 0xF) << 8)
1125 | ((rcw14 & 0xF) << 4)
1126 | ((rcw15 & 0xF) << 0)
1131 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
1133 unsigned int res = 0;
1136 * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
1137 * not set at the same time.
1139 if (ddr->ddr_sdram_cfg & 0x10000000
1140 && ddr->ddr_sdram_cfg & 0x00008000) {
1141 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
1142 " should not be set at the same time.\n");
1150 compute_fsl_memctl_config_regs(const memctl_options_t *popts,
1151 fsl_ddr_cfg_regs_t *ddr,
1152 const common_timing_params_t *common_dimm,
1153 const dimm_params_t *dimm_params,
1154 unsigned int dbw_cap_adj)
1157 unsigned int cas_latency;
1158 unsigned int additive_latency;
1161 unsigned int wrlvl_en;
1163 memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
1165 if (common_dimm == NULL) {
1166 printf("Error: subset DIMM params struct null pointer\n");
1171 * Process overrides first.
1173 * FIXME: somehow add dereated caslat to this
1175 cas_latency = (popts->cas_latency_override)
1176 ? popts->cas_latency_override_value
1177 : common_dimm->lowest_common_SPD_caslat;
1179 additive_latency = (popts->additive_latency_override)
1180 ? popts->additive_latency_override_value
1181 : common_dimm->additive_latency;
1183 sr_it = (popts->auto_self_refresh_en)
1186 /* ZQ calibration */
1187 zq_en = (popts->zq_en) ? 1 : 0;
1188 /* write leveling */
1189 wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
1191 /* Chip Select Memory Bounds (CSn_BNDS) */
1192 for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1193 unsigned long long ea = 0, sa = 0;
1195 if (popts->ba_intlv_ctl && (i > 0) &&
1196 ((popts->ba_intlv_ctl & 0x60) != FSL_DDR_CS2_CS3 )) {
1197 /* Don't set up boundaries for other CS
1198 * other than CS0, if bank interleaving
1199 * is enabled and not CS2+CS3 interleaved.
1200 * But we need to set the ODT_RD_CFG and
1201 * ODT_WR_CFG for CS1_CONFIG here.
1203 set_csn_config(i, ddr, popts, dimm_params);
1207 if (dimm_params[i/2].n_ranks == 0) {
1208 debug("Skipping setup of CS%u "
1209 "because n_ranks on DIMM %u is 0\n", i, i/2);
1212 if (popts->memctl_interleaving && popts->ba_intlv_ctl) {
1214 * This works superbank 2CS
1215 * There are 2 memory controllers configured
1216 * identically, memory is interleaved between them,
1217 * and each controller uses rank interleaving within
1218 * itself. Therefore the starting and ending address
1219 * on each controller is twice the amount present on
1222 unsigned long long rank_density
1223 = dimm_params[0].capacity;
1224 ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
1226 else if (!popts->memctl_interleaving && popts->ba_intlv_ctl) {
1228 * If memory interleaving between controllers is NOT
1229 * enabled, the starting address for each memory
1230 * controller is distinct. However, because rank
1231 * interleaving is enabled, the starting and ending
1232 * addresses of the total memory on that memory
1233 * controller needs to be programmed into its
1234 * respective CS0_BNDS.
1236 unsigned long long rank_density
1237 = dimm_params[i/2].rank_density;
1238 switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
1239 case FSL_DDR_CS0_CS1_CS2_CS3:
1240 /* CS0+CS1+CS2+CS3 interleaving, only CS0_CNDS
1243 sa = common_dimm->base_address;
1244 ea = sa + (4 * (rank_density >> dbw_cap_adj))-1;
1246 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
1247 /* CS0+CS1 and CS2+CS3 interleaving, CS0_CNDS
1248 * and CS2_CNDS need to be set.
1251 sa = dimm_params[i/2].base_address;
1252 ea = sa + (i * (rank_density >>
1256 case FSL_DDR_CS0_CS1:
1257 /* CS0+CS1 interleaving, CS0_CNDS needs
1260 sa = common_dimm->base_address;
1261 ea = sa + (2 * (rank_density >> dbw_cap_adj))-1;
1263 case FSL_DDR_CS2_CS3:
1264 /* CS2+CS3 interleaving*/
1266 sa = dimm_params[i/2].base_address;
1267 ea = sa + (2 * (rank_density >>
1271 default: /* No bank(chip-select) interleaving */
1275 else if (popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1277 * Only the rank on CS0 of each memory controller may
1278 * be used if memory controller interleaving is used
1279 * without rank interleaving within each memory
1280 * controller. However, the ending address programmed
1281 * into each CS0 must be the sum of the amount of
1282 * memory in the two CS0 ranks.
1285 unsigned long long rank_density
1286 = dimm_params[0].rank_density;
1287 ea = (2 * (rank_density >> dbw_cap_adj)) - 1;
1291 else if (!popts->memctl_interleaving && !popts->ba_intlv_ctl) {
1293 * No rank interleaving and no memory controller
1296 unsigned long long rank_density
1297 = dimm_params[i/2].rank_density;
1298 sa = dimm_params[i/2].base_address;
1299 ea = sa + (rank_density >> dbw_cap_adj) - 1;
1301 if ((dimm_params[i/2].n_ranks == 1)) {
1302 /* Odd chip select, single-rank dimm */
1306 /* Odd chip select, dual-rank DIMM */
1307 sa += rank_density >> dbw_cap_adj;
1308 ea += rank_density >> dbw_cap_adj;
1316 ddr->cs[i].bnds = (0
1317 | ((sa & 0xFFF) << 16) /* starting address MSB */
1318 | ((ea & 0xFFF) << 0) /* ending address MSB */
1321 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
1322 set_csn_config(i, ddr, popts, dimm_params);
1323 set_csn_config_2(i, ddr);
1326 #if !defined(CONFIG_FSL_DDR1)
1327 set_timing_cfg_0(ddr);
1330 set_timing_cfg_3(ddr, common_dimm, cas_latency);
1331 set_timing_cfg_1(ddr, popts, common_dimm, cas_latency);
1332 set_timing_cfg_2(ddr, popts, common_dimm,
1333 cas_latency, additive_latency);
1335 set_ddr_sdram_cfg(ddr, popts, common_dimm);
1337 set_ddr_sdram_cfg_2(ddr, popts);
1338 set_ddr_sdram_mode(ddr, popts, common_dimm,
1339 cas_latency, additive_latency);
1340 set_ddr_sdram_mode_2(ddr, popts);
1341 set_ddr_sdram_interval(ddr, popts, common_dimm);
1342 set_ddr_data_init(ddr);
1343 set_ddr_sdram_clk_cntl(ddr, popts);
1344 set_ddr_init_addr(ddr);
1345 set_ddr_init_ext_addr(ddr);
1346 set_timing_cfg_4(ddr);
1347 set_timing_cfg_5(ddr);
1349 set_ddr_zq_cntl(ddr, zq_en);
1350 set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
1352 set_ddr_sr_cntr(ddr, sr_it);
1354 set_ddr_sdram_rcw_1(ddr);
1355 set_ddr_sdram_rcw_2(ddr);
1357 return check_fsl_memctl_config_regs(ddr);