3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 DECLARE_GLOBAL_DATA_PTR;
32 #if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */
34 #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
36 #define PROFF_SMC PROFF_SMC1
37 #define CPM_CR_CH_SMC CPM_CR_CH_SMC1
39 #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
41 #define PROFF_SMC PROFF_SMC2
42 #define CPM_CR_CH_SMC CPM_CR_CH_SMC2
44 #endif /* CONFIG_8xx_CONS_SMCx */
46 #if defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */
48 #define PROFF_SCC PROFF_SCC1
49 #define CPM_CR_CH_SCC CPM_CR_CH_SCC1
51 #elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */
53 #define PROFF_SCC PROFF_SCC2
54 #define CPM_CR_CH_SCC CPM_CR_CH_SCC2
56 #elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */
58 #define PROFF_SCC PROFF_SCC3
59 #define CPM_CR_CH_SCC CPM_CR_CH_SCC3
61 #elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */
63 #define PROFF_SCC PROFF_SCC4
64 #define CPM_CR_CH_SCC CPM_CR_CH_SCC4
66 #endif /* CONFIG_8xx_CONS_SCCx */
68 static void serial_setdivisor(volatile cpm8xx_t *cp)
70 int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
72 if(divisor/16>0x1000) {
73 /* bad divisor, assume 50Mhz clock and 9600 baud */
74 divisor=(50*1000*1000 + 8*9600)/16/9600;
77 #ifdef CFG_BRGCLK_PRESCALE
78 divisor /= CFG_BRGCLK_PRESCALE;
82 cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
84 cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
88 #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
91 * Minimal serial functions needed to use one of the SMC ports
92 * as serial console interface.
95 static void smc_setbrg (void)
97 volatile immap_t *im = (immap_t *)CFG_IMMR;
98 volatile cpm8xx_t *cp = &(im->im_cpm);
100 /* Set up the baud rate generator.
101 * See 8xx_io/commproc.c for details.
106 cp->cp_simode = 0x00000000;
108 serial_setdivisor(cp);
111 static int smc_init (void)
113 volatile immap_t *im = (immap_t *)CFG_IMMR;
115 volatile smc_uart_t *up;
116 volatile cbd_t *tbdf, *rbdf;
117 volatile cpm8xx_t *cp = &(im->im_cpm);
118 #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
119 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
123 /* initialize pointers to SMC */
125 sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
126 up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
128 /* Disable transmitter/receiver.
130 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
134 im->im_siu_conf.sc_sdcr = 1;
136 /* clear error conditions */
138 im->im_sdma.sdma_sdsr = CFG_SDSR;
140 im->im_sdma.sdma_sdsr = 0x83;
143 /* clear SDMA interrupt mask */
145 im->im_sdma.sdma_sdmr = CFG_SDMR;
147 im->im_sdma.sdma_sdmr = 0x00;
150 #if defined(CONFIG_8xx_CONS_SMC1)
151 /* Use Port B for SMC1 instead of other functions.
153 cp->cp_pbpar |= 0x000000c0;
154 cp->cp_pbdir &= ~0x000000c0;
155 cp->cp_pbodr &= ~0x000000c0;
156 #else /* CONFIG_8xx_CONS_SMC2 */
157 # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
158 /* Use Port A for SMC2 instead of other functions.
160 ip->iop_papar |= 0x00c0;
161 ip->iop_padir &= ~0x00c0;
162 ip->iop_paodr &= ~0x00c0;
163 # else /* must be a 860 then */
164 /* Use Port B for SMC2 instead of other functions.
166 cp->cp_pbpar |= 0x00000c00;
167 cp->cp_pbdir &= ~0x00000c00;
168 cp->cp_pbodr &= ~0x00000c00;
172 #if defined(CONFIG_FADS) || defined(CONFIG_ADS)
174 #if defined(CONFIG_8xx_CONS_SMC1)
175 *((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
177 *((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
179 #endif /* CONFIG_FADS */
181 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
182 /* Enable Monitor Port Transceiver */
183 *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
184 #endif /* CONFIG_RPXLITE */
186 /* Set the physical address of the host memory buffers in
187 * the buffer descriptors.
190 #ifdef CFG_ALLOC_DPRAM
191 dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
193 dpaddr = CPM_SERIAL_BASE ;
196 /* Allocate space for two buffer descriptors in the DP ram.
197 * For now, this address seems OK, but it may have to
198 * change with newer versions of the firmware.
199 * damm: allocating space after the two buffers for rx/tx data
202 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
203 rbdf->cbd_bufaddr = (uint) (rbdf+2);
206 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
209 /* Set up the uart parameters in the parameter ram.
211 up->smc_rbase = dpaddr;
212 up->smc_tbase = dpaddr+sizeof(cbd_t);
213 up->smc_rfcr = SMC_EB;
214 up->smc_tfcr = SMC_EB;
216 #if defined(CONFIG_MBX)
218 #endif /* CONFIG_MBX */
220 /* Set UART mode, 8 bit, no parity, one stop.
221 * Enable receive and transmit.
223 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
225 /* Mask all interrupts and remove anything pending.
230 /* Set up the baud rate generator.
234 /* Make the first buffer the only buffer.
236 tbdf->cbd_sc |= BD_SC_WRAP;
237 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
239 /* Single character receive.
244 /* Initialize Tx/Rx parameters.
247 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
250 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
252 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
255 /* Enable transmitter/receiver.
257 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
263 smc_putc(const char c)
265 volatile cbd_t *tbdf;
267 volatile smc_uart_t *up;
268 volatile immap_t *im = (immap_t *)CFG_IMMR;
269 volatile cpm8xx_t *cpmp = &(im->im_cpm);
271 #ifdef CONFIG_MODEM_SUPPORT
279 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
281 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
283 /* Wait for last character to go.
286 buf = (char *)tbdf->cbd_bufaddr;
289 tbdf->cbd_datlen = 1;
290 tbdf->cbd_sc |= BD_SC_READY;
293 while (tbdf->cbd_sc & BD_SC_READY) {
300 smc_puts (const char *s)
310 volatile cbd_t *rbdf;
311 volatile unsigned char *buf;
312 volatile smc_uart_t *up;
313 volatile immap_t *im = (immap_t *)CFG_IMMR;
314 volatile cpm8xx_t *cpmp = &(im->im_cpm);
317 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
319 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
321 /* Wait for character to show up.
323 buf = (unsigned char *)rbdf->cbd_bufaddr;
325 while (rbdf->cbd_sc & BD_SC_EMPTY)
329 rbdf->cbd_sc |= BD_SC_EMPTY;
337 volatile cbd_t *rbdf;
338 volatile smc_uart_t *up;
339 volatile immap_t *im = (immap_t *)CFG_IMMR;
340 volatile cpm8xx_t *cpmp = &(im->im_cpm);
342 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
344 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
346 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
349 struct serial_device serial_smc_device =
361 #endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */
363 #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
364 defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
369 volatile immap_t *im = (immap_t *)CFG_IMMR;
370 volatile cpm8xx_t *cp = &(im->im_cpm);
372 /* Set up the baud rate generator.
373 * See 8xx_io/commproc.c for details.
378 cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
380 serial_setdivisor(cp);
383 static int scc_init (void)
385 volatile immap_t *im = (immap_t *)CFG_IMMR;
387 volatile scc_uart_t *up;
388 volatile cbd_t *tbdf, *rbdf;
389 volatile cpm8xx_t *cp = &(im->im_cpm);
391 #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
392 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
395 /* initialize pointers to SCC */
397 sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
398 up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
400 #if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
401 { /* Disable Ethernet, enable Serial */
405 c &= ~0x40; /* enable COM3 */
406 c |= 0x80; /* disable Ethernet */
410 cp->cp_pbpar |= 0x2000;
411 cp->cp_pbdat |= 0x2000;
412 cp->cp_pbdir |= 0x2000;
414 #endif /* CONFIG_LWMON */
416 /* Disable transmitter/receiver.
418 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
420 #if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
422 * The MPC850 has SCC3 on Port B
424 cp->cp_pbpar |= 0x06;
425 cp->cp_pbdir &= ~0x06;
426 cp->cp_pbodr &= ~0x06;
428 #elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
430 * Standard configuration for SCC's is on Part A
432 ip->iop_papar |= ((3 << (2 * SCC_INDEX)));
433 ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
434 ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
437 * The IP860 has SCC3 and SCC4 on Port D
439 ip->iop_pdpar |= ((3 << (2 * SCC_INDEX)));
442 /* Allocate space for two buffer descriptors in the DP ram.
445 #ifdef CFG_ALLOC_DPRAM
446 dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
448 dpaddr = CPM_SERIAL2_BASE ;
453 im->im_siu_conf.sc_sdcr = 0x0001;
455 /* Set the physical address of the host memory buffers in
456 * the buffer descriptors.
459 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
460 rbdf->cbd_bufaddr = (uint) (rbdf+2);
463 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
466 /* Set up the baud rate generator.
470 /* Set up the uart parameters in the parameter ram.
472 up->scc_genscc.scc_rbase = dpaddr;
473 up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
475 /* Initialize Tx/Rx parameters.
477 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
479 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
481 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
484 up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
485 up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
487 up->scc_genscc.scc_mrblr = 1; /* Single character receive */
488 up->scc_maxidl = 0; /* disable max idle */
489 up->scc_brkcr = 1; /* send one break character on stop TX */
497 up->scc_char1 = 0x8000;
498 up->scc_char2 = 0x8000;
499 up->scc_char3 = 0x8000;
500 up->scc_char4 = 0x8000;
501 up->scc_char5 = 0x8000;
502 up->scc_char6 = 0x8000;
503 up->scc_char7 = 0x8000;
504 up->scc_char8 = 0x8000;
505 up->scc_rccm = 0xc0ff;
507 /* Set low latency / small fifo.
509 sp->scc_gsmrh = SCC_GSMRH_RFW;
511 /* Set SCC(x) clock mode to 16x
512 * See 8xx_io/commproc.c for details.
517 /* Set UART mode, clock divider 16 on Tx and Rx
519 sp->scc_gsmrl &= ~0xF;
521 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
524 sp->scc_psmr |= SCU_PSMR_CL;
526 /* Mask all interrupts and remove anything pending.
529 sp->scc_scce = 0xffff;
530 sp->scc_dsr = 0x7e7e;
531 sp->scc_psmr = 0x3000;
533 /* Make the first buffer the only buffer.
535 tbdf->cbd_sc |= BD_SC_WRAP;
536 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
538 /* Enable transmitter/receiver.
540 sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
546 scc_putc(const char c)
548 volatile cbd_t *tbdf;
550 volatile scc_uart_t *up;
551 volatile immap_t *im = (immap_t *)CFG_IMMR;
552 volatile cpm8xx_t *cpmp = &(im->im_cpm);
554 #ifdef CONFIG_MODEM_SUPPORT
562 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
564 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
566 /* Wait for last character to go.
569 buf = (char *)tbdf->cbd_bufaddr;
572 tbdf->cbd_datlen = 1;
573 tbdf->cbd_sc |= BD_SC_READY;
576 while (tbdf->cbd_sc & BD_SC_READY) {
583 scc_puts (const char *s)
593 volatile cbd_t *rbdf;
594 volatile unsigned char *buf;
595 volatile scc_uart_t *up;
596 volatile immap_t *im = (immap_t *)CFG_IMMR;
597 volatile cpm8xx_t *cpmp = &(im->im_cpm);
600 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
602 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
604 /* Wait for character to show up.
606 buf = (unsigned char *)rbdf->cbd_bufaddr;
608 while (rbdf->cbd_sc & BD_SC_EMPTY)
612 rbdf->cbd_sc |= BD_SC_EMPTY;
620 volatile cbd_t *rbdf;
621 volatile scc_uart_t *up;
622 volatile immap_t *im = (immap_t *)CFG_IMMR;
623 volatile cpm8xx_t *cpmp = &(im->im_cpm);
625 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
627 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
629 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
632 struct serial_device serial_scc_device =
644 #endif /* CONFIG_8xx_CONS_SCCx */
646 #ifdef CONFIG_MODEM_SUPPORT
647 void disable_putc(void)
652 void enable_putc(void)
658 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
661 kgdb_serial_init(void)
665 if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
667 #if defined(CONFIG_8xx_CONS_SMC1)
669 #elif defined(CONFIG_8xx_CONS_SMC2)
673 else if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
675 #if defined(CONFIG_8xx_CONS_SCC1)
677 #elif defined(CONFIG_8xx_CONS_SCC2)
679 #elif defined(CONFIG_8xx_CONS_SCC3)
681 #elif defined(CONFIG_8xx_CONS_SCC4)
688 serial_printf("[on %s%d] ", default_serial_console()->ctlr, i);
699 putDebugStr (const char *str)
707 return serial_getc();
711 kgdb_interruptible (int yes)
715 #endif /* CFG_CMD_KGDB */
717 #endif /* CONFIG_8xx_CONS_NONE */