3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 DECLARE_GLOBAL_DATA_PTR;
32 #if !defined(CONFIG_8xx_CONS_NONE) /* No Console at all */
34 #if defined(CONFIG_8xx_CONS_SMC1) /* Console on SMC1 */
36 #define PROFF_SMC PROFF_SMC1
37 #define CPM_CR_CH_SMC CPM_CR_CH_SMC1
39 #elif defined(CONFIG_8xx_CONS_SMC2) /* Console on SMC2 */
41 #define PROFF_SMC PROFF_SMC2
42 #define CPM_CR_CH_SMC CPM_CR_CH_SMC2
44 #endif /* CONFIG_8xx_CONS_SMCx */
46 #if defined(CONFIG_8xx_CONS_SCC1) /* Console on SCC1 */
48 #define PROFF_SCC PROFF_SCC1
49 #define CPM_CR_CH_SCC CPM_CR_CH_SCC1
51 #elif defined(CONFIG_8xx_CONS_SCC2) /* Console on SCC2 */
53 #define PROFF_SCC PROFF_SCC2
54 #define CPM_CR_CH_SCC CPM_CR_CH_SCC2
56 #elif defined(CONFIG_8xx_CONS_SCC3) /* Console on SCC3 */
58 #define PROFF_SCC PROFF_SCC3
59 #define CPM_CR_CH_SCC CPM_CR_CH_SCC3
61 #elif defined(CONFIG_8xx_CONS_SCC4) /* Console on SCC4 */
63 #define PROFF_SCC PROFF_SCC4
64 #define CPM_CR_CH_SCC CPM_CR_CH_SCC4
66 #endif /* CONFIG_8xx_CONS_SCCx */
68 static void serial_setdivisor(volatile cpm8xx_t *cp)
70 int divisor=(gd->cpu_clk + 8*gd->baudrate)/16/gd->baudrate;
72 if(divisor/16>0x1000) {
73 /* bad divisor, assume 50Mhz clock and 9600 baud */
74 divisor=(50*1000*1000 + 8*9600)/16/9600;
77 #ifdef CFG_BRGCLK_PRESCALE
78 divisor /= CFG_BRGCLK_PRESCALE;
82 cp->cp_brgc1=((divisor-1)<<1) | CPM_BRG_EN;
84 cp->cp_brgc1=((divisor/16-1)<<1) | CPM_BRG_EN | CPM_BRG_DIV16;
88 #if (defined (CONFIG_8xx_CONS_SMC1) || defined (CONFIG_8xx_CONS_SMC2))
91 * Minimal serial functions needed to use one of the SMC ports
92 * as serial console interface.
95 static void smc_setbrg (void)
97 volatile immap_t *im = (immap_t *)CFG_IMMR;
98 volatile cpm8xx_t *cp = &(im->im_cpm);
100 /* Set up the baud rate generator.
101 * See 8xx_io/commproc.c for details.
106 cp->cp_simode = 0x00000000;
108 serial_setdivisor(cp);
111 static int smc_init (void)
113 volatile immap_t *im = (immap_t *)CFG_IMMR;
115 volatile smc_uart_t *up;
116 volatile cbd_t *tbdf, *rbdf;
117 volatile cpm8xx_t *cp = &(im->im_cpm);
118 #if (!defined(CONFIG_8xx_CONS_SMC1)) && (defined(CONFIG_MPC823) || defined(CONFIG_MPC850))
119 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
123 /* initialize pointers to SMC */
125 sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
126 up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
128 /* Disable transmitter/receiver.
130 sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
134 im->im_siu_conf.sc_sdcr = 1;
136 /* clear error conditions */
138 im->im_sdma.sdma_sdsr = CFG_SDSR;
140 im->im_sdma.sdma_sdsr = 0x83;
143 /* clear SDMA interrupt mask */
145 im->im_sdma.sdma_sdmr = CFG_SDMR;
147 im->im_sdma.sdma_sdmr = 0x00;
150 #if defined(CONFIG_8xx_CONS_SMC1)
151 /* Use Port B for SMC1 instead of other functions.
153 cp->cp_pbpar |= 0x000000c0;
154 cp->cp_pbdir &= ~0x000000c0;
155 cp->cp_pbodr &= ~0x000000c0;
156 #else /* CONFIG_8xx_CONS_SMC2 */
157 # if defined(CONFIG_MPC823) || defined(CONFIG_MPC850)
158 /* Use Port A for SMC2 instead of other functions.
160 ip->iop_papar |= 0x00c0;
161 ip->iop_padir &= ~0x00c0;
162 ip->iop_paodr &= ~0x00c0;
163 # else /* must be a 860 then */
164 /* Use Port B for SMC2 instead of other functions.
166 cp->cp_pbpar |= 0x00000c00;
167 cp->cp_pbdir &= ~0x00000c00;
168 cp->cp_pbodr &= ~0x00000c00;
172 #if defined(CONFIG_FADS) || defined(CONFIG_ADS)
174 #if defined(CONFIG_8xx_CONS_SMC1)
175 *((uint *) BCSR1) &= ~BCSR1_RS232EN_1;
177 *((uint *) BCSR1) &= ~BCSR1_RS232EN_2;
179 #endif /* CONFIG_FADS */
181 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
182 /* Enable Monitor Port Transceiver */
183 *((uchar *) BCSR0) |= BCSR0_ENMONXCVR ;
184 #endif /* CONFIG_RPXLITE */
186 /* Set the physical address of the host memory buffers in
187 * the buffer descriptors.
190 #ifdef CFG_ALLOC_DPRAM
191 dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
193 dpaddr = CPM_SERIAL_BASE ;
196 /* Allocate space for two buffer descriptors in the DP ram.
197 * For now, this address seems OK, but it may have to
198 * change with newer versions of the firmware.
199 * damm: allocating space after the two buffers for rx/tx data
202 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
203 rbdf->cbd_bufaddr = (uint) (rbdf+2);
206 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
209 /* Set up the uart parameters in the parameter ram.
211 up->smc_rbase = dpaddr;
212 up->smc_tbase = dpaddr+sizeof(cbd_t);
213 up->smc_rfcr = SMC_EB;
214 up->smc_tfcr = SMC_EB;
216 #if defined(CONFIG_MBX)
218 #endif /* CONFIG_MBX */
220 /* Set UART mode, 8 bit, no parity, one stop.
221 * Enable receive and transmit.
223 sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
225 /* Mask all interrupts and remove anything pending.
230 #ifdef CFG_SPC1920_SMC1_CLK4 /* clock source is PLD */
231 *((volatile uchar *) CFG_SPC1920_PLD_BASE+6) = 0xff;
233 /* Set up the baud rate generator */
237 /* Make the first buffer the only buffer.
239 tbdf->cbd_sc |= BD_SC_WRAP;
240 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
242 /* Single character receive.
247 /* Initialize Tx/Rx parameters.
250 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
253 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
255 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
258 /* Enable transmitter/receiver.
260 sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
266 smc_putc(const char c)
268 volatile cbd_t *tbdf;
270 volatile smc_uart_t *up;
271 volatile immap_t *im = (immap_t *)CFG_IMMR;
272 volatile cpm8xx_t *cpmp = &(im->im_cpm);
274 #ifdef CONFIG_MODEM_SUPPORT
282 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
284 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
286 /* Wait for last character to go.
289 buf = (char *)tbdf->cbd_bufaddr;
292 tbdf->cbd_datlen = 1;
293 tbdf->cbd_sc |= BD_SC_READY;
296 while (tbdf->cbd_sc & BD_SC_READY) {
303 smc_puts (const char *s)
313 volatile cbd_t *rbdf;
314 volatile unsigned char *buf;
315 volatile smc_uart_t *up;
316 volatile immap_t *im = (immap_t *)CFG_IMMR;
317 volatile cpm8xx_t *cpmp = &(im->im_cpm);
320 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
322 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
324 /* Wait for character to show up.
326 buf = (unsigned char *)rbdf->cbd_bufaddr;
328 while (rbdf->cbd_sc & BD_SC_EMPTY)
332 rbdf->cbd_sc |= BD_SC_EMPTY;
340 volatile cbd_t *rbdf;
341 volatile smc_uart_t *up;
342 volatile immap_t *im = (immap_t *)CFG_IMMR;
343 volatile cpm8xx_t *cpmp = &(im->im_cpm);
345 up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
347 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
349 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
352 struct serial_device serial_smc_device =
364 #endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */
366 #if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
367 defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
372 volatile immap_t *im = (immap_t *)CFG_IMMR;
373 volatile cpm8xx_t *cp = &(im->im_cpm);
375 /* Set up the baud rate generator.
376 * See 8xx_io/commproc.c for details.
381 cp->cp_sicr &= ~(0x000000FF << (8 * SCC_INDEX));
383 serial_setdivisor(cp);
386 static int scc_init (void)
388 volatile immap_t *im = (immap_t *)CFG_IMMR;
390 volatile scc_uart_t *up;
391 volatile cbd_t *tbdf, *rbdf;
392 volatile cpm8xx_t *cp = &(im->im_cpm);
394 #if (SCC_INDEX != 2) || !defined(CONFIG_MPC850)
395 volatile iop8xx_t *ip = (iop8xx_t *)&(im->im_ioport);
398 /* initialize pointers to SCC */
400 sp = (scc_t *) &(cp->cp_scc[SCC_INDEX]);
401 up = (scc_uart_t *) &cp->cp_dparam[PROFF_SCC];
403 #if defined(CONFIG_LWMON) && defined(CONFIG_8xx_CONS_SCC2)
404 { /* Disable Ethernet, enable Serial */
408 c &= ~0x40; /* enable COM3 */
409 c |= 0x80; /* disable Ethernet */
413 cp->cp_pbpar |= 0x2000;
414 cp->cp_pbdat |= 0x2000;
415 cp->cp_pbdir |= 0x2000;
417 #endif /* CONFIG_LWMON */
419 /* Disable transmitter/receiver.
421 sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
423 #if (SCC_INDEX == 2) && defined(CONFIG_MPC850)
425 * The MPC850 has SCC3 on Port B
427 cp->cp_pbpar |= 0x06;
428 cp->cp_pbdir &= ~0x06;
429 cp->cp_pbodr &= ~0x06;
431 #elif (SCC_INDEX < 2) || !defined(CONFIG_IP860)
433 * Standard configuration for SCC's is on Part A
435 ip->iop_papar |= ((3 << (2 * SCC_INDEX)));
436 ip->iop_padir &= ~((3 << (2 * SCC_INDEX)));
437 ip->iop_paodr &= ~((3 << (2 * SCC_INDEX)));
440 * The IP860 has SCC3 and SCC4 on Port D
442 ip->iop_pdpar |= ((3 << (2 * SCC_INDEX)));
445 /* Allocate space for two buffer descriptors in the DP ram.
448 #ifdef CFG_ALLOC_DPRAM
449 dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
451 dpaddr = CPM_SERIAL2_BASE ;
456 im->im_siu_conf.sc_sdcr = 0x0001;
458 /* Set the physical address of the host memory buffers in
459 * the buffer descriptors.
462 rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
463 rbdf->cbd_bufaddr = (uint) (rbdf+2);
466 tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
469 /* Set up the baud rate generator.
473 /* Set up the uart parameters in the parameter ram.
475 up->scc_genscc.scc_rbase = dpaddr;
476 up->scc_genscc.scc_tbase = dpaddr+sizeof(cbd_t);
478 /* Initialize Tx/Rx parameters.
480 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
482 cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SCC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
484 while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
487 up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
488 up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
490 up->scc_genscc.scc_mrblr = 1; /* Single character receive */
491 up->scc_maxidl = 0; /* disable max idle */
492 up->scc_brkcr = 1; /* send one break character on stop TX */
500 up->scc_char1 = 0x8000;
501 up->scc_char2 = 0x8000;
502 up->scc_char3 = 0x8000;
503 up->scc_char4 = 0x8000;
504 up->scc_char5 = 0x8000;
505 up->scc_char6 = 0x8000;
506 up->scc_char7 = 0x8000;
507 up->scc_char8 = 0x8000;
508 up->scc_rccm = 0xc0ff;
510 /* Set low latency / small fifo.
512 sp->scc_gsmrh = SCC_GSMRH_RFW;
514 /* Set SCC(x) clock mode to 16x
515 * See 8xx_io/commproc.c for details.
520 /* Set UART mode, clock divider 16 on Tx and Rx
522 sp->scc_gsmrl &= ~0xF;
524 (SCC_GSMRL_MODE_UART | SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
527 sp->scc_psmr |= SCU_PSMR_CL;
529 /* Mask all interrupts and remove anything pending.
532 sp->scc_scce = 0xffff;
533 sp->scc_dsr = 0x7e7e;
534 sp->scc_psmr = 0x3000;
536 /* Make the first buffer the only buffer.
538 tbdf->cbd_sc |= BD_SC_WRAP;
539 rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
541 /* Enable transmitter/receiver.
543 sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
549 scc_putc(const char c)
551 volatile cbd_t *tbdf;
553 volatile scc_uart_t *up;
554 volatile immap_t *im = (immap_t *)CFG_IMMR;
555 volatile cpm8xx_t *cpmp = &(im->im_cpm);
557 #ifdef CONFIG_MODEM_SUPPORT
565 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
567 tbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
569 /* Wait for last character to go.
572 buf = (char *)tbdf->cbd_bufaddr;
575 tbdf->cbd_datlen = 1;
576 tbdf->cbd_sc |= BD_SC_READY;
579 while (tbdf->cbd_sc & BD_SC_READY) {
586 scc_puts (const char *s)
596 volatile cbd_t *rbdf;
597 volatile unsigned char *buf;
598 volatile scc_uart_t *up;
599 volatile immap_t *im = (immap_t *)CFG_IMMR;
600 volatile cpm8xx_t *cpmp = &(im->im_cpm);
603 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
605 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
607 /* Wait for character to show up.
609 buf = (unsigned char *)rbdf->cbd_bufaddr;
611 while (rbdf->cbd_sc & BD_SC_EMPTY)
615 rbdf->cbd_sc |= BD_SC_EMPTY;
623 volatile cbd_t *rbdf;
624 volatile scc_uart_t *up;
625 volatile immap_t *im = (immap_t *)CFG_IMMR;
626 volatile cpm8xx_t *cpmp = &(im->im_cpm);
628 up = (scc_uart_t *)&cpmp->cp_dparam[PROFF_SCC];
630 rbdf = (cbd_t *)&cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
632 return(!(rbdf->cbd_sc & BD_SC_EMPTY));
635 struct serial_device serial_scc_device =
647 #endif /* CONFIG_8xx_CONS_SCCx */
649 #ifdef CONFIG_MODEM_SUPPORT
650 void disable_putc(void)
655 void enable_putc(void)
661 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
664 kgdb_serial_init(void)
668 if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
670 #if defined(CONFIG_8xx_CONS_SMC1)
672 #elif defined(CONFIG_8xx_CONS_SMC2)
676 else if (strcmp(default_serial_console()->ctlr, "SMC") == 0)
678 #if defined(CONFIG_8xx_CONS_SCC1)
680 #elif defined(CONFIG_8xx_CONS_SCC2)
682 #elif defined(CONFIG_8xx_CONS_SCC3)
684 #elif defined(CONFIG_8xx_CONS_SCC4)
691 serial_printf("[on %s%d] ", default_serial_console()->ctlr, i);
702 putDebugStr (const char *str)
710 return serial_getc();
714 kgdb_interruptible (int yes)
718 #endif /* CFG_CMD_KGDB */
720 #endif /* CONFIG_8xx_CONS_NONE */