2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
32 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
33 extern void dma_init(void);
34 extern uint dma_check(void);
35 extern int dma_xfer(void *dest, uint count, void *src);
38 #ifdef CONFIG_SPD_EEPROM
41 #define CFG_READ_SPD i2c_read
45 * Only one of the following three should be 1; others should be 0
46 * By default the cache line interleaving is selected if
47 * the CONFIG_DDR_INTERLEAVE flag is defined in MPC8641HPCN.h
49 #define CFG_PAGE_INTERLEAVING 0
50 #define CFG_BANK_INTERLEAVING 0
51 #define CFG_SUPER_BANK_INTERLEAVING 0
54 * Convert picoseconds into clock cycles (rounding up if needed).
58 picos_to_clk(int picos)
62 clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
63 if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
72 * Calculate the Density of each Physical Rank.
73 * Returned size is in bytes.
75 * Study these table from Byte 31 of JEDEC SPD Spec.
89 * Reorder Table to be linear by stripping the bottom
90 * 2 or 5 bits off and shifting them up to the top.
94 compute_banksize(unsigned int mem_type, unsigned char row_dens)
98 if (mem_type == SPD_MEMTYPE_DDR) {
99 /* Bottom 2 bits up to the top. */
100 bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
101 debug("DDR: DDR I rank density = 0x%08x\n", bsize);
103 /* Bottom 5 bits up to the top. */
104 bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)) << 27;
105 debug("DDR: DDR II rank density = 0x%08x\n", bsize);
112 * Convert a two-nibble BCD value into a cycle time.
113 * While the spec calls for nano-seconds, picos are returned.
115 * This implements the tables for bytes 9, 23 and 25 for both
116 * DDR I and II. No allowance for distinguishing the invalid
117 * fields absent for DDR I yet present in DDR II is made.
118 * (That is, cycle times of .25, .33, .66 and .75 ns are
119 * allowed for both DDR II and I.)
123 convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
126 * Table look up the lower nibble, allow DDR I & II.
128 unsigned int tenths_ps[16] = {
140 330, /* FIXME: Is 333 better/valid? */
141 660, /* FIXME: Is 667 better/valid? */
147 unsigned int whole_ns = (spd_val & 0xF0) >> 4;
148 unsigned int tenth_ns = spd_val & 0x0F;
149 unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
156 spd_init(unsigned char i2c_address, unsigned int ddr_num,
157 unsigned int dimm_num, unsigned int start_addr)
159 volatile immap_t *immap = (immap_t *)CFG_IMMR;
160 volatile ccsr_ddr_t *ddr;
161 volatile ccsr_gur_t *gur = &immap->im_gur;
163 unsigned int n_ranks;
164 unsigned int rank_density;
165 unsigned int odt_rd_cfg, odt_wr_cfg;
166 unsigned int odt_cfg, mode_odt_enable;
167 unsigned int dqs_cfg;
168 unsigned char twr_clk, twtr_clk, twr_auto_clk;
169 unsigned int tCKmin_ps, tCKmax_ps;
170 unsigned int max_data_rate, effective_data_rate;
171 unsigned int busfreq;
172 unsigned sdram_cfg_1;
173 unsigned int memsize;
174 unsigned char caslat, caslat_ctrl;
175 unsigned int trfc, trfc_clk, trfc_low, trfc_high;
176 unsigned int trcd_clk;
177 unsigned int trtp_clk;
178 unsigned char cke_min_clk;
179 unsigned char add_lat;
180 unsigned char wr_lat;
181 unsigned char wr_data_delay;
182 unsigned char four_act;
184 unsigned char burst_len;
185 unsigned int mode_caslat;
186 unsigned char sdram_type;
187 unsigned char d_init;
188 unsigned int law_size;
189 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
192 ddr = &immap->im_ddr1;
194 ddr = &immap->im_ddr2;
197 * Read SPD information.
200 debug("Performing SPD read at I2C address 0x%02lx\n",i2c_address);
201 memset((void *)&spd, 0, sizeof(spd));
202 CFG_READ_SPD(i2c_address, 0, 1, (uchar *) &spd, sizeof(spd));
205 * Check for supported memory module types.
207 if (spd.mem_type != SPD_MEMTYPE_DDR &&
208 spd.mem_type != SPD_MEMTYPE_DDR2) {
209 debug("Warning: Unable to locate DDR I or DDR II module for DIMM %d of DDR controller %d.\n"
210 " Fundamental memory type is 0x%0x\n",
217 debug("\nFound memory of type 0x%02lx ", spd.mem_type);
218 if (spd.mem_type == SPD_MEMTYPE_DDR)
224 * These test gloss over DDR I and II differences in interpretation
225 * of bytes 3 and 4, but irrelevantly. Multiple asymmetric banks
226 * are not supported on DDR I; and not encoded on DDR II.
228 * Also note that the 8548 controller can support:
231 * 8 <= ncol <= 11 (still, for DDR)
232 * 6 <= ncol <= 9 (for FCRAM)
234 if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
235 printf("DDR: Unsupported number of Row Addr lines: %d.\n",
239 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
240 printf("DDR: Unsupported number of Column Addr lines: %d.\n",
246 * Determine the number of physical banks controlled by
247 * different Chip Select signals. This is not quite the
248 * same as the number of DIMM modules on the board. Feh.
250 if (spd.mem_type == SPD_MEMTYPE_DDR) {
253 n_ranks = (spd.nrows & 0x7) + 1;
256 debug("DDR: number of ranks = %d\n", n_ranks);
259 printf("DDR: Only 2 chip selects are supported: %d\n",
265 * Adjust DDR II IO voltage biasing. It just makes it work.
267 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
269 | 0x80000000 /* Enable */
270 | 0x10000000 /* VSEL to 1.8V */
275 * Determine the size of each Rank in bytes.
277 rank_density = compute_banksize(spd.mem_type, spd.row_dens);
279 debug("Start address for this controller is 0x%08lx\n", start_addr);
282 * ODT configuration recommendation from DDR Controller Chapter.
284 odt_rd_cfg = 0; /* Never assert ODT */
285 odt_wr_cfg = 0; /* Never assert ODT */
286 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
287 odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */
290 #ifdef CONFIG_DDR_INTERLEAVE
291 #ifdef CONFIG_MPC8641HPCN
293 printf("For interleaving memory on HPCN, need to use DIMM 1 for DDR Controller %d !\n", ddr_num);
297 * Since interleaved memory only uses CS0, the
298 * memory sticks have to be identical in size and quantity
299 * of ranks. That essentially gives double the size on
300 * one rank, i.e on CS0 for both controllers put together.
306 * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
309 ddr->cs0_bnds = (start_addr >> 8)
310 | (((start_addr + rank_density - 1) >> 24));
312 * Default interleaving mode to cache-line interleaving.
314 ddr->cs0_config = ( 1 << 31
315 #if (CFG_PAGE_INTERLEAVING == 1)
316 | (PAGE_INTERLEAVING)
317 #elif (CFG_BANK_INTERLEAVING == 1)
318 | (BANK_INTERLEAVING)
319 #elif (CFG_SUPER_BANK_INTERLEAVING == 1)
320 | (SUPER_BANK_INTERLEAVING)
322 | (CACHE_LINE_INTERLEAVING)
326 | (spd.nrow_addr - 12) << 8
327 | (spd.ncol_addr - 8) );
329 debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds);
330 debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
333 * Adjustment for dual rank memory to get correct memory
334 * size (return value of this function).
343 #endif /* CONFIG_MPC8641HPCN */
345 #else /* CONFIG_DDR_INTERLEAVE */
349 * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
351 ddr->cs0_bnds = (start_addr >> 8)
352 | (((start_addr + rank_density - 1) >> 24));
354 ddr->cs0_config = ( 1 << 31
357 | (spd.nrow_addr - 12) << 8
358 | (spd.ncol_addr - 8) );
360 debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds);
361 debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
365 * Eg: Bounds: 0x1000_0000 to 0x1f00_0000,
368 ddr->cs1_bnds = (((start_addr + rank_density) >> 8)
369 | (( start_addr + 2*rank_density - 1)
371 ddr->cs1_config = ( 1<<31
374 | (spd.nrow_addr - 12) << 8
375 | (spd.ncol_addr - 8) );
376 debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds);
377 debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config);
382 * This is the 2nd DIMM slot for this controller
385 * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
387 ddr->cs2_bnds = (start_addr >> 8)
388 | (((start_addr + rank_density - 1) >> 24));
390 ddr->cs2_config = ( 1 << 31
393 | (spd.nrow_addr - 12) << 8
394 | (spd.ncol_addr - 8) );
396 debug("DDR: cs2_bnds = 0x%08x\n", ddr->cs2_bnds);
397 debug("DDR: cs2_config = 0x%08x\n", ddr->cs2_config);
401 * Eg: Bounds: 0x1000_0000 to 0x1f00_0000,
404 ddr->cs3_bnds = (((start_addr + rank_density) >> 8)
405 | (( start_addr + 2*rank_density - 1)
407 ddr->cs3_config = ( 1<<31
410 | (spd.nrow_addr - 12) << 8
411 | (spd.ncol_addr - 8) );
412 debug("DDR: cs3_bnds = 0x%08x\n", ddr->cs3_bnds);
413 debug("DDR: cs3_config = 0x%08x\n", ddr->cs3_config);
416 #endif /* CONFIG_DDR_INTERLEAVE */
419 * Find the largest CAS by locating the highest 1 bit
420 * in the spd.cas_lat field. Translate it to a DDR
421 * controller field value:
423 * CAS Lat DDR I DDR II Ctrl
424 * Clocks SPD Bit SPD Bit Value
425 * ------- ------- ------- -----
436 caslat = __ilog2(spd.cas_lat);
437 if ((spd.mem_type == SPD_MEMTYPE_DDR)
439 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
442 } else if (spd.mem_type == SPD_MEMTYPE_DDR2
443 && (caslat < 2 || caslat > 5)) {
444 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
448 debug("DDR: caslat SPD bit is %d\n", caslat);
451 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
452 * The SPD clk_cycle field (tCKmin) is measured in tenths of
453 * nanoseconds and represented as BCD.
455 tCKmin_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle);
456 debug("DDR: tCKmin = %d ps\n", tCKmin_ps);
459 * Double-data rate, scaled 1000 to picoseconds, and back down to MHz.
461 max_data_rate = 2 * 1000 * 1000 / tCKmin_ps;
462 debug("DDR: Module max data rate = %d Mhz\n", max_data_rate);
466 * Adjust the CAS Latency to allow for bus speeds that
467 * are slower than the DDR module.
469 busfreq = get_bus_freq(0) / 1000000; /* MHz */
471 effective_data_rate = max_data_rate;
473 /* DDR rate out-of-range */
474 puts("DDR: platform frequency is not fit for DDR rate\n");
477 } else if (90 <= busfreq && busfreq < 230 && max_data_rate >= 230) {
479 * busfreq 90~230 range, treated as DDR 200.
481 effective_data_rate = 200;
482 if (spd.clk_cycle3 == 0xa0) /* 10 ns */
484 else if (spd.clk_cycle2 == 0xa0)
487 } else if (230 <= busfreq && busfreq < 280 && max_data_rate >= 280) {
489 * busfreq 230~280 range, treated as DDR 266.
491 effective_data_rate = 266;
492 if (spd.clk_cycle3 == 0x75) /* 7.5 ns */
494 else if (spd.clk_cycle2 == 0x75)
497 } else if (280 <= busfreq && busfreq < 350 && max_data_rate >= 350) {
499 * busfreq 280~350 range, treated as DDR 333.
501 effective_data_rate = 333;
502 if (spd.clk_cycle3 == 0x60) /* 6.0 ns */
504 else if (spd.clk_cycle2 == 0x60)
507 } else if (350 <= busfreq && busfreq < 460 && max_data_rate >= 460) {
509 * busfreq 350~460 range, treated as DDR 400.
511 effective_data_rate = 400;
512 if (spd.clk_cycle3 == 0x50) /* 5.0 ns */
514 else if (spd.clk_cycle2 == 0x50)
517 } else if (460 <= busfreq && busfreq < 560 && max_data_rate >= 560) {
519 * busfreq 460~560 range, treated as DDR 533.
521 effective_data_rate = 533;
522 if (spd.clk_cycle3 == 0x3D) /* 3.75 ns */
524 else if (spd.clk_cycle2 == 0x3D)
527 } else if (560 <= busfreq && busfreq < 700 && max_data_rate >= 700) {
529 * busfreq 560~700 range, treated as DDR 667.
531 effective_data_rate = 667;
532 if (spd.clk_cycle3 == 0x30) /* 3.0 ns */
534 else if (spd.clk_cycle2 == 0x30)
537 } else if (700 <= busfreq) {
539 * DDR rate out-of-range
541 printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
542 busfreq, max_data_rate);
548 * Convert caslat clocks to DDR controller value.
549 * Force caslat_ctrl to be DDR Controller field-sized.
551 if (spd.mem_type == SPD_MEMTYPE_DDR) {
552 caslat_ctrl = (caslat + 1) & 0x07;
554 caslat_ctrl = (2 * caslat - 1) & 0x0f;
557 debug("DDR: effective data rate is %d MHz\n", effective_data_rate);
558 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
559 caslat, caslat_ctrl);
563 * Avoid writing for DDR I. The new PQ38 DDR controller
564 * dreams up non-zero default values to be backwards compatible.
566 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
567 unsigned char taxpd_clk = 8; /* By the book. */
568 unsigned char tmrd_clk = 2; /* By the book. */
569 unsigned char act_pd_exit = 2; /* Empirical? */
570 unsigned char pre_pd_exit = 6; /* Empirical? */
572 ddr->timing_cfg_0 = (0
573 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
574 | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
575 | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
576 | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
578 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
584 * Some Timing Config 1 values now.
585 * Sneak Extended Refresh Recovery in here too.
589 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
590 * use conservative value.
591 * For DDR II, they are bytes 36 and 37, in quarter nanos.
594 if (spd.mem_type == SPD_MEMTYPE_DDR) {
595 twr_clk = 3; /* Clocks */
596 twtr_clk = 1; /* Clocks */
598 twr_clk = picos_to_clk(spd.twr * 250);
599 twtr_clk = picos_to_clk(spd.twtr * 250);
603 * Calculate Trfc, in picos.
604 * DDR I: Byte 42 straight up in ns.
605 * DDR II: Byte 40 and 42 swizzled some, in ns.
607 if (spd.mem_type == SPD_MEMTYPE_DDR) {
608 trfc = spd.trfc * 1000; /* up to ps */
610 unsigned int byte40_table_ps[8] = {
621 trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
622 + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
624 trfc_clk = picos_to_clk(trfc);
627 * Trcd, Byte 29, from quarter nanos to ps and clocks.
629 trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
632 * Convert trfc_clk to DDR controller fields. DDR I should
633 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
634 * 8548 controller has an extended REFREC field of three bits.
635 * The controller automatically adds 8 clocks to this value,
636 * so preadjust it down 8 first before splitting it up.
638 trfc_low = (trfc_clk - 8) & 0xf;
639 trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
642 * Sneak in some Extended Refresh Recovery.
644 ddr->ext_refrec = (trfc_high << 16);
645 debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
649 | ((picos_to_clk(spd.trp * 250) & 0x07) << 28) /* PRETOACT */
650 | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24) /* ACTTOPRE */
651 | (trcd_clk << 20) /* ACTTORW */
652 | (caslat_ctrl << 16) /* CASLAT */
653 | (trfc_low << 12) /* REFEC */
654 | ((twr_clk & 0x07) << 8) /* WRRREC */
655 | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) /* ACTTOACT */
656 | ((twtr_clk & 0x07) << 0) /* WRTORD */
659 debug("DDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
670 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
671 * which comes from Trcd, and also note that:
672 * add_lat + caslat must be >= 4
675 if (spd.mem_type == SPD_MEMTYPE_DDR2
676 && (odt_wr_cfg || odt_rd_cfg)
678 add_lat = 4 - caslat;
679 if (add_lat > trcd_clk) {
680 add_lat = trcd_clk - 1;
686 * Historically 0x2 == 4/8 clock delay.
687 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
694 * Minimum CKE Pulse Width.
695 * Four Activate Window
697 if (spd.mem_type == SPD_MEMTYPE_DDR) {
699 * This is a lie. It should really be 1, but if it is
700 * set to 1, bits overlap into the old controller's
701 * otherwise unused ACSM field. If we leave it 0, then
702 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
706 trtp_clk = 2; /* By the book. */
707 cke_min_clk = 1; /* By the book. */
708 four_act = 1; /* By the book. */
713 /* Convert SPD value from quarter nanos to picos. */
714 trtp_clk = picos_to_clk(spd.trtp * 250);
716 cke_min_clk = 3; /* By the book. */
717 four_act = picos_to_clk(37500); /* By the book. 1k pages? */
721 * Empirically set ~MCAS-to-preamble override for DDR 2.
722 * Your milage will vary.
725 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
726 if (effective_data_rate == 266 || effective_data_rate == 333) {
727 cpo = 0x7; /* READ_LAT + 5/4 */
728 } else if (effective_data_rate == 400) {
729 cpo = 0x9; /* READ_LAT + 7/4 */
731 /* Pure speculation */
736 ddr->timing_cfg_2 = (0
737 | ((add_lat & 0x7) << 28) /* ADD_LAT */
738 | ((cpo & 0x1f) << 23) /* CPO */
739 | ((wr_lat & 0x7) << 19) /* WR_LAT */
740 | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
741 | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
742 | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
743 | ((four_act & 0x1f) << 0) /* FOUR_ACT */
746 debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
750 * Determine the Mode Register Set.
752 * This is nominally part specific, but it appears to be
753 * consistent for all DDR I devices, and for all DDR II devices.
755 * caslat must be programmed
756 * burst length is always 4
757 * burst type is sequential
760 * operating mode is "normal"
769 * Table lookup from DDR I or II Device Operation Specs.
771 if (spd.mem_type == SPD_MEMTYPE_DDR) {
772 if (1 <= caslat && caslat <= 4) {
773 unsigned char mode_caslat_table[4] = {
774 0x5, /* 1.5 clocks */
775 0x2, /* 2.0 clocks */
776 0x6, /* 2.5 clocks */
779 mode_caslat = mode_caslat_table[caslat - 1];
781 puts("DDR I: Only CAS Latencies of 1.5, 2.0, "
782 "2.5 and 3.0 clocks are supported.\n");
787 if (2 <= caslat && caslat <= 5) {
788 mode_caslat = caslat;
790 puts("DDR II: Only CAS Latencies of 2.0, 3.0, "
791 "4.0 and 5.0 clocks are supported.\n");
797 * Encoded Burst Length of 4.
799 burst_len = 2; /* Fiat. */
801 if (spd.mem_type == SPD_MEMTYPE_DDR) {
802 twr_auto_clk = 0; /* Historical */
805 * Determine tCK max in picos. Grab tWR and convert to picos.
806 * Auto-precharge write recovery is:
807 * WR = roundup(tWR_ns/tCKmax_ns).
809 * Ponder: Is twr_auto_clk different than twr_clk?
811 tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd.tckmax);
812 twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps;
817 * Mode Reg in bits 16 ~ 31,
818 * Extended Mode Reg 1 in bits 0 ~ 15.
820 mode_odt_enable = 0x0; /* Default disabled */
821 if (odt_wr_cfg || odt_rd_cfg) {
823 * Bits 6 and 2 in Extended MRS(1)
824 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
825 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
827 mode_odt_enable = 0x40; /* 150 Ohm */
832 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
833 | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
834 | (twr_auto_clk << 9) /* Write Recovery Autopre */
835 | (mode_caslat << 4) /* caslat */
836 | (burst_len << 0) /* Burst length */
839 debug("DDR: sdram_mode = 0x%08x\n", ddr->sdram_mode_1);
843 * Clear EMRS2 and EMRS3.
845 ddr->sdram_mode_2 = 0;
846 debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2);
850 * Determine Refresh Rate. Ignore self refresh bit on DDR I.
851 * Table from SPD Spec, Byte 12, converted to picoseconds and
852 * filled in with "default" normal values.
855 unsigned int refresh_clk;
856 unsigned int refresh_time_ns[8] = {
857 15625000, /* 0 Normal 1.00x */
858 3900000, /* 1 Reduced .25x */
859 7800000, /* 2 Extended .50x */
860 31300000, /* 3 Extended 2.00x */
861 62500000, /* 4 Extended 4.00x */
862 125000000, /* 5 Extended 8.00x */
863 15625000, /* 6 Normal 1.00x filler */
864 15625000, /* 7 Normal 1.00x filler */
867 refresh_clk = picos_to_clk(refresh_time_ns[spd.refresh & 0x7]);
870 * Set BSTOPRE to 0x100 for page mode
871 * If auto-charge is used, set BSTOPRE = 0
873 ddr->sdram_interval =
875 | (refresh_clk & 0x3fff) << 16
878 debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval);
882 * Is this an ECC DDR chip?
883 * But don't mess with it if the DDR controller will init mem.
885 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
886 if (spd.config == 0x02) {
887 ddr->err_disable = 0x0000000d;
888 ddr->err_sbe = 0x00ff0000;
890 debug("DDR: err_disable = 0x%08x\n", ddr->err_disable);
891 debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe);
902 * When ODT is enabled, Chap 9 suggests asserting ODT to
903 * internal IOs only during reads.
906 if (odt_rd_cfg | odt_wr_cfg) {
907 odt_cfg = 0x2; /* ODT to IOs during reads */
911 * Try to use differential DQS with DDR II.
913 if (spd.mem_type == SPD_MEMTYPE_DDR) {
914 dqs_cfg = 0; /* No Differential DQS for DDR I */
916 dqs_cfg = 0x1; /* Differential DQS for DDR II */
919 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
921 * Use the DDR controller to auto initialize memory.
924 ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE;
925 debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init);
928 * Memory will be initialized via DMA, or not at all.
933 ddr->sdram_cfg_2 = (0
934 | (dqs_cfg << 26) /* Differential DQS */
935 | (odt_cfg << 21) /* ODT */
936 | (d_init << 4) /* D_INIT auto init DDR */
939 debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr->sdram_cfg_2);
942 #ifdef MPC86xx_DDR_SDRAM_CLK_CNTL
944 unsigned char clk_adjust;
947 * Setup the clock control.
948 * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
949 * SDRAM_CLK_CNTL[5-7] = Clock Adjust
950 * 0110 3/4 cycle late
951 * 0111 7/8 cycle late
953 if (spd.mem_type == SPD_MEMTYPE_DDR) {
959 ddr->sdram_clk_cntl = (0
963 debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl);
969 * Figure out memory size in Megabytes.
971 debug("# ranks = %d, rank_density = 0x%08lx\n", n_ranks, rank_density);
972 memsize = n_ranks * rank_density / 0x100000;
977 unsigned int enable_ddr(unsigned int ddr_num)
979 volatile immap_t *immap = (immap_t *)CFG_IMMR;
980 spd_eeprom_t spd1,spd2;
981 volatile ccsr_ddr_t *ddr;
982 unsigned sdram_cfg_1;
983 unsigned char sdram_type, mem_type, config, mod_attr;
984 unsigned char d_init;
985 unsigned int no_dimm1=0, no_dimm2=0;
987 /* Set up pointer to enable the current ddr controller */
989 ddr = &immap->im_ddr1;
991 ddr = &immap->im_ddr2;
994 * Read both dimm slots and decide whether
995 * or not to enable this controller.
997 memset((void *)&spd1,0,sizeof(spd1));
998 memset((void *)&spd2,0,sizeof(spd2));
1001 CFG_READ_SPD(SPD_EEPROM_ADDRESS1,
1002 0, 1, (uchar *) &spd1, sizeof(spd1));
1003 CFG_READ_SPD(SPD_EEPROM_ADDRESS2,
1004 0, 1, (uchar *) &spd2, sizeof(spd2));
1006 CFG_READ_SPD(SPD_EEPROM_ADDRESS3,
1007 0, 1, (uchar *) &spd1, sizeof(spd1));
1008 CFG_READ_SPD(SPD_EEPROM_ADDRESS4,
1009 0, 1, (uchar *) &spd2, sizeof(spd2));
1013 * Check for supported memory module types.
1015 if (spd1.mem_type != SPD_MEMTYPE_DDR
1016 && spd1.mem_type != SPD_MEMTYPE_DDR2) {
1019 debug("\nFound memory of type 0x%02lx ",spd1.mem_type );
1020 if (spd1.mem_type == SPD_MEMTYPE_DDR)
1026 if (spd2.mem_type != SPD_MEMTYPE_DDR &&
1027 spd2.mem_type != SPD_MEMTYPE_DDR2) {
1030 debug("\nFound memory of type 0x%02lx ",spd2.mem_type );
1031 if (spd2.mem_type == SPD_MEMTYPE_DDR)
1037 #ifdef CONFIG_DDR_INTERLEAVE
1039 printf("For interleaved operation memory modules need to be present in CS0 DIMM slots of both DDR controllers!\n");
1045 * Memory is not present in DIMM1 and DIMM2 - so do not enable DDRn
1047 if (no_dimm1 && no_dimm2) {
1048 printf("No memory modules found for DDR controller %d!!\n", ddr_num);
1051 mem_type = no_dimm2 ? spd1.mem_type : spd2.mem_type;
1054 * Figure out the settings for the sdram_cfg register.
1055 * Build up the entire register in 'sdram_cfg' before
1056 * writing since the write into the register will
1057 * actually enable the memory controller; all settings
1058 * must be done before enabling.
1060 * sdram_cfg[0] = 1 (ddr sdram logic enable)
1061 * sdram_cfg[1] = 1 (self-refresh-enable)
1062 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
1066 sdram_type = (mem_type == SPD_MEMTYPE_DDR) ? 2 : 3;
1068 | (1 << 31) /* Enable */
1069 | (1 << 30) /* Self refresh */
1070 | (sdram_type << 24) /* SDRAM type */
1074 * sdram_cfg[3] = RD_EN - registered DIMM enable
1075 * A value of 0x26 indicates micron registered
1076 * DIMMS (micron.com)
1078 mod_attr = no_dimm2 ? spd1.mod_attr : spd2.mod_attr;
1079 if (mem_type == SPD_MEMTYPE_DDR && mod_attr == 0x26) {
1080 sdram_cfg_1 |= 0x10000000; /* RD_EN */
1083 #if defined(CONFIG_DDR_ECC)
1085 config = no_dimm2 ? spd1.config : spd2.config;
1088 * If the user wanted ECC (enabled via sdram_cfg[2])
1090 if (config == 0x02) {
1091 sdram_cfg_1 |= 0x20000000; /* ECC_EN */
1096 * REV1 uses 1T timing.
1097 * REV2 may use 1T or 2T as configured by the user.
1100 uint pvr = get_pvr();
1102 if (pvr != PVR_85xx_REV1) {
1103 #if defined(CONFIG_DDR_2T_TIMING)
1105 * Enable 2T timing by setting sdram_cfg[16].
1107 sdram_cfg_1 |= 0x8000; /* 2T_EN */
1113 * 200 painful micro-seconds must elapse between
1114 * the DDR clock setup and the DDR config enable.
1121 ddr->sdram_cfg_1 = sdram_cfg_1;
1123 asm volatile("sync;isync");
1126 debug("DDR: sdram_cfg = 0x%08x\n", ddr->sdram_cfg_1);
1129 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
1131 debug("DDR: memory initializing\n");
1134 * Poll until memory is initialized.
1135 * 512 Meg at 400 might hit this 200 times or so.
1137 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
1140 debug("DDR: memory initialized\n\n");
1143 debug("Enabled DDR Controller %d\n", ddr_num);
1152 int memsize_ddr1_dimm1 = 0;
1153 int memsize_ddr1_dimm2 = 0;
1154 int memsize_ddr2_dimm1 = 0;
1155 int memsize_ddr2_dimm2 = 0;
1156 int memsize_total = 0;
1157 int memsize_ddr1 = 0;
1158 int memsize_ddr2 = 0;
1159 unsigned int ddr1_enabled = 0;
1160 unsigned int ddr2_enabled = 0;
1161 unsigned int law_size_ddr1;
1162 unsigned int law_size_ddr2;
1163 volatile immap_t *immap = (immap_t *)CFG_IMMR;
1164 volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
1165 volatile ccsr_ddr_t *ddr2 = &immap->im_ddr2;
1166 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
1168 #ifdef CONFIG_DDR_INTERLEAVE
1169 unsigned int law_size_interleaved;
1171 memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1,
1173 (unsigned int)memsize_total * 1024*1024);
1174 memsize_total += memsize_ddr1_dimm1;
1176 memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3,
1178 (unsigned int)memsize_total * 1024*1024);
1179 memsize_total += memsize_ddr2_dimm1;
1181 if (memsize_ddr1_dimm1 != memsize_ddr2_dimm1) {
1182 if (memsize_ddr1_dimm1 < memsize_ddr2_dimm1)
1183 memsize_total -= memsize_ddr1_dimm1;
1185 memsize_total -= memsize_ddr2_dimm1;
1186 debug("Total memory available for interleaving 0x%08lx\n",
1187 memsize_total * 1024 * 1024);
1188 debug("Adjusting CS0_BNDS to account for unequal DIMM sizes in interleaved memory\n");
1189 ddr1->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24;
1190 ddr2->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24;
1191 debug("DDR1: cs0_bnds = 0x%08x\n", ddr1->cs0_bnds);
1192 debug("DDR2: cs0_bnds = 0x%08x\n", ddr2->cs0_bnds);
1195 ddr1_enabled = enable_ddr(1);
1196 ddr2_enabled = enable_ddr(2);
1199 * Both controllers need to be enabled for interleaving.
1201 if (ddr1_enabled && ddr2_enabled) {
1202 law_size_interleaved = 19 + __ilog2(memsize_total);
1205 * Set up LAWBAR for DDR 1 space.
1207 mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
1208 mcm->lawar1 = (LAWAR_EN
1209 | LAWAR_TRGT_IF_DDR_INTERLEAVED
1210 | (LAWAR_SIZE & law_size_interleaved));
1211 debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
1212 debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
1213 debug("Interleaved memory size is 0x%08lx\n", memsize_total);
1215 #ifdef CONFIG_DDR_INTERLEAVE
1216 #if (CFG_PAGE_INTERLEAVING == 1)
1218 #elif (CFG_BANK_INTERLEAVING == 1)
1220 #elif (CFG_SUPER_BANK_INTERLEAVING == 1)
1221 printf("Super-bank ");
1223 printf("Cache-line ");
1226 printf("Interleaved");
1227 return memsize_total * 1024 * 1024;
1229 printf("Interleaved memory not enabled - check CS0 DIMM slots for both controllers.\n");
1235 * Call spd_sdram() routine to init ddr1 - pass I2c address,
1236 * controller number, dimm number, and starting address.
1238 memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1,
1240 (unsigned int)memsize_total * 1024*1024);
1241 memsize_total += memsize_ddr1_dimm1;
1243 memsize_ddr1_dimm2 = spd_init(SPD_EEPROM_ADDRESS2,
1245 (unsigned int)memsize_total * 1024*1024);
1246 memsize_total += memsize_ddr1_dimm2;
1249 * Enable the DDR controller - pass ddr controller number.
1251 ddr1_enabled = enable_ddr(1);
1253 /* Keep track of memory to be addressed by DDR1 */
1254 memsize_ddr1 = memsize_ddr1_dimm1 + memsize_ddr1_dimm2;
1257 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord.
1260 law_size_ddr1 = 19 + __ilog2(memsize_ddr1);
1263 * Set up LAWBAR for DDR 1 space.
1265 mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
1266 mcm->lawar1 = (LAWAR_EN
1267 | LAWAR_TRGT_IF_DDR1
1268 | (LAWAR_SIZE & law_size_ddr1));
1269 debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
1270 debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
1273 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
1274 memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3,
1276 (unsigned int)memsize_total * 1024*1024);
1277 memsize_total += memsize_ddr2_dimm1;
1279 memsize_ddr2_dimm2 = spd_init(SPD_EEPROM_ADDRESS4,
1281 (unsigned int)memsize_total * 1024*1024);
1282 memsize_total += memsize_ddr2_dimm2;
1284 ddr2_enabled = enable_ddr(2);
1286 /* Keep track of memory to be addressed by DDR2 */
1287 memsize_ddr2 = memsize_ddr2_dimm1 + memsize_ddr2_dimm2;
1290 law_size_ddr2 = 19 + __ilog2(memsize_ddr2);
1293 * Set up LAWBAR for DDR 2 space.
1296 mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12)
1299 mcm->lawbar8 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
1301 mcm->lawar8 = (LAWAR_EN
1302 | LAWAR_TRGT_IF_DDR2
1303 | (LAWAR_SIZE & law_size_ddr2));
1304 debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
1305 debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
1307 #endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
1309 debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n",
1310 memsize_ddr1, memsize_ddr2);
1313 * If neither DDR controller is enabled return 0.
1315 if (!ddr1_enabled && !ddr2_enabled)
1318 printf("Non-interleaved");
1319 return memsize_total * 1024 * 1024;
1322 #endif /* CONFIG_DDR_INTERLEAVE */
1326 #endif /* CONFIG_SPD_EEPROM */
1329 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
1332 * Initialize all of memory for ECC, then enable errors.
1336 ddr_enable_ecc(unsigned int dram_size)
1340 volatile immap_t *immap = (immap_t *)CFG_IMMR;
1341 volatile ccsr_ddr_t *ddr1= &immap->im_ddr1;
1345 for (*p = 0; p < (uint *)(8 * 1024); p++) {
1346 if (((unsigned int)p & 0x1f) == 0) {
1347 ppcDcbz((unsigned long) p);
1349 *p = (unsigned int)CONFIG_MEM_INIT_VALUE;
1350 if (((unsigned int)p & 0x1c) == 0x1c) {
1351 ppcDcbf((unsigned long) p);
1356 dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
1358 dma_xfer((uint *)0x4000, 0x4000, (uint *)0);
1360 dma_xfer((uint *)0x8000, 0x8000, (uint *)0);
1362 dma_xfer((uint *)0x10000, 0x10000, (uint *)0);
1364 dma_xfer((uint *)0x20000, 0x20000, (uint *)0);
1366 dma_xfer((uint *)0x40000, 0x40000, (uint *)0);
1368 dma_xfer((uint *)0x80000, 0x80000, (uint *)0);
1370 dma_xfer((uint *)0x100000, 0x100000, (uint *)0);
1372 dma_xfer((uint *)0x200000, 0x200000, (uint *)0);
1374 dma_xfer((uint *)0x400000, 0x400000, (uint *)0);
1376 for (i = 1; i < dram_size / 0x800000; i++) {
1377 dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
1381 * Enable errors for ECC.
1383 debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable);
1384 ddr1->err_disable = 0x00000000;
1385 asm("sync;isync;msync");
1386 debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable);
1389 #endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */