2 * Copyright 2004 Freescale Semiconductor.
3 * (C) Copyright 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
32 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
33 extern void dma_init(void);
34 extern uint dma_check(void);
35 extern int dma_xfer(void *dest, uint count, void *src);
38 #ifdef CONFIG_SPD_EEPROM
41 #define CFG_READ_SPD i2c_read
45 * Only one of the following three should be 1; others should be 0
46 * By default the cache line interleaving is selected if
47 * the CONFIG_DDR_INTERLEAVE flag is defined
49 #define CFG_PAGE_INTERLEAVING 0
50 #define CFG_BANK_INTERLEAVING 0
51 #define CFG_SUPER_BANK_INTERLEAVING 0
54 * Convert picoseconds into DRAM clock cycles (rounding up if needed).
58 picos_to_clk(unsigned int picos)
60 /* use unsigned long long to avoid rounding errors */
61 const unsigned long long ULL_2e12 = 2000000000000ULL;
62 unsigned long long clks;
63 unsigned long long clks_temp;
68 clks = get_bus_freq(0) * (unsigned long long) picos;
70 clks = clks / ULL_2e12;
71 if (clks_temp % ULL_2e12) {
75 if (clks > 0xFFFFFFFFULL) {
79 return (unsigned int) clks;
84 * Calculate the Density of each Physical Rank.
85 * Returned size is in bytes.
87 * Study these table from Byte 31 of JEDEC SPD Spec.
101 * Reorder Table to be linear by stripping the bottom
102 * 2 or 5 bits off and shifting them up to the top.
106 compute_banksize(unsigned int mem_type, unsigned char row_dens)
110 if (mem_type == SPD_MEMTYPE_DDR) {
111 /* Bottom 2 bits up to the top. */
112 bsize = ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
113 debug("DDR: DDR I rank density = 0x%08x\n", bsize);
115 /* Bottom 5 bits up to the top. */
116 bsize = ((row_dens >> 5) | ((row_dens & 31) << 3)) << 27;
117 debug("DDR: DDR II rank density = 0x%08x\n", bsize);
124 * Convert a two-nibble BCD value into a cycle time.
125 * While the spec calls for nano-seconds, picos are returned.
127 * This implements the tables for bytes 9, 23 and 25 for both
128 * DDR I and II. No allowance for distinguishing the invalid
129 * fields absent for DDR I yet present in DDR II is made.
130 * (That is, cycle times of .25, .33, .66 and .75 ns are
131 * allowed for both DDR II and I.)
135 convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
138 * Table look up the lower nibble, allow DDR I & II.
140 unsigned int tenths_ps[16] = {
159 unsigned int whole_ns = (spd_val & 0xF0) >> 4;
160 unsigned int tenth_ns = spd_val & 0x0F;
161 unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
168 * Determine Refresh Rate. Ignore self refresh bit on DDR I.
169 * Table from SPD Spec, Byte 12, converted to picoseconds and
170 * filled in with "default" normal values.
172 unsigned int determine_refresh_rate(unsigned int spd_refresh)
174 unsigned int refresh_time_ns[8] = {
175 15625000, /* 0 Normal 1.00x */
176 3900000, /* 1 Reduced .25x */
177 7800000, /* 2 Extended .50x */
178 31300000, /* 3 Extended 2.00x */
179 62500000, /* 4 Extended 4.00x */
180 125000000, /* 5 Extended 8.00x */
181 15625000, /* 6 Normal 1.00x filler */
182 15625000, /* 7 Normal 1.00x filler */
185 return picos_to_clk(refresh_time_ns[spd_refresh & 0x7]);
190 spd_init(unsigned char i2c_address, unsigned int ddr_num,
191 unsigned int dimm_num, unsigned int start_addr)
193 volatile immap_t *immap = (immap_t *)CFG_IMMR;
194 volatile ccsr_ddr_t *ddr;
195 volatile ccsr_gur_t *gur = &immap->im_gur;
197 unsigned int n_ranks;
198 unsigned int rank_density;
199 unsigned int odt_rd_cfg, odt_wr_cfg;
200 unsigned int odt_cfg, mode_odt_enable;
201 unsigned int refresh_clk;
202 #ifdef MPC86xx_DDR_SDRAM_CLK_CNTL
203 unsigned char clk_adjust;
205 unsigned int dqs_cfg;
206 unsigned char twr_clk, twtr_clk, twr_auto_clk;
207 unsigned int tCKmin_ps, tCKmax_ps;
208 unsigned int max_data_rate;
209 unsigned int busfreq;
210 unsigned int memsize;
211 unsigned char caslat, caslat_ctrl;
212 unsigned int trfc, trfc_clk, trfc_low, trfc_high;
213 unsigned int trcd_clk;
214 unsigned int trtp_clk;
215 unsigned char cke_min_clk;
216 unsigned char add_lat;
217 unsigned char wr_lat;
218 unsigned char wr_data_delay;
219 unsigned char four_act;
221 unsigned char burst_len;
222 unsigned int mode_caslat;
223 unsigned char d_init;
224 unsigned int tCycle_ps, modfreq;
227 ddr = &immap->im_ddr1;
229 ddr = &immap->im_ddr2;
232 * Read SPD information.
234 debug("Performing SPD read at I2C address 0x%02lx\n",i2c_address);
235 memset((void *)&spd, 0, sizeof(spd));
236 CFG_READ_SPD(i2c_address, 0, 1, (uchar *) &spd, sizeof(spd));
239 * Check for supported memory module types.
241 if (spd.mem_type != SPD_MEMTYPE_DDR &&
242 spd.mem_type != SPD_MEMTYPE_DDR2) {
243 debug("Warning: Unable to locate DDR I or DDR II module for DIMM %d of DDR controller %d.\n"
244 " Fundamental memory type is 0x%0x\n",
251 debug("\nFound memory of type 0x%02lx ", spd.mem_type);
252 if (spd.mem_type == SPD_MEMTYPE_DDR)
258 * These test gloss over DDR I and II differences in interpretation
259 * of bytes 3 and 4, but irrelevantly. Multiple asymmetric banks
260 * are not supported on DDR I; and not encoded on DDR II.
262 * Also note that the 8548 controller can support:
265 * 8 <= ncol <= 11 (still, for DDR)
266 * 6 <= ncol <= 9 (for FCRAM)
268 if (spd.nrow_addr < 12 || spd.nrow_addr > 14) {
269 printf("DDR: Unsupported number of Row Addr lines: %d.\n",
273 if (spd.ncol_addr < 8 || spd.ncol_addr > 11) {
274 printf("DDR: Unsupported number of Column Addr lines: %d.\n",
280 * Determine the number of physical banks controlled by
281 * different Chip Select signals. This is not quite the
282 * same as the number of DIMM modules on the board. Feh.
284 if (spd.mem_type == SPD_MEMTYPE_DDR) {
287 n_ranks = (spd.nrows & 0x7) + 1;
290 debug("DDR: number of ranks = %d\n", n_ranks);
293 printf("DDR: Only 2 chip selects are supported: %d\n",
299 * Adjust DDR II IO voltage biasing. Rev1 only
301 if (((get_svr() & 0xf0) == 0x10) && (spd.mem_type == SPD_MEMTYPE_DDR2)) {
303 | 0x80000000 /* Enable */
304 | 0x10000000 /* VSEL to 1.8V */
309 * Determine the size of each Rank in bytes.
311 rank_density = compute_banksize(spd.mem_type, spd.row_dens);
313 debug("Start address for this controller is 0x%08lx\n", start_addr);
316 * ODT configuration recommendation from DDR Controller Chapter.
318 odt_rd_cfg = 0; /* Never assert ODT */
319 odt_wr_cfg = 0; /* Never assert ODT */
320 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
321 odt_wr_cfg = 1; /* Assert ODT on writes to CS0 */
324 #ifdef CONFIG_DDR_INTERLEAVE
327 printf("For interleaving memory on HPCN, need to use DIMM 1 for DDR Controller %d !\n", ddr_num);
331 * Since interleaved memory only uses CS0, the
332 * memory sticks have to be identical in size and quantity
333 * of ranks. That essentially gives double the size on
334 * one rank, i.e on CS0 for both controllers put together.
340 * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
343 ddr->cs0_bnds = (start_addr >> 8)
344 | (((start_addr + rank_density - 1) >> 24));
346 * Default interleaving mode to cache-line interleaving.
348 ddr->cs0_config = ( 1 << 31
349 #if (CFG_PAGE_INTERLEAVING == 1)
350 | (PAGE_INTERLEAVING)
351 #elif (CFG_BANK_INTERLEAVING == 1)
352 | (BANK_INTERLEAVING)
353 #elif (CFG_SUPER_BANK_INTERLEAVING == 1)
354 | (SUPER_BANK_INTERLEAVING)
356 | (CACHE_LINE_INTERLEAVING)
360 | (spd.nrow_addr - 12) << 8
361 | (spd.ncol_addr - 8) );
363 debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds);
364 debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
367 * Adjustment for dual rank memory to get correct memory
368 * size (return value of this function).
377 #else /* CONFIG_DDR_INTERLEAVE */
381 * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
383 ddr->cs0_bnds = (start_addr >> 8)
384 | (((start_addr + rank_density - 1) >> 24));
386 ddr->cs0_config = ( 1 << 31
389 | (spd.nrow_addr - 12) << 8
390 | (spd.ncol_addr - 8) );
392 debug("DDR: cs0_bnds = 0x%08x\n", ddr->cs0_bnds);
393 debug("DDR: cs0_config = 0x%08x\n", ddr->cs0_config);
397 * Eg: Bounds: 0x1000_0000 to 0x1f00_0000,
400 ddr->cs1_bnds = (((start_addr + rank_density) >> 8)
401 | (( start_addr + 2*rank_density - 1)
403 ddr->cs1_config = ( 1<<31
406 | (spd.nrow_addr - 12) << 8
407 | (spd.ncol_addr - 8) );
408 debug("DDR: cs1_bnds = 0x%08x\n", ddr->cs1_bnds);
409 debug("DDR: cs1_config = 0x%08x\n", ddr->cs1_config);
414 * This is the 2nd DIMM slot for this controller
417 * Eg: Bounds: 0x0000_0000 to 0x0f000_0000 first 256 Meg
419 ddr->cs2_bnds = (start_addr >> 8)
420 | (((start_addr + rank_density - 1) >> 24));
422 ddr->cs2_config = ( 1 << 31
425 | (spd.nrow_addr - 12) << 8
426 | (spd.ncol_addr - 8) );
428 debug("DDR: cs2_bnds = 0x%08x\n", ddr->cs2_bnds);
429 debug("DDR: cs2_config = 0x%08x\n", ddr->cs2_config);
433 * Eg: Bounds: 0x1000_0000 to 0x1f00_0000,
436 ddr->cs3_bnds = (((start_addr + rank_density) >> 8)
437 | (( start_addr + 2*rank_density - 1)
439 ddr->cs3_config = ( 1<<31
442 | (spd.nrow_addr - 12) << 8
443 | (spd.ncol_addr - 8) );
444 debug("DDR: cs3_bnds = 0x%08x\n", ddr->cs3_bnds);
445 debug("DDR: cs3_config = 0x%08x\n", ddr->cs3_config);
448 #endif /* CONFIG_DDR_INTERLEAVE */
451 * Find the largest CAS by locating the highest 1 bit
452 * in the spd.cas_lat field. Translate it to a DDR
453 * controller field value:
455 * CAS Lat DDR I DDR II Ctrl
456 * Clocks SPD Bit SPD Bit Value
457 * ------- ------- ------- -----
468 caslat = __ilog2(spd.cas_lat);
469 if ((spd.mem_type == SPD_MEMTYPE_DDR)
471 printf("DDR I: Invalid SPD CAS Latency: 0x%x.\n", spd.cas_lat);
474 } else if (spd.mem_type == SPD_MEMTYPE_DDR2
475 && (caslat < 2 || caslat > 5)) {
476 printf("DDR II: Invalid SPD CAS Latency: 0x%x.\n",
480 debug("DDR: caslat SPD bit is %d\n", caslat);
483 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
484 * The SPD clk_cycle field (tCKmin) is measured in tenths of
485 * nanoseconds and represented as BCD.
487 tCKmin_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle);
488 debug("DDR: tCKmin = %d ps\n", tCKmin_ps);
491 * Double-data rate, scaled 1000 to picoseconds, and back down to MHz.
493 max_data_rate = 2 * 1000 * 1000 / tCKmin_ps;
494 debug("DDR: Module max data rate = %d Mhz\n", max_data_rate);
498 * Adjust the CAS Latency to allow for bus speeds that
499 * are slower than the DDR module.
501 busfreq = get_bus_freq(0) / 1000000; /* MHz */
502 tCycle_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle3);
503 modfreq = 2 * 1000 * 1000 / tCycle_ps;
505 if ((spd.mem_type == SPD_MEMTYPE_DDR2) && (busfreq < 266)) {
506 printf("DDR: platform frequency too low for correct DDR2 controller operation\n");
508 } else if (busfreq < 90) {
509 printf("DDR: platform frequency too low for correct DDR1 operation\n");
513 if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 2)))) {
516 tCycle_ps = convert_bcd_tenths_to_cycle_time_ps(spd.clk_cycle2);
517 modfreq = 2 * 1000 * 1000 / tCycle_ps;
518 if ((busfreq <= modfreq) && (spd.cas_lat & (1 << (caslat - 1))))
520 else if (busfreq > max_data_rate) {
521 printf("DDR: Bus freq %d MHz is not fit for DDR rate %d MHz\n",
522 busfreq, max_data_rate);
528 * Empirically set ~MCAS-to-preamble override for DDR 2.
529 * Your milage will vary.
532 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
533 if (busfreq <= 333) {
535 } else if (busfreq <= 400) {
543 * Convert caslat clocks to DDR controller value.
544 * Force caslat_ctrl to be DDR Controller field-sized.
546 if (spd.mem_type == SPD_MEMTYPE_DDR) {
547 caslat_ctrl = (caslat + 1) & 0x07;
549 caslat_ctrl = (2 * caslat - 1) & 0x0f;
552 debug("DDR: caslat SPD bit is %d, controller field is 0x%x\n",
553 caslat, caslat_ctrl);
557 * Avoid writing for DDR I. The new PQ38 DDR controller
558 * dreams up non-zero default values to be backwards compatible.
560 if (spd.mem_type == SPD_MEMTYPE_DDR2) {
561 unsigned char taxpd_clk = 8; /* By the book. */
562 unsigned char tmrd_clk = 2; /* By the book. */
563 unsigned char act_pd_exit = 2; /* Empirical? */
564 unsigned char pre_pd_exit = 6; /* Empirical? */
566 ddr->timing_cfg_0 = (0
567 | ((act_pd_exit & 0x7) << 20) /* ACT_PD_EXIT */
568 | ((pre_pd_exit & 0x7) << 16) /* PRE_PD_EXIT */
569 | ((taxpd_clk & 0xf) << 8) /* ODT_PD_EXIT */
570 | ((tmrd_clk & 0xf) << 0) /* MRS_CYC */
572 debug("DDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
578 * Some Timing Config 1 values now.
579 * Sneak Extended Refresh Recovery in here too.
583 * For DDR I, WRREC(Twr) and WRTORD(Twtr) are not in SPD,
584 * use conservative value.
585 * For DDR II, they are bytes 36 and 37, in quarter nanos.
588 if (spd.mem_type == SPD_MEMTYPE_DDR) {
589 twr_clk = 3; /* Clocks */
590 twtr_clk = 1; /* Clocks */
592 twr_clk = picos_to_clk(spd.twr * 250);
593 twtr_clk = picos_to_clk(spd.twtr * 250);
597 * Calculate Trfc, in picos.
598 * DDR I: Byte 42 straight up in ns.
599 * DDR II: Byte 40 and 42 swizzled some, in ns.
601 if (spd.mem_type == SPD_MEMTYPE_DDR) {
602 trfc = spd.trfc * 1000; /* up to ps */
604 unsigned int byte40_table_ps[8] = {
615 trfc = (((spd.trctrfc_ext & 0x1) * 256) + spd.trfc) * 1000
616 + byte40_table_ps[(spd.trctrfc_ext >> 1) & 0x7];
618 trfc_clk = picos_to_clk(trfc);
621 * Trcd, Byte 29, from quarter nanos to ps and clocks.
623 trcd_clk = picos_to_clk(spd.trcd * 250) & 0x7;
626 * Convert trfc_clk to DDR controller fields. DDR I should
627 * fit in the REFREC field (16-19) of TIMING_CFG_1, but the
628 * 8548 controller has an extended REFREC field of three bits.
629 * The controller automatically adds 8 clocks to this value,
630 * so preadjust it down 8 first before splitting it up.
632 trfc_low = (trfc_clk - 8) & 0xf;
633 trfc_high = ((trfc_clk - 8) >> 4) & 0x3;
636 * Sneak in some Extended Refresh Recovery.
638 ddr->ext_refrec = (trfc_high << 16);
639 debug("DDR: ext_refrec = 0x%08x\n", ddr->ext_refrec);
643 | ((picos_to_clk(spd.trp * 250) & 0x07) << 28) /* PRETOACT */
644 | ((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24) /* ACTTOPRE */
645 | (trcd_clk << 20) /* ACTTORW */
646 | (caslat_ctrl << 16) /* CASLAT */
647 | (trfc_low << 12) /* REFEC */
648 | ((twr_clk & 0x07) << 8) /* WRRREC */
649 | ((picos_to_clk(spd.trrd * 250) & 0x07) << 4) /* ACTTOACT */
650 | ((twtr_clk & 0x07) << 0) /* WRTORD */
653 debug("DDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
664 * For DDR II, with ODT enabled, use "a value" less than ACTTORW,
665 * which comes from Trcd, and also note that:
666 * add_lat + caslat must be >= 4
669 if (spd.mem_type == SPD_MEMTYPE_DDR2
670 && (odt_wr_cfg || odt_rd_cfg)
672 add_lat = 4 - caslat;
673 if (add_lat >= trcd_clk) {
674 add_lat = trcd_clk - 1;
680 * Historically 0x2 == 4/8 clock delay.
681 * Empirically, 0x3 == 6/8 clock delay is suggested for DDR I 266.
688 * Minimum CKE Pulse Width.
689 * Four Activate Window
691 if (spd.mem_type == SPD_MEMTYPE_DDR) {
693 * This is a lie. It should really be 1, but if it is
694 * set to 1, bits overlap into the old controller's
695 * otherwise unused ACSM field. If we leave it 0, then
696 * the HW will magically treat it as 1 for DDR 1. Oh Yea.
700 trtp_clk = 2; /* By the book. */
701 cke_min_clk = 1; /* By the book. */
702 four_act = 1; /* By the book. */
707 /* Convert SPD value from quarter nanos to picos. */
708 trtp_clk = picos_to_clk(spd.trtp * 250);
710 cke_min_clk = 3; /* By the book. */
711 four_act = picos_to_clk(37500); /* By the book. 1k pages? */
714 ddr->timing_cfg_2 = (0
715 | ((add_lat & 0x7) << 28) /* ADD_LAT */
716 | ((cpo & 0x1f) << 23) /* CPO */
717 | ((wr_lat & 0x7) << 19) /* WR_LAT */
718 | ((trtp_clk & 0x7) << 13) /* RD_TO_PRE */
719 | ((wr_data_delay & 0x7) << 10) /* WR_DATA_DELAY */
720 | ((cke_min_clk & 0x7) << 6) /* CKE_PLS */
721 | ((four_act & 0x1f) << 0) /* FOUR_ACT */
724 debug("DDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
728 * Determine the Mode Register Set.
730 * This is nominally part specific, but it appears to be
731 * consistent for all DDR I devices, and for all DDR II devices.
733 * caslat must be programmed
734 * burst length is always 4
735 * burst type is sequential
738 * operating mode is "normal"
747 * Table lookup from DDR I or II Device Operation Specs.
749 if (spd.mem_type == SPD_MEMTYPE_DDR) {
750 if (1 <= caslat && caslat <= 4) {
751 unsigned char mode_caslat_table[4] = {
752 0x5, /* 1.5 clocks */
753 0x2, /* 2.0 clocks */
754 0x6, /* 2.5 clocks */
757 mode_caslat = mode_caslat_table[caslat - 1];
759 puts("DDR I: Only CAS Latencies of 1.5, 2.0, "
760 "2.5 and 3.0 clocks are supported.\n");
765 if (2 <= caslat && caslat <= 5) {
766 mode_caslat = caslat;
768 puts("DDR II: Only CAS Latencies of 2.0, 3.0, "
769 "4.0 and 5.0 clocks are supported.\n");
775 * Encoded Burst Length of 4.
777 burst_len = 2; /* Fiat. */
779 if (spd.mem_type == SPD_MEMTYPE_DDR) {
780 twr_auto_clk = 0; /* Historical */
783 * Determine tCK max in picos. Grab tWR and convert to picos.
784 * Auto-precharge write recovery is:
785 * WR = roundup(tWR_ns/tCKmax_ns).
787 * Ponder: Is twr_auto_clk different than twr_clk?
789 tCKmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd.tckmax);
790 twr_auto_clk = (spd.twr * 250 + tCKmax_ps - 1) / tCKmax_ps;
794 * Mode Reg in bits 16 ~ 31,
795 * Extended Mode Reg 1 in bits 0 ~ 15.
797 mode_odt_enable = 0x0; /* Default disabled */
798 if (odt_wr_cfg || odt_rd_cfg) {
800 * Bits 6 and 2 in Extended MRS(1)
801 * Bit 2 == 0x04 == 75 Ohm, with 2 DIMM modules.
802 * Bit 6 == 0x40 == 150 Ohm, with 1 DIMM module.
804 mode_odt_enable = 0x40; /* 150 Ohm */
809 | (add_lat << (16 + 3)) /* Additive Latency in EMRS1 */
810 | (mode_odt_enable << 16) /* ODT Enable in EMRS1 */
811 | (twr_auto_clk << 9) /* Write Recovery Autopre */
812 | (mode_caslat << 4) /* caslat */
813 | (burst_len << 0) /* Burst length */
816 debug("DDR: sdram_mode = 0x%08x\n", ddr->sdram_mode_1);
819 * Clear EMRS2 and EMRS3.
821 ddr->sdram_mode_2 = 0;
822 debug("DDR: sdram_mode_2 = 0x%08x\n", ddr->sdram_mode_2);
825 * Determine Refresh Rate.
827 refresh_clk = determine_refresh_rate(spd.refresh & 0x7);
830 * Set BSTOPRE to 0x100 for page mode
831 * If auto-charge is used, set BSTOPRE = 0
833 ddr->sdram_interval =
835 | (refresh_clk & 0x3fff) << 16
838 debug("DDR: sdram_interval = 0x%08x\n", ddr->sdram_interval);
842 * Is this an ECC DDR chip?
843 * But don't mess with it if the DDR controller will init mem.
845 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
846 if (spd.config == 0x02) {
847 ddr->err_disable = 0x0000000d;
848 ddr->err_sbe = 0x00ff0000;
850 debug("DDR: err_disable = 0x%08x\n", ddr->err_disable);
851 debug("DDR: err_sbe = 0x%08x\n", ddr->err_sbe);
854 asm volatile("sync;isync");
862 * When ODT is enabled, Chap 9 suggests asserting ODT to
863 * internal IOs only during reads.
866 if (odt_rd_cfg | odt_wr_cfg) {
867 odt_cfg = 0x2; /* ODT to IOs during reads */
871 * Try to use differential DQS with DDR II.
873 if (spd.mem_type == SPD_MEMTYPE_DDR) {
874 dqs_cfg = 0; /* No Differential DQS for DDR I */
876 dqs_cfg = 0x1; /* Differential DQS for DDR II */
879 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
881 * Use the DDR controller to auto initialize memory.
884 ddr->sdram_data_init = CONFIG_MEM_INIT_VALUE;
885 debug("DDR: ddr_data_init = 0x%08x\n", ddr->sdram_data_init);
888 * Memory will be initialized via DMA, or not at all.
893 ddr->sdram_cfg_2 = (0
894 | (dqs_cfg << 26) /* Differential DQS */
895 | (odt_cfg << 21) /* ODT */
896 | (d_init << 4) /* D_INIT auto init DDR */
899 debug("DDR: sdram_cfg_2 = 0x%08x\n", ddr->sdram_cfg_2);
902 #ifdef MPC86xx_DDR_SDRAM_CLK_CNTL
904 * Setup the clock control.
905 * SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
906 * SDRAM_CLK_CNTL[5-7] = Clock Adjust
907 * 0110 3/4 cycle late
908 * 0111 7/8 cycle late
910 if (spd.mem_type == SPD_MEMTYPE_DDR)
915 ddr->sdram_clk_cntl = (0
919 debug("DDR: sdram_clk_cntl = 0x%08x\n", ddr->sdram_clk_cntl);
923 * Figure out memory size in Megabytes.
925 debug("# ranks = %d, rank_density = 0x%08lx\n", n_ranks, rank_density);
926 memsize = n_ranks * rank_density / 0x100000;
931 unsigned int enable_ddr(unsigned int ddr_num)
933 volatile immap_t *immap = (immap_t *)CFG_IMMR;
934 spd_eeprom_t spd1,spd2;
935 volatile ccsr_ddr_t *ddr;
936 unsigned sdram_cfg_1;
937 unsigned char sdram_type, mem_type, config, mod_attr;
938 unsigned char d_init;
939 unsigned int no_dimm1=0, no_dimm2=0;
941 /* Set up pointer to enable the current ddr controller */
943 ddr = &immap->im_ddr1;
945 ddr = &immap->im_ddr2;
948 * Read both dimm slots and decide whether
949 * or not to enable this controller.
951 memset((void *)&spd1, 0, sizeof(spd1));
952 memset((void *)&spd2, 0, sizeof(spd2));
955 CFG_READ_SPD(SPD_EEPROM_ADDRESS1,
956 0, 1, (uchar *) &spd1, sizeof(spd1));
957 #if defined(SPD_EEPROM_ADDRESS2)
958 CFG_READ_SPD(SPD_EEPROM_ADDRESS2,
959 0, 1, (uchar *) &spd2, sizeof(spd2));
962 #if defined(SPD_EEPROM_ADDRESS3)
963 CFG_READ_SPD(SPD_EEPROM_ADDRESS3,
964 0, 1, (uchar *) &spd1, sizeof(spd1));
966 #if defined(SPD_EEPROM_ADDRESS4)
967 CFG_READ_SPD(SPD_EEPROM_ADDRESS4,
968 0, 1, (uchar *) &spd2, sizeof(spd2));
973 * Check for supported memory module types.
975 if (spd1.mem_type != SPD_MEMTYPE_DDR
976 && spd1.mem_type != SPD_MEMTYPE_DDR2) {
979 debug("\nFound memory of type 0x%02lx ",spd1.mem_type );
980 if (spd1.mem_type == SPD_MEMTYPE_DDR)
986 if (spd2.mem_type != SPD_MEMTYPE_DDR &&
987 spd2.mem_type != SPD_MEMTYPE_DDR2) {
990 debug("\nFound memory of type 0x%02lx ",spd2.mem_type );
991 if (spd2.mem_type == SPD_MEMTYPE_DDR)
997 #ifdef CONFIG_DDR_INTERLEAVE
999 printf("For interleaved operation memory modules need to be present in CS0 DIMM slots of both DDR controllers!\n");
1005 * Memory is not present in DIMM1 and DIMM2 - so do not enable DDRn
1007 if (no_dimm1 && no_dimm2) {
1008 printf("No memory modules found for DDR controller %d!!\n", ddr_num);
1011 mem_type = no_dimm2 ? spd1.mem_type : spd2.mem_type;
1014 * Figure out the settings for the sdram_cfg register.
1015 * Build up the entire register in 'sdram_cfg' before
1016 * writing since the write into the register will
1017 * actually enable the memory controller; all settings
1018 * must be done before enabling.
1020 * sdram_cfg[0] = 1 (ddr sdram logic enable)
1021 * sdram_cfg[1] = 1 (self-refresh-enable)
1022 * sdram_cfg[5:7] = (SDRAM type = DDR SDRAM)
1026 sdram_type = (mem_type == SPD_MEMTYPE_DDR) ? 2 : 3;
1028 | (1 << 31) /* Enable */
1029 | (1 << 30) /* Self refresh */
1030 | (sdram_type << 24) /* SDRAM type */
1034 * sdram_cfg[3] = RD_EN - registered DIMM enable
1035 * A value of 0x26 indicates micron registered
1036 * DIMMS (micron.com)
1038 mod_attr = no_dimm2 ? spd1.mod_attr : spd2.mod_attr;
1039 if (mem_type == SPD_MEMTYPE_DDR && mod_attr == 0x26) {
1040 sdram_cfg_1 |= 0x10000000; /* RD_EN */
1043 #if defined(CONFIG_DDR_ECC)
1045 config = no_dimm2 ? spd1.config : spd2.config;
1048 * If the user wanted ECC (enabled via sdram_cfg[2])
1050 if (config == 0x02) {
1051 ddr->err_disable = 0x00000000;
1052 asm volatile("sync;isync;");
1053 ddr->err_sbe = 0x00ff0000;
1054 ddr->err_int_en = 0x0000000d;
1055 sdram_cfg_1 |= 0x20000000; /* ECC_EN */
1060 * Set 1T or 2T timing based on 1 or 2 modules
1063 if (!(no_dimm1 || no_dimm2)) {
1065 * 2T timing,because both DIMMS are present.
1066 * Enable 2T timing by setting sdram_cfg[16].
1068 sdram_cfg_1 |= 0x8000; /* 2T_EN */
1073 * 200 painful micro-seconds must elapse between
1074 * the DDR clock setup and the DDR config enable.
1081 ddr->sdram_cfg_1 = sdram_cfg_1;
1083 asm volatile("sync;isync");
1086 debug("DDR: sdram_cfg = 0x%08x\n", ddr->sdram_cfg_1);
1089 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
1091 debug("DDR: memory initializing\n");
1094 * Poll until memory is initialized.
1095 * 512 Meg at 400 might hit this 200 times or so.
1097 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
1100 debug("DDR: memory initialized\n\n");
1103 debug("Enabled DDR Controller %d\n", ddr_num);
1112 int memsize_ddr1_dimm1 = 0;
1113 int memsize_ddr1_dimm2 = 0;
1114 int memsize_ddr1 = 0;
1115 unsigned int law_size_ddr1;
1116 volatile immap_t *immap = (immap_t *)CFG_IMMR;
1117 volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
1118 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
1120 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
1121 int memsize_ddr2_dimm1 = 0;
1122 int memsize_ddr2_dimm2 = 0;
1123 int memsize_ddr2 = 0;
1124 unsigned int law_size_ddr2;
1127 unsigned int ddr1_enabled = 0;
1128 unsigned int ddr2_enabled = 0;
1129 int memsize_total = 0;
1131 #ifdef CONFIG_DDR_INTERLEAVE
1132 unsigned int law_size_interleaved;
1133 volatile ccsr_ddr_t *ddr2 = &immap->im_ddr2;
1135 memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1,
1137 (unsigned int)memsize_total * 1024*1024);
1138 memsize_total += memsize_ddr1_dimm1;
1140 memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3,
1142 (unsigned int)memsize_total * 1024*1024);
1143 memsize_total += memsize_ddr2_dimm1;
1145 if (memsize_ddr1_dimm1 != memsize_ddr2_dimm1) {
1146 if (memsize_ddr1_dimm1 < memsize_ddr2_dimm1)
1147 memsize_total -= memsize_ddr1_dimm1;
1149 memsize_total -= memsize_ddr2_dimm1;
1150 debug("Total memory available for interleaving 0x%08lx\n",
1151 memsize_total * 1024 * 1024);
1152 debug("Adjusting CS0_BNDS to account for unequal DIMM sizes in interleaved memory\n");
1153 ddr1->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24;
1154 ddr2->cs0_bnds = ((memsize_total * 1024 * 1024) - 1) >> 24;
1155 debug("DDR1: cs0_bnds = 0x%08x\n", ddr1->cs0_bnds);
1156 debug("DDR2: cs0_bnds = 0x%08x\n", ddr2->cs0_bnds);
1159 ddr1_enabled = enable_ddr(1);
1160 ddr2_enabled = enable_ddr(2);
1163 * Both controllers need to be enabled for interleaving.
1165 if (ddr1_enabled && ddr2_enabled) {
1166 law_size_interleaved = 19 + __ilog2(memsize_total);
1169 * Set up LAWBAR for DDR 1 space.
1171 mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
1172 mcm->lawar1 = (LAWAR_EN
1173 | LAWAR_TRGT_IF_DDR_INTERLEAVED
1174 | (LAWAR_SIZE & law_size_interleaved));
1175 debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
1176 debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
1177 debug("Interleaved memory size is 0x%08lx\n", memsize_total);
1179 #ifdef CONFIG_DDR_INTERLEAVE
1180 #if (CFG_PAGE_INTERLEAVING == 1)
1182 #elif (CFG_BANK_INTERLEAVING == 1)
1184 #elif (CFG_SUPER_BANK_INTERLEAVING == 1)
1185 printf("Super-bank ");
1187 printf("Cache-line ");
1190 printf("Interleaved");
1191 return memsize_total * 1024 * 1024;
1193 printf("Interleaved memory not enabled - check CS0 DIMM slots for both controllers.\n");
1199 * Call spd_sdram() routine to init ddr1 - pass I2c address,
1200 * controller number, dimm number, and starting address.
1202 memsize_ddr1_dimm1 = spd_init(SPD_EEPROM_ADDRESS1,
1204 (unsigned int)memsize_total * 1024*1024);
1205 memsize_total += memsize_ddr1_dimm1;
1207 #if defined(SPD_EEPROM_ADDRESS2)
1208 memsize_ddr1_dimm2 = spd_init(SPD_EEPROM_ADDRESS2,
1210 (unsigned int)memsize_total * 1024*1024);
1212 memsize_total += memsize_ddr1_dimm2;
1215 * Enable the DDR controller - pass ddr controller number.
1217 ddr1_enabled = enable_ddr(1);
1219 /* Keep track of memory to be addressed by DDR1 */
1220 memsize_ddr1 = memsize_ddr1_dimm1 + memsize_ddr1_dimm2;
1223 * First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord.
1226 law_size_ddr1 = 19 + __ilog2(memsize_ddr1);
1229 * Set up LAWBAR for DDR 1 space.
1231 mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
1232 mcm->lawar1 = (LAWAR_EN
1233 | LAWAR_TRGT_IF_DDR1
1234 | (LAWAR_SIZE & law_size_ddr1));
1235 debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
1236 debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
1239 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
1240 memsize_ddr2_dimm1 = spd_init(SPD_EEPROM_ADDRESS3,
1242 (unsigned int)memsize_total * 1024*1024);
1243 memsize_total += memsize_ddr2_dimm1;
1245 memsize_ddr2_dimm2 = spd_init(SPD_EEPROM_ADDRESS4,
1247 (unsigned int)memsize_total * 1024*1024);
1248 memsize_total += memsize_ddr2_dimm2;
1250 ddr2_enabled = enable_ddr(2);
1252 /* Keep track of memory to be addressed by DDR2 */
1253 memsize_ddr2 = memsize_ddr2_dimm1 + memsize_ddr2_dimm2;
1256 law_size_ddr2 = 19 + __ilog2(memsize_ddr2);
1259 * Set up LAWBAR for DDR 2 space.
1262 mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12)
1265 mcm->lawbar8 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
1267 mcm->lawar8 = (LAWAR_EN
1268 | LAWAR_TRGT_IF_DDR2
1269 | (LAWAR_SIZE & law_size_ddr2));
1270 debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
1271 debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
1273 #endif /* CONFIG_NUM_DDR_CONTROLLERS > 1 */
1275 debug("\nMemory sizes are DDR1 = 0x%08lx, DDR2 = 0x%08lx\n",
1276 memsize_ddr1, memsize_ddr2);
1279 * If neither DDR controller is enabled return 0.
1281 if (!ddr1_enabled && !ddr2_enabled)
1284 printf("Non-interleaved");
1285 return memsize_total * 1024 * 1024;
1287 #endif /* CONFIG_DDR_INTERLEAVE */
1291 #endif /* CONFIG_SPD_EEPROM */
1294 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
1297 * Initialize all of memory for ECC, then enable errors.
1301 ddr_enable_ecc(unsigned int dram_size)
1305 volatile immap_t *immap = (immap_t *)CFG_IMMR;
1306 volatile ccsr_ddr_t *ddr1= &immap->im_ddr1;
1310 for (*p = 0; p < (uint *)(8 * 1024); p++) {
1311 if (((unsigned int)p & 0x1f) == 0) {
1312 ppcDcbz((unsigned long) p);
1314 *p = (unsigned int)CONFIG_MEM_INIT_VALUE;
1315 if (((unsigned int)p & 0x1c) == 0x1c) {
1316 ppcDcbf((unsigned long) p);
1320 dma_xfer((uint *)0x002000, 0x002000, (uint *)0); /* 8K */
1321 dma_xfer((uint *)0x004000, 0x004000, (uint *)0); /* 16K */
1322 dma_xfer((uint *)0x008000, 0x008000, (uint *)0); /* 32K */
1323 dma_xfer((uint *)0x010000, 0x010000, (uint *)0); /* 64K */
1324 dma_xfer((uint *)0x020000, 0x020000, (uint *)0); /* 128k */
1325 dma_xfer((uint *)0x040000, 0x040000, (uint *)0); /* 256k */
1326 dma_xfer((uint *)0x080000, 0x080000, (uint *)0); /* 512k */
1327 dma_xfer((uint *)0x100000, 0x100000, (uint *)0); /* 1M */
1328 dma_xfer((uint *)0x200000, 0x200000, (uint *)0); /* 2M */
1329 dma_xfer((uint *)0x400000, 0x400000, (uint *)0); /* 4M */
1331 for (i = 1; i < dram_size / 0x800000; i++) {
1332 dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
1336 * Enable errors for ECC.
1338 debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable);
1339 ddr1->err_disable = 0x00000000;
1340 asm volatile("sync;isync");
1341 debug("DMA DDR: err_disable = 0x%08x\n", ddr1->err_disable);
1344 #endif /* CONFIG_DDR_ECC && ! CONFIG_ECC_INIT_VIA_DDRCONTROLLER */