cpu/mpc86xx/pcie_indirect.c

   1 /*
   2  * Support for indirect PCI bridges.
   3  *
   4  * Copyright (c) Freescale Semiconductor, Inc.
   5  * 2006. All rights reserved.
   6  *
   7  * Jason Jin <Jason.jin@freescale.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  *
  14  * partly derived from
  15  * arch/powerpc/platforms/86xx/mpc86xx_pcie.c
  16  */
  17
  18 #include <common.h>
  19
  20 #ifdef CONFIG_PCI
  21
  22 #include <asm/processor.h>
  23 #include <asm/io.h>
  24 #include <pci.h>
  25
  26 #define PCI_CFG_OUT     out_be32
  27 #define PEX_FIX         out_be32(hose->cfg_addr+0x4, 0x0400ffff)
  28
  29 static int
  30 indirect_read_config_pcie(struct pci_controller *hose,
  31                          pci_dev_t dev, int offset,
  32                          int len,u32 *val)
  33 {
  34         int bus = PCI_BUS(dev);
  35         char devfn = ( (PCI_DEV(dev) << 4 ) | (PCI_FUNC(dev)) ) ;
  36
  37         unsigned char *cfg_data;
  38         u32 temp;
  39
  40         PEX_FIX;
  41         if( bus == 0xff) {
  42                 PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001);
  43         }else {
  44                 PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);
  45         }
  46         /*
  47          * Note: the caller has already checked that offset is
  48          * suitably aligned and that len is 1, 2 or 4.
  49          */
  50         /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
  51         cfg_data = hose->cfg_data;
  52         PEX_FIX;
  53         temp = in_le32(cfg_data);
  54         switch (len) {
  55         case 1:
  56                 *val = (temp >> (((offset & 3))*8)) & 0xff;
  57                 break;
  58         case 2:
  59                 *val = (temp >> (((offset & 3))*8)) & 0xffff;
  60                 break;
  61         default:
  62                 *val = temp;
  63                 break;
  64         }
  65
  66         return 0;
  67 }
  68
  69 static int
  70 indirect_write_config_pcie(struct pci_controller *hose,
  71                           pci_dev_t dev,
  72                           int offset,
  73                           int len,
  74                           u32 val)
  75 {
  76         int bus = PCI_BUS(dev);
  77         char devfn = ( (PCI_DEV(dev) << 4 ) | (PCI_FUNC(dev)) ) ;
  78
  79         unsigned char *cfg_data;
  80         u32 temp;
  81
  82         PEX_FIX;
  83         if( bus == 0xff) {
  84                 PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001);
  85         }else {
  86                 PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);
  87         }
  88
  89         /*
  90          * Note: the caller has already checked that offset is
  91          * suitably aligned and that len is 1, 2 or 4.
  92          */
  93         /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
  94         cfg_data = hose->cfg_data;
  95         switch (len) {
  96         case 1:
  97                 PEX_FIX;
  98                 temp = in_le32(cfg_data);
  99                 temp = (temp & ~(0xff << ((offset & 3) * 8))) |
 100                         (val << ((offset & 3) * 8));
 101                 PEX_FIX;
 102                 out_le32(cfg_data, temp);
 103                 break;
 104         case 2:
 105                 PEX_FIX;
 106                 temp = in_le32(cfg_data);
 107                 temp = (temp & ~(0xffff << ((offset & 3) * 8)));
 108                 temp |= (val << ((offset & 3) * 8)) ;
 109                 PEX_FIX;
 110                 out_le32(cfg_data, temp);
 111                 break;
 112         default:
 113                 PEX_FIX;
 114                 out_le32(cfg_data, val);
 115                 break;
 116         }
 117         PEX_FIX;
 118         return 0;
 119 }
 120
 121 static int
 122 indirect_read_config_byte_pcie(struct pci_controller *hose,
 123                               pci_dev_t dev,
 124                               int offset,
 125                               u8 *val)
 126 {
 127         u32 val32;
 128         indirect_read_config_pcie(hose,dev,offset,1,&val32);
 129         *val = (u8)val32;
 130         return 0;
 131 }
 132
 133 static int
 134 indirect_read_config_word_pcie(struct pci_controller *hose,
 135                               pci_dev_t dev,
 136                               int offset,
 137                               u16 *val)
 138 {
 139         u32 val32;
 140         indirect_read_config_pcie(hose,dev,offset,2,&val32);
 141         *val = (u16)val32;
 142         return 0;
 143 }
 144
 145 static int
 146 indirect_read_config_dword_pcie(struct pci_controller *hose,
 147                                pci_dev_t dev,
 148                                int offset,
 149                                u32 *val)
 150 {
 151         return indirect_read_config_pcie(hose,dev, offset,4,val);
 152 }
 153
 154 static int
 155 indirect_write_config_byte_pcie(struct pci_controller *hose,
 156                                pci_dev_t dev,
 157                                int offset,
 158                                char val)
 159 {
 160         return indirect_write_config_pcie(hose,dev, offset,1,(u32)val);
 161 }
 162
 163 static int
 164 indirect_write_config_word_pcie(struct pci_controller *hose,
 165                                pci_dev_t dev,
 166                                int offset,
 167                                unsigned short val)
 168 {
 169         return indirect_write_config_pcie(hose,dev, offset,2,(u32)val);
 170 }
 171
 172 static int
 173 indirect_write_config_dword_pcie(struct pci_controller *hose,
 174                                 pci_dev_t dev,
 175                                 int offset,
 176                                 unsigned short val)
 177 {
 178         return indirect_write_config_pcie(hose,dev, offset,4,val);
 179 }
 180
 181 void
 182 pcie_setup_indirect(struct pci_controller* hose,
 183                    u32 cfg_addr,
 184                    u32 cfg_data)
 185 {
 186         pci_set_ops(hose,
 187                     indirect_read_config_byte_pcie,
 188                     indirect_read_config_word_pcie,
 189                     indirect_read_config_dword_pcie,
 190                     indirect_write_config_byte_pcie,
 191                     indirect_write_config_word_pcie,
 192                     indirect_write_config_dword_pcie);
 193
 194         hose->cfg_addr = (unsigned int *) cfg_addr;
 195         hose->cfg_data = (unsigned char *) cfg_data;
 196 }
 197
 198 #endif  /* CONFIG_PCI */