cpu/mpc86xx/pcie_indirect.c

   1 /*
   2  * Support for indirect PCI bridges.
   3  *
   4  * Copyright (c) Freescale Semiconductor, Inc.
   5  * 2006. All rights reserved.
   6  *
   7  * Jason Jin <Jason.jin@freescale.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  *
  14  * partly derived from
  15  * arch/powerpc/platforms/86xx/mpc86xx_pcie.c
  16  */
  17
  18 #include <common.h>
  19
  20 #ifdef CONFIG_PCI
  21
  22 #include <asm/processor.h>
  23 #include <asm/io.h>
  24 #include <pci.h>
  25
  26 #define PCI_CFG_OUT     out_be32
  27 #define PEX_FIX         out_be32(hose->cfg_addr+0x4, 0x0400ffff)
  28
  29 static int
  30 indirect_read_config_pcie(struct pci_controller *hose,
  31                          pci_dev_t dev, int offset,
  32                          int len,u32 *val)
  33 {
  34         int bus = PCI_BUS(dev);
  35
  36         volatile unsigned char *cfg_data;
  37         u32 temp;
  38
  39         PEX_FIX;
  40         if( bus == 0xff) {
  41                 PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001);
  42         }else {
  43                 PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);
  44         }
  45         /*
  46          * Note: the caller has already checked that offset is
  47          * suitably aligned and that len is 1, 2 or 4.
  48          */
  49         /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
  50         cfg_data = hose->cfg_data;
  51         PEX_FIX;
  52         temp = in_le32((u32 *)cfg_data);
  53         switch (len) {
  54         case 1:
  55                 *val = (temp >> (((offset & 3))*8)) & 0xff;
  56                 break;
  57         case 2:
  58                 *val = (temp >> (((offset & 3))*8)) & 0xffff;
  59                 break;
  60         default:
  61                 *val = temp;
  62                 break;
  63         }
  64
  65         return 0;
  66 }
  67
  68 static int
  69 indirect_write_config_pcie(struct pci_controller *hose,
  70                           pci_dev_t dev,
  71                           int offset,
  72                           int len,
  73                           u32 val)
  74 {
  75         int bus = PCI_BUS(dev);
  76         volatile unsigned char *cfg_data;
  77         u32 temp;
  78
  79         PEX_FIX;
  80         if( bus == 0xff) {
  81                 PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000001);
  82         }else {
  83                 PCI_CFG_OUT(hose->cfg_addr, dev | (offset & 0xfc) | 0x80000000);
  84         }
  85
  86         /*
  87          * Note: the caller has already checked that offset is
  88          * suitably aligned and that len is 1, 2 or 4.
  89          */
  90         /* ERRATA PCI-Ex 12 - Configuration Address/Data Alignment */
  91         cfg_data = hose->cfg_data;
  92         switch (len) {
  93         case 1:
  94                 PEX_FIX;
  95                 temp = in_le32((u32 *)cfg_data);
  96                 temp = (temp & ~(0xff << ((offset & 3) * 8))) |
  97                         (val << ((offset & 3) * 8));
  98                 PEX_FIX;
  99                 out_le32((u32 *)cfg_data, temp);
 100                 break;
 101         case 2:
 102                 PEX_FIX;
 103                 temp = in_le32((u32 *)cfg_data);
 104                 temp = (temp & ~(0xffff << ((offset & 3) * 8)));
 105                 temp |= (val << ((offset & 3) * 8)) ;
 106                 PEX_FIX;
 107                 out_le32((u32 *)cfg_data, temp);
 108                 break;
 109         default:
 110                 PEX_FIX;
 111                 out_le32((u32 *)cfg_data, val);
 112                 break;
 113         }
 114         PEX_FIX;
 115         return 0;
 116 }
 117
 118 static int
 119 indirect_read_config_byte_pcie(struct pci_controller *hose,
 120                               pci_dev_t dev,
 121                               int offset,
 122                               u8 *val)
 123 {
 124         u32 val32;
 125         indirect_read_config_pcie(hose,dev,offset,1,&val32);
 126         *val = (u8)val32;
 127         return 0;
 128 }
 129
 130 static int
 131 indirect_read_config_word_pcie(struct pci_controller *hose,
 132                               pci_dev_t dev,
 133                               int offset,
 134                               u16 *val)
 135 {
 136         u32 val32;
 137         indirect_read_config_pcie(hose,dev,offset,2,&val32);
 138         *val = (u16)val32;
 139         return 0;
 140 }
 141
 142 static int
 143 indirect_read_config_dword_pcie(struct pci_controller *hose,
 144                                pci_dev_t dev,
 145                                int offset,
 146                                u32 *val)
 147 {
 148         return indirect_read_config_pcie(hose,dev, offset,4,val);
 149 }
 150
 151 static int
 152 indirect_write_config_byte_pcie(struct pci_controller *hose,
 153                                pci_dev_t dev,
 154                                int offset,
 155                                u8 val)
 156 {
 157         return indirect_write_config_pcie(hose,dev, offset,1,(u32)val);
 158 }
 159
 160 static int
 161 indirect_write_config_word_pcie(struct pci_controller *hose,
 162                                pci_dev_t dev,
 163                                int offset,
 164                                unsigned short val)
 165 {
 166         return indirect_write_config_pcie(hose,dev, offset,2,(u32)val);
 167 }
 168
 169 static int
 170 indirect_write_config_dword_pcie(struct pci_controller *hose,
 171                                 pci_dev_t dev,
 172                                 int offset,
 173                                 u32 val)
 174 {
 175         return indirect_write_config_pcie(hose,dev, offset,4,val);
 176 }
 177
 178 void
 179 pcie_setup_indirect(struct pci_controller* hose,
 180                    u32 cfg_addr,
 181                    u32 cfg_data)
 182 {
 183         pci_set_ops(hose,
 184                     indirect_read_config_byte_pcie,
 185                     indirect_read_config_word_pcie,
 186                     indirect_read_config_dword_pcie,
 187                     indirect_write_config_byte_pcie,
 188                     indirect_write_config_word_pcie,
 189                     indirect_write_config_dword_pcie);
 190
 191         hose->cfg_addr = (unsigned int *) cfg_addr;
 192         hose->cfg_data = (unsigned char *) cfg_data;
 193 }
 194
 195 #endif  /* CONFIG_PCI */