4 * Driver for the Motorola Triple Speed Ethernet Controller
6 * This software may be used and distributed according to the
7 * terms of the GNU Public License, Version 2, incorporated
10 * (C) Copyright 2003, Motorola, Inc.
11 * maintained by Xianghua Xiao (x.xiao@motorola.com)
22 /* TSEC1 is offset 0x24000, TSEC2 is offset 0x25000
23 #define TSEC_BASE_ADDR (CFG_IMMR + 0x25000)
25 #define TSEC_BASE_ADDR (CFG_IMMR + 0x24000)
26 #define TSEC_MEM_SIZE 0x01000
28 #define MAC_ADDR_LEN 6
30 #define TSEC_TIMEOUT 1000000
31 #define TOUT_LOOP 1000000
33 /* MAC register bits */
34 #define MACCFG1_SOFT_RESET 0x80000000
35 #define MACCFG1_RESET_RX_MC 0x00080000
36 #define MACCFG1_RESET_TX_MC 0x00040000
37 #define MACCFG1_RESET_RX_FUN 0x00020000
38 #define MACCFG1_RESET_TX_FUN 0x00010000
39 #define MACCFG1_LOOPBACK 0x00000100
40 #define MACCFG1_RX_FLOW 0x00000020
41 #define MACCFG1_TX_FLOW 0x00000010
42 #define MACCFG1_SYNCD_RX_EN 0x00000008
43 #define MACCFG1_RX_EN 0x00000004
44 #define MACCFG1_SYNCD_TX_EN 0x00000002
45 #define MACCFG1_TX_EN 0x00000001
47 #define MACCFG2_INIT_SETTINGS 0x00007205
48 #define MACCFG2_FULL_DUPLEX 0x00000001
49 #define MACCFG2_IF 0x00000300
50 #define MACCFG2_MII 0x00000100
52 #define ECNTRL_INIT_SETTINGS 0x00001000
53 #define ECNTRL_TBI_MODE 0x00000020
55 #define TBIPA_VALUE 0x1f
56 #define MIIMCFG_INIT_VALUE 0x00000003
57 #define MIIMCFG_RESET 0x80000000
59 #define MIIMIND_BUSY 0x00000001
60 #define MIIMIND_NOTVALID 0x00000004
62 #define MIIM_CONTROL 0x00
63 #define MIIM_CONTROL_INIT 0x00001140
64 #define MIIM_ANEN 0x00001000
65 #define MIIM_CONTROL_RESET 0x00009140
67 #define MIIM_STATUS 0x1
68 #define MIIM_STATUS_AN_DONE 0x00000020
70 #define MIIM_GBIT_CONTROL 0x9
71 #define MIIM_GBIT_CONTROL_INIT 0xe00
73 #define MIIM_TBI_ANEX 0x6
74 #define MIIM_TBI_ANEX_NP 0x00000004
75 #define MIIM_TBI_ANEX_PRX 0x00000002
77 #define MIIM_TBI_ANLPBPA 0x5
78 #define MIIM_TBI_ANLPBPA_HALF 0x00000040
79 #define MIIM_TBI_ANLPBPA_FULL 0x00000020
81 #ifdef CONFIG_PHY_CIS8201
82 #define MIIM_AUX_CONSTAT 0x1c
83 #define MIIM_AUXCONSTAT_INIT 0x0004
84 #define MIIM_AUXCONSTAT_DUPLEX 0x0020
85 #define MIIM_AUXCONSTAT_SPEED 0x0018
86 #define MIIM_AUXCONSTAT_GBIT 0x0010
87 #define MIIM_AUXCONSTAT_100 0x0008
89 #define MIIM_EXT_CON1 0x17
90 #define MIIM_EXTCON1_INIT 0x0000
94 #ifdef CONFIG_PHY_M88E1011
96 #define MIIM_ANAR_INIT 0x1e1
98 #define MIIM_GBIT_CON 0x09
99 #define MIIM_GBIT_CON_ADVERT 0x0e00
101 #define MIIM_PHY_STATUS 0x11
102 #define MIIM_PHYSTAT_SPEED 0xc000
103 #define MIIM_PHYSTAT_GBIT 0x8000
104 #define MIIM_PHYSTAT_100 0x4000
105 #define MIIM_PHYSTAT_DUPLEX 0x2000
106 #define MIIM_PHYSTAT_SPDDONE 0x0800
107 #define MIIM_PHYSTAT_LINK 0x0400
110 #define MIIM_READ_COMMAND 0x00000001
112 #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
114 #define MINFLR_INIT_SETTINGS 0x00000040
116 #define DMACTRL_INIT_SETTINGS 0x000000c3
117 #define DMACTRL_GRS 0x00000010
118 #define DMACTRL_GTS 0x00000008
120 #define TSTAT_CLEAR_THALT 0x80000000
121 #define RSTAT_CLEAR_RHALT 0x00800000
123 /* Write value to the PHY at phyid to the register at offset, */
124 /* using the register space defined in regbase. Note that */
125 /* miimcfg needs to have the clock speed setup correctly. This */
126 /* macro will wait until the write is done before it finishes */
127 #define write_phy_reg(regbase, phyid, offset, value) do { \
128 int timeout=1000000; \
129 regbase->miimadd = (phyid << 8) | offset; \
130 regbase->miimcon = value; \
132 while((regbase->miimind & MIIMIND_BUSY) && timeout--); \
136 /* This works around errata in reseting the PHY */
137 #define RESET_ERRATA(regs, ID) do { \
138 write_phy_reg(regs, (ID), 0x1d, 0x1f); \
139 write_phy_reg(regs, (ID), 0x1e, 0x200c); \
140 write_phy_reg(regs, (ID), 0x1d, 0x5); \
141 write_phy_reg(regs, (ID), 0x1e, 0x0); \
142 write_phy_reg(regs, (ID), 0x1e, 0x100); \
145 #define IEVENT_INIT_CLEAR 0xffffffff
146 #define IEVENT_BABR 0x80000000
147 #define IEVENT_RXC 0x40000000
148 #define IEVENT_BSY 0x20000000
149 #define IEVENT_EBERR 0x10000000
150 #define IEVENT_MSRO 0x04000000
151 #define IEVENT_GTSC 0x02000000
152 #define IEVENT_BABT 0x01000000
153 #define IEVENT_TXC 0x00800000
154 #define IEVENT_TXE 0x00400000
155 #define IEVENT_TXB 0x00200000
156 #define IEVENT_TXF 0x00100000
157 #define IEVENT_IE 0x00080000
158 #define IEVENT_LC 0x00040000
159 #define IEVENT_CRL 0x00020000
160 #define IEVENT_XFUN 0x00010000
161 #define IEVENT_RXB0 0x00008000
162 #define IEVENT_GRSC 0x00000100
163 #define IEVENT_RXF0 0x00000080
165 #define IMASK_INIT_CLEAR 0x00000000
166 #define IMASK_TXEEN 0x00400000
167 #define IMASK_TXBEN 0x00200000
168 #define IMASK_TXFEN 0x00100000
169 #define IMASK_RXFEN0 0x00000080
172 /* Default Attribute fields */
173 #define ATTR_INIT_SETTINGS 0x000000c0
174 #define ATTRELI_INIT_SETTINGS 0x00000000
177 /* TxBD status field bits */
178 #define TXBD_READY 0x8000
179 #define TXBD_PADCRC 0x4000
180 #define TXBD_WRAP 0x2000
181 #define TXBD_INTERRUPT 0x1000
182 #define TXBD_LAST 0x0800
183 #define TXBD_CRC 0x0400
184 #define TXBD_DEF 0x0200
185 #define TXBD_HUGEFRAME 0x0080
186 #define TXBD_LATECOLLISION 0x0080
187 #define TXBD_RETRYLIMIT 0x0040
188 #define TXBD_RETRYCOUNTMASK 0x003c
189 #define TXBD_UNDERRUN 0x0002
190 #define TXBD_STATS 0x03ff
192 /* RxBD status field bits */
193 #define RXBD_EMPTY 0x8000
194 #define RXBD_RO1 0x4000
195 #define RXBD_WRAP 0x2000
196 #define RXBD_INTERRUPT 0x1000
197 #define RXBD_LAST 0x0800
198 #define RXBD_FIRST 0x0400
199 #define RXBD_MISS 0x0100
200 #define RXBD_BROADCAST 0x0080
201 #define RXBD_MULTICAST 0x0040
202 #define RXBD_LARGE 0x0020
203 #define RXBD_NONOCTET 0x0010
204 #define RXBD_SHORT 0x0008
205 #define RXBD_CRCERR 0x0004
206 #define RXBD_OVERRUN 0x0002
207 #define RXBD_TRUNCATED 0x0001
208 #define RXBD_STATS 0x003f
212 ushort status; /* Status Fields */
213 ushort length; /* Buffer length */
214 uint bufPtr; /* Buffer Pointer */
219 ushort status; /* Status Fields */
220 ushort length; /* Buffer Length */
221 uint bufPtr; /* Buffer Pointer */
224 typedef struct rmon_mib
226 /* Transmit and Receive Counters */
227 uint tr64; /* Transmit and Receive 64-byte Frame Counter */
228 uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */
229 uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */
230 uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */
231 uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */
232 uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */
233 uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */
234 /* Receive Counters */
235 uint rbyt; /* Receive Byte Counter */
236 uint rpkt; /* Receive Packet Counter */
237 uint rfcs; /* Receive FCS Error Counter */
238 uint rmca; /* Receive Multicast Packet (Counter) */
239 uint rbca; /* Receive Broadcast Packet */
240 uint rxcf; /* Receive Control Frame Packet */
241 uint rxpf; /* Receive Pause Frame Packet */
242 uint rxuo; /* Receive Unknown OP Code */
243 uint raln; /* Receive Alignment Error */
244 uint rflr; /* Receive Frame Length Error */
245 uint rcde; /* Receive Code Error */
246 uint rcse; /* Receive Carrier Sense Error */
247 uint rund; /* Receive Undersize Packet */
248 uint rovr; /* Receive Oversize Packet */
249 uint rfrg; /* Receive Fragments */
250 uint rjbr; /* Receive Jabber */
251 uint rdrp; /* Receive Drop */
252 /* Transmit Counters */
253 uint tbyt; /* Transmit Byte Counter */
254 uint tpkt; /* Transmit Packet */
255 uint tmca; /* Transmit Multicast Packet */
256 uint tbca; /* Transmit Broadcast Packet */
257 uint txpf; /* Transmit Pause Control Frame */
258 uint tdfr; /* Transmit Deferral Packet */
259 uint tedf; /* Transmit Excessive Deferral Packet */
260 uint tscl; /* Transmit Single Collision Packet */
262 uint tmcl; /* Transmit Multiple Collision Packet */
263 uint tlcl; /* Transmit Late Collision Packet */
264 uint txcl; /* Transmit Excessive Collision Packet */
265 uint tncl; /* Transmit Total Collision */
269 uint tdrp; /* Transmit Drop Frame */
270 uint tjbr; /* Transmit Jabber Frame */
271 uint tfcs; /* Transmit FCS Error */
272 uint txcf; /* Transmit Control Frame */
273 uint tovr; /* Transmit Oversize Frame */
274 uint tund; /* Transmit Undersize Frame */
275 uint tfrg; /* Transmit Fragments Frame */
276 /* General Registers */
277 uint car1; /* Carry Register One */
278 uint car2; /* Carry Register Two */
279 uint cam1; /* Carry Register One Mask */
280 uint cam2; /* Carry Register Two Mask */
283 typedef struct tsec_hash_regs
285 uint iaddr0; /* Individual Address Register 0 */
286 uint iaddr1; /* Individual Address Register 1 */
287 uint iaddr2; /* Individual Address Register 2 */
288 uint iaddr3; /* Individual Address Register 3 */
289 uint iaddr4; /* Individual Address Register 4 */
290 uint iaddr5; /* Individual Address Register 5 */
291 uint iaddr6; /* Individual Address Register 6 */
292 uint iaddr7; /* Individual Address Register 7 */
294 uint gaddr0; /* Group Address Register 0 */
295 uint gaddr1; /* Group Address Register 1 */
296 uint gaddr2; /* Group Address Register 2 */
297 uint gaddr3; /* Group Address Register 3 */
298 uint gaddr4; /* Group Address Register 4 */
299 uint gaddr5; /* Group Address Register 5 */
300 uint gaddr6; /* Group Address Register 6 */
301 uint gaddr7; /* Group Address Register 7 */
307 /* General Control and Status Registers (0x2_n000) */
310 uint ievent; /* Interrupt Event */
311 uint imask; /* Interrupt Mask */
312 uint edis; /* Error Disabled */
314 uint ecntrl; /* Ethernet Control */
315 uint minflr; /* Minimum Frame Length */
316 uint ptv; /* Pause Time Value */
317 uint dmactrl; /* DMA Control */
318 uint tbipa; /* TBI PHY Address */
323 /* Transmit Control and Status Registers (0x2_n100) */
324 uint tctrl; /* Transmit Control */
325 uint tstat; /* Transmit Status */
327 uint tbdlen; /* Tx BD Data Length */
329 uint ctbptr; /* Current TxBD Pointer */
331 uint tbptr; /* TxBD Pointer */
335 uint tbase; /* TxBD Base Address */
337 uint ostbd; /* Out of Sequence TxBD */
338 uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
341 /* Receive Control and Status Registers (0x2_n300) */
342 uint rctrl; /* Receive Control */
343 uint rstat; /* Receive Status */
345 uint rbdlen; /* RxBD Data Length */
348 uint crbptr; /* Current Receive Buffer Pointer */
350 uint mrblr; /* Maximum Receive Buffer Length */
352 uint rbptr; /* RxBD Pointer */
356 uint rbase; /* RxBD Base Address */
359 /* MAC Registers (0x2_n500) */
360 uint maccfg1; /* MAC Configuration #1 */
361 uint maccfg2; /* MAC Configuration #2 */
362 uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */
363 uint hafdup; /* Half-duplex */
364 uint maxfrm; /* Maximum Frame */
370 uint miimcfg; /* MII Management: Configuration */
371 uint miimcom; /* MII Management: Command */
372 uint miimadd; /* MII Management: Address */
373 uint miimcon; /* MII Management: Control */
374 uint miimstat; /* MII Management: Status */
375 uint miimind; /* MII Management: Indicators */
379 uint ifstat; /* Interface Status */
380 uint macstnaddr1; /* Station Address, part 1 */
381 uint macstnaddr2; /* Station Address, part 2 */
387 /* RMON MIB Registers (0x2_n680-0x2_n73c) */
391 /* Hash Function Registers (0x2_n800) */
396 /* Pattern Registers (0x2_nb00) */
398 uint attr; /* Default Attribute Register */
399 uint attreli; /* Default Attribute Extract Length and Index */
401 /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
405 #endif /* __TSEC_H */