3 * Freescale Three Speed Ethernet Controller driver
5 * This software may be used and distributed according to the
6 * terms of the GNU Public License, Version 2, incorporated
9 * Copyright 2004 Freescale Semiconductor.
10 * (C) Copyright 2003, Motorola, Inc.
11 * maintained by Jon Loeliger (loeliger@freescale.com)
23 #if defined(CONFIG_TSEC_ENET)
28 static uint rxIdx; /* index of the current RX buffer */
29 static uint txIdx; /* index of the current TX buffer */
31 typedef volatile struct rtxbd {
32 txbd8_t txbd[TX_BUF_CNT];
33 rxbd8_t rxbd[PKTBUFSRX];
36 struct tsec_info_struct {
39 unsigned int phyregidx;
43 /* The tsec_info structure contains 3 values which the
44 * driver uses to determine how to operate a given ethernet
45 * device. For now, the structure is initialized with the
46 * knowledge that all current implementations have 2 TSEC
47 * devices, and one FEC. The information needed is:
48 * phyaddr - The address of the PHY which is attached to
51 * gigabit - This variable indicates whether the device
52 * supports gigabit speed ethernet
54 * phyregidx - This variable specifies which ethernet device
55 * controls the MII Management registers which are connected
56 * to the PHY. For 8540/8560, only TSEC1 (index 0) has
57 * access to the PHYs, so all of the entries have "0".
59 * The values specified in the table are taken from the board's
60 * config file in include/configs/. When implementing a new
61 * board with ethernet capability, it is necessary to define:
71 static struct tsec_info_struct tsec_info[] = {
72 #ifdef CONFIG_MPC85XX_TSEC1
73 {TSEC1_PHY_ADDR, 1, TSEC1_PHYIDX},
75 #ifdef CONFIG_MPC85XX_TSEC2
76 {TSEC2_PHY_ADDR, 1, TSEC2_PHYIDX},
78 #ifdef CONFIG_MPC85XX_FEC
79 {FEC_PHY_ADDR, 0, FEC_PHYIDX},
83 #define MAXCONTROLLERS 3
85 static int relocated = 0;
87 static struct tsec_private *privlist[MAXCONTROLLERS];
90 static RTXBD rtx __attribute__ ((aligned(8)));
92 #error "rtx must be 64-bit aligned"
95 static int tsec_send(struct eth_device* dev, volatile void *packet, int length);
96 static int tsec_recv(struct eth_device* dev);
97 static int tsec_init(struct eth_device* dev, bd_t * bd);
98 static void tsec_halt(struct eth_device* dev);
99 static void init_registers(volatile tsec_t *regs);
100 static void startup_tsec(struct eth_device *dev);
101 static int init_phy(struct eth_device *dev);
102 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
103 uint read_phy_reg(struct tsec_private *priv, uint regnum);
104 struct phy_info * get_phy_info(struct eth_device *dev);
105 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
106 static void adjust_link(struct eth_device *dev);
107 static void relocate_cmds(void);
109 /* Initialize device structure. Returns success if PHY
110 * initialization succeeded (i.e. if it recognizes the PHY)
112 int tsec_initialize(bd_t *bis, int index)
114 struct eth_device* dev;
116 struct tsec_private *priv;
118 dev = (struct eth_device*) malloc(sizeof *dev);
123 memset(dev, 0, sizeof *dev);
125 priv = (struct tsec_private *) malloc(sizeof(*priv));
130 privlist[index] = priv;
131 priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index*TSEC_SIZE);
132 priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
133 tsec_info[index].phyregidx*TSEC_SIZE);
135 priv->phyaddr = tsec_info[index].phyaddr;
136 priv->gigabit = tsec_info[index].gigabit;
138 sprintf(dev->name, "MOTO ENET%d", index);
141 dev->init = tsec_init;
142 dev->halt = tsec_halt;
143 dev->send = tsec_send;
144 dev->recv = tsec_recv;
146 /* Tell u-boot to get the addr from the env */
148 dev->enetaddr[i] = 0;
154 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
155 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
157 /* Try to initialize PHY here, and return */
158 return init_phy(dev);
162 /* Initializes data structures and registers for the controller,
163 * and brings the interface up. Returns the link status, meaning
164 * that it returns success if the link is up, failure otherwise.
165 * This allows u-boot to find the first active controller. */
166 int tsec_init(struct eth_device* dev, bd_t * bd)
169 char tmpbuf[MAC_ADDR_LEN];
171 struct tsec_private *priv = (struct tsec_private *)dev->priv;
172 volatile tsec_t *regs = priv->regs;
174 /* Make sure the controller is stopped */
177 /* Init MACCFG2. Defaults to GMII */
178 regs->maccfg2 = MACCFG2_INIT_SETTINGS;
181 regs->ecntrl = ECNTRL_INIT_SETTINGS;
183 /* Copy the station address into the address registers.
184 * Backwards, because little endian MACS are dumb */
185 for(i=0;i<MAC_ADDR_LEN;i++) {
186 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
188 (uint)(regs->macstnaddr1) = *((uint *)(tmpbuf));
190 tempval = *((uint *)(tmpbuf +4));
192 (uint)(regs->macstnaddr2) = tempval;
194 /* reset the indices to zero */
198 /* Clear out (for the most part) the other registers */
199 init_registers(regs);
201 /* Ready the device for tx/rx */
204 /* If there's no link, fail */
210 /* Write value to the device's PHY through the registers
211 * specified in priv, modifying the register specified in regnum.
212 * It will wait for the write to be done (or for a timeout to
213 * expire) before exiting
215 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value)
217 volatile tsec_t *regbase = priv->phyregs;
218 uint phyid = priv->phyaddr;
221 regbase->miimadd = (phyid << 8) | regnum;
222 regbase->miimcon = value;
226 while((regbase->miimind & MIIMIND_BUSY) && timeout--);
230 /* Reads register regnum on the device's PHY through the
231 * registers specified in priv. It lowers and raises the read
232 * command, and waits for the data to become valid (miimind
233 * notvalid bit cleared), and the bus to cease activity (miimind
234 * busy bit cleared), and then returns the value
236 uint read_phy_reg(struct tsec_private *priv, uint regnum)
239 volatile tsec_t *regbase = priv->phyregs;
240 uint phyid = priv->phyaddr;
242 /* Put the address of the phy, and the register
243 * number into MIIMADD */
244 regbase->miimadd = (phyid << 8) | regnum;
246 /* Clear the command register, and wait */
247 regbase->miimcom = 0;
250 /* Initiate a read command, and wait */
251 regbase->miimcom = MIIM_READ_COMMAND;
254 /* Wait for the the indication that the read is done */
255 while((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY)));
257 /* Grab the value read from the PHY */
258 value = regbase->miimstat;
264 /* Discover which PHY is attached to the device, and configure it
265 * properly. If the PHY is not recognized, then return 0
266 * (failure). Otherwise, return 1
268 static int init_phy(struct eth_device *dev)
270 struct tsec_private *priv = (struct tsec_private *)dev->priv;
271 struct phy_info *curphy;
273 /* Assign a Physical address to the TBI */
274 priv->regs->tbipa=TBIPA_VALUE;
279 /* Get the cmd structure corresponding to the attached
281 curphy = get_phy_info(dev);
284 printf("%s: No PHY found\n", dev->name);
289 priv->phyinfo = curphy;
291 phy_run_commands(priv, priv->phyinfo->config);
297 /* Returns which value to write to the control register. */
298 /* For 10/100, the value is slightly different */
299 uint mii_cr_init(uint mii_reg, struct tsec_private *priv)
302 return MIIM_CONTROL_INIT;
308 /* Parse the status register for link, and then do
309 * auto-negotiation */
310 uint mii_parse_sr(uint mii_reg, struct tsec_private *priv)
312 uint timeout = TSEC_TIMEOUT;
314 if(mii_reg & MIIM_STATUS_LINK)
320 while((!(mii_reg & MIIM_STATUS_AN_DONE)) && timeout--)
321 mii_reg = read_phy_reg(priv, MIIM_STATUS);
328 /* Parse the 88E1011's status register for speed and duplex
330 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private *priv)
334 if(mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
339 speed = (mii_reg &MIIM_88E1011_PHYSTAT_SPEED);
342 case MIIM_88E1011_PHYSTAT_GBIT:
345 case MIIM_88E1011_PHYSTAT_100:
356 /* Parse the cis8201's status register for speed and duplex
358 uint mii_parse_cis8201(uint mii_reg, struct tsec_private *priv)
362 if(mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
367 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
369 case MIIM_CIS8201_AUXCONSTAT_GBIT:
372 case MIIM_CIS8201_AUXCONSTAT_100:
384 /* Parse the DM9161's status register for speed and duplex
386 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private *priv)
388 if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
393 if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
402 /* Hack to write all 4 PHYs with the LED values */
403 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private *priv)
406 volatile tsec_t *regbase = priv->phyregs;
409 for(phyid=0;phyid<4;phyid++) {
410 regbase->miimadd = (phyid << 8) | mii_reg;
411 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
415 while((regbase->miimind & MIIMIND_BUSY) && timeout--);
418 return MIIM_CIS8204_SLEDCON_INIT;
422 /* Initialized required registers to appropriate values, zeroing
423 * those we don't care about (unless zero is bad, in which case,
424 * choose a more appropriate value) */
425 static void init_registers(volatile tsec_t *regs)
428 regs->ievent = IEVENT_INIT_CLEAR;
430 regs->imask = IMASK_INIT_CLEAR;
432 regs->hash.iaddr0 = 0;
433 regs->hash.iaddr1 = 0;
434 regs->hash.iaddr2 = 0;
435 regs->hash.iaddr3 = 0;
436 regs->hash.iaddr4 = 0;
437 regs->hash.iaddr5 = 0;
438 regs->hash.iaddr6 = 0;
439 regs->hash.iaddr7 = 0;
441 regs->hash.gaddr0 = 0;
442 regs->hash.gaddr1 = 0;
443 regs->hash.gaddr2 = 0;
444 regs->hash.gaddr3 = 0;
445 regs->hash.gaddr4 = 0;
446 regs->hash.gaddr5 = 0;
447 regs->hash.gaddr6 = 0;
448 regs->hash.gaddr7 = 0;
450 regs->rctrl = 0x00000000;
452 /* Init RMON mib registers */
453 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
455 regs->rmon.cam1 = 0xffffffff;
456 regs->rmon.cam2 = 0xffffffff;
458 regs->mrblr = MRBLR_INIT_SETTINGS;
460 regs->minflr = MINFLR_INIT_SETTINGS;
462 regs->attr = ATTR_INIT_SETTINGS;
463 regs->attreli = ATTRELI_INIT_SETTINGS;
468 /* Configure maccfg2 based on negotiated speed and duplex
469 * reported by PHY handling code */
470 static void adjust_link(struct eth_device *dev)
472 struct tsec_private *priv = (struct tsec_private *)dev->priv;
473 volatile tsec_t *regs = priv->regs;
476 if(priv->duplexity != 0)
477 regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
479 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
481 switch(priv->speed) {
483 regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
488 regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
492 printf("%s: Speed was bad\n", dev->name);
496 printf("Speed: %d, %s duplex\n", priv->speed,
497 (priv->duplexity) ? "full" : "half");
500 printf("%s: No link.\n", dev->name);
505 /* Set up the buffers and their descriptors, and bring up the
507 static void startup_tsec(struct eth_device *dev)
510 struct tsec_private *priv = (struct tsec_private *)dev->priv;
511 volatile tsec_t *regs = priv->regs;
513 /* Point to the buffer descriptors */
514 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
515 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
517 /* Initialize the Rx Buffer descriptors */
518 for (i = 0; i < PKTBUFSRX; i++) {
519 rtx.rxbd[i].status = RXBD_EMPTY;
520 rtx.rxbd[i].length = 0;
521 rtx.rxbd[i].bufPtr = (uint)NetRxPackets[i];
523 rtx.rxbd[PKTBUFSRX -1].status |= RXBD_WRAP;
525 /* Initialize the TX Buffer Descriptors */
526 for(i=0; i<TX_BUF_CNT; i++) {
527 rtx.txbd[i].status = 0;
528 rtx.txbd[i].length = 0;
529 rtx.txbd[i].bufPtr = 0;
531 rtx.txbd[TX_BUF_CNT -1].status |= TXBD_WRAP;
533 /* Start up the PHY */
534 phy_run_commands(priv, priv->phyinfo->startup);
537 /* Enable Transmit and Receive */
538 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
540 /* Tell the DMA it is clear to go */
541 regs->dmactrl |= DMACTRL_INIT_SETTINGS;
542 regs->tstat = TSTAT_CLEAR_THALT;
543 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
546 /* This returns the status bits of the device. The return value
547 * is never checked, and this is what the 8260 driver did, so we
548 * do the same. Presumably, this would be zero if there were no
550 static int tsec_send(struct eth_device* dev, volatile void *packet, int length)
554 struct tsec_private *priv = (struct tsec_private *)dev->priv;
555 volatile tsec_t *regs = priv->regs;
557 /* Find an empty buffer descriptor */
558 for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
559 if (i >= TOUT_LOOP) {
560 debug ("%s: tsec: tx buffers full\n", dev->name);
565 rtx.txbd[txIdx].bufPtr = (uint)packet;
566 rtx.txbd[txIdx].length = length;
567 rtx.txbd[txIdx].status |= (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
569 /* Tell the DMA to go */
570 regs->tstat = TSTAT_CLEAR_THALT;
572 /* Wait for buffer to be transmitted */
573 for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
574 if (i >= TOUT_LOOP) {
575 debug ("%s: tsec: tx error\n", dev->name);
580 txIdx = (txIdx + 1) % TX_BUF_CNT;
581 result = rtx.txbd[txIdx].status & TXBD_STATS;
586 static int tsec_recv(struct eth_device* dev)
589 struct tsec_private *priv = (struct tsec_private *)dev->priv;
590 volatile tsec_t *regs = priv->regs;
592 while(!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
594 length = rtx.rxbd[rxIdx].length;
596 /* Send the packet up if there were no errors */
597 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
598 NetReceive(NetRxPackets[rxIdx], length - 4);
600 printf("Got error %x\n",
601 (rtx.rxbd[rxIdx].status & RXBD_STATS));
604 rtx.rxbd[rxIdx].length = 0;
606 /* Set the wrap bit if this is the last element in the list */
607 rtx.rxbd[rxIdx].status = RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
609 rxIdx = (rxIdx + 1) % PKTBUFSRX;
612 if(regs->ievent&IEVENT_BSY) {
613 regs->ievent = IEVENT_BSY;
614 regs->rstat = RSTAT_CLEAR_RHALT;
622 /* Stop the interface */
623 static void tsec_halt(struct eth_device* dev)
625 struct tsec_private *priv = (struct tsec_private *)dev->priv;
626 volatile tsec_t *regs = priv->regs;
628 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
629 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
631 while(!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC)));
633 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
635 /* Shut down the PHY, as needed */
636 phy_run_commands(priv, priv->phyinfo->shutdown);
640 struct phy_info phy_info_M88E1011S = {
644 (struct phy_cmd[]) { /* config */
645 /* Reset and configure the PHY */
646 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
648 {0x1e, 0x200c, NULL},
652 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
653 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
654 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
655 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
658 (struct phy_cmd[]) { /* startup */
659 /* Status is read once to clear old link state */
660 {MIIM_STATUS, miim_read, NULL},
662 {MIIM_STATUS, miim_read, &mii_parse_sr},
663 /* Read the status */
664 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
667 (struct phy_cmd[]) { /* shutdown */
672 struct phy_info phy_info_cis8204 = {
676 (struct phy_cmd[]) { /* config */
677 /* Override PHY config settings */
678 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
679 /* Configure some basic stuff */
680 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
681 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, &mii_cis8204_fixled},
682 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, NULL},
685 (struct phy_cmd[]) { /* startup */
686 /* Read the Status (2x to make sure link is right) */
687 {MIIM_STATUS, miim_read, NULL},
689 {MIIM_STATUS, miim_read, &mii_parse_sr},
690 /* Read the status */
691 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
694 (struct phy_cmd[]) { /* shutdown */
700 struct phy_info phy_info_cis8201 = {
704 (struct phy_cmd[]) { /* config */
705 /* Override PHY config settings */
706 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
707 /* Set up the interface mode */
708 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL},
709 /* Configure some basic stuff */
710 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
713 (struct phy_cmd[]) { /* startup */
714 /* Read the Status (2x to make sure link is right) */
715 {MIIM_STATUS, miim_read, NULL},
717 {MIIM_STATUS, miim_read, &mii_parse_sr},
718 /* Read the status */
719 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
722 (struct phy_cmd[]) { /* shutdown */
728 struct phy_info phy_info_dm9161 = {
732 (struct phy_cmd[]) { /* config */
733 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
734 /* Do not bypass the scrambler/descrambler */
735 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
736 /* Clear 10BTCSR to default */
737 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL},
738 /* Configure some basic stuff */
739 {MIIM_CONTROL, MIIM_CR_INIT, NULL},
740 /* Restart Auto Negotiation */
741 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
744 (struct phy_cmd[]) { /* startup */
745 /* Status is read once to clear old link state */
746 {MIIM_STATUS, miim_read, NULL},
748 {MIIM_STATUS, miim_read, &mii_parse_sr},
749 /* Read the status */
750 {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr},
753 (struct phy_cmd[]) { /* shutdown */
758 struct phy_info *phy_info[] = {
769 /* Grab the identifier of the device's PHY, and search through
770 * all of the known PHYs to see if one matches. If so, return
771 * it, if not, return NULL */
772 struct phy_info * get_phy_info(struct eth_device *dev)
774 struct tsec_private *priv = (struct tsec_private *)dev->priv;
775 uint phy_reg, phy_ID;
777 struct phy_info *theInfo = NULL;
779 /* Grab the bits from PHYIR1, and put them in the upper half */
780 phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
781 phy_ID = (phy_reg & 0xffff) << 16;
783 /* Grab the bits from PHYIR2, and put them in the lower half */
784 phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
785 phy_ID |= (phy_reg & 0xffff);
787 /* loop through all the known PHY types, and find one that */
788 /* matches the ID we read from the PHY. */
789 for(i=0; phy_info[i]; i++) {
790 if(phy_info[i]->id == (phy_ID >> phy_info[i]->shift))
791 theInfo = phy_info[i];
796 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
799 printf("%s: PHY is %s (%x)\n", dev->name, theInfo->name,
807 /* Execute the given series of commands on the given device's
808 * PHY, running functions as necessary*/
809 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
813 volatile tsec_t *phyregs = priv->phyregs;
815 phyregs->miimcfg = MIIMCFG_RESET;
817 phyregs->miimcfg = MIIMCFG_INIT_VALUE;
819 while(phyregs->miimind & MIIMIND_BUSY);
821 for(i=0;cmd->mii_reg != miim_end;i++) {
822 if(cmd->mii_data == miim_read) {
823 result = read_phy_reg(priv, cmd->mii_reg);
825 if(cmd->funct != NULL)
826 (*(cmd->funct))(result, priv);
829 if(cmd->funct != NULL)
830 result = (*(cmd->funct))(cmd->mii_reg, priv);
832 result = cmd->mii_data;
834 write_phy_reg(priv, cmd->mii_reg, result);
842 /* Relocate the function pointers in the phy cmd lists */
843 static void relocate_cmds(void)
845 struct phy_cmd **cmdlistptr;
848 DECLARE_GLOBAL_DATA_PTR;
850 for(i=0; phy_info[i]; i++) {
851 /* First thing's first: relocate the pointers to the
852 * PHY command structures (the structs were done) */
853 phy_info[i] = (struct phy_info *) ((uint)phy_info[i]
855 phy_info[i]->name += gd->reloc_off;
856 phy_info[i]->config =
857 (struct phy_cmd *)((uint)phy_info[i]->config
859 phy_info[i]->startup =
860 (struct phy_cmd *)((uint)phy_info[i]->startup
862 phy_info[i]->shutdown =
863 (struct phy_cmd *)((uint)phy_info[i]->shutdown
866 cmdlistptr = &phy_info[i]->config;
868 for(;cmdlistptr <= &phy_info[i]->shutdown;cmdlistptr++) {
870 for(cmd=*cmdlistptr;cmd->mii_reg != miim_end;cmd++) {
871 /* Only relocate non-NULL pointers */
873 cmd->funct += gd->reloc_off;
885 #ifndef CONFIG_BITBANGMII
887 struct tsec_private * get_priv_for_phy(unsigned char phyaddr)
891 for(i=0;i<MAXCONTROLLERS;i++) {
892 if(privlist[i]->phyaddr == phyaddr)
900 * Read a MII PHY register.
905 int miiphy_read(unsigned char addr, unsigned char reg, unsigned short *value)
908 struct tsec_private *priv = get_priv_for_phy(addr);
911 printf("Can't read PHY at address %d\n", addr);
915 ret = (unsigned short)read_phy_reg(priv, reg);
922 * Write a MII PHY register.
927 int miiphy_write(unsigned char addr, unsigned char reg, unsigned short value)
929 struct tsec_private *priv = get_priv_for_phy(addr);
932 printf("Can't write PHY at address %d\n", addr);
936 write_phy_reg(priv, reg, value);
941 #endif /* CONFIG_BITBANGMII */
943 #endif /* CONFIG_TSEC_ENET */