2 * Copyright 2004, 2007 Freescale Semiconductor.
3 * Copyright (C) 2003 Motorola,Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
26 * The processor starts at 0xfffffffc and the code is first executed in the
27 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
35 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
37 #include <ppc_asm.tmpl>
40 #include <asm/cache.h>
43 #ifndef CONFIG_IDENT_STRING
44 #define CONFIG_IDENT_STRING ""
48 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
51 * Set up GOT: Global Offset Table
53 * Use r14 to access the GOT
56 GOT_ENTRY(_GOT2_TABLE_)
57 GOT_ENTRY(_FIXUP_TABLE_)
60 GOT_ENTRY(_start_of_vectors)
61 GOT_ENTRY(_end_of_vectors)
62 GOT_ENTRY(transfer_to_handler)
66 GOT_ENTRY(__bss_start)
70 * e500 Startup -- after reset only the last 4KB of the effective
71 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
72 * section is located at THIS LAST page and basically does three
73 * things: clear some registers, set up exception tables and
74 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
75 * continue the boot procedure.
77 * Once the boot rom is mapped by TLB entries we can proceed
78 * with normal startup.
87 /* clear registers/arrays not reset by hardware */
91 mtspr L1CSR0,r0 /* invalidate d-cache */
92 mtspr L1CSR1,r0 /* invalidate i-cache */
95 mtspr DBSR,r1 /* Clear all valid bits */
98 * Enable L1 Caches early
102 lis r2,L1CSR0_CPE@H /* enable parity */
104 mtspr L1CSR0,r2 /* enable L1 Dcache */
106 mtspr L1CSR1,r2 /* enable L1 Icache */
110 /* Setup interrupt vectors */
115 mtspr IVOR0,r1 /* 0: Critical input */
117 mtspr IVOR1,r1 /* 1: Machine check */
119 mtspr IVOR2,r1 /* 2: Data storage */
121 mtspr IVOR3,r1 /* 3: Instruction storage */
123 mtspr IVOR4,r1 /* 4: External interrupt */
125 mtspr IVOR5,r1 /* 5: Alignment */
127 mtspr IVOR6,r1 /* 6: Program check */
129 mtspr IVOR7,r1 /* 7: floating point unavailable */
131 mtspr IVOR8,r1 /* 8: System call */
132 /* 9: Auxiliary processor unavailable(unsupported) */
134 mtspr IVOR10,r1 /* 10: Decrementer */
136 mtspr IVOR11,r1 /* 11: Interval timer */
138 mtspr IVOR12,r1 /* 12: Watchdog timer */
140 mtspr IVOR13,r1 /* 13: Data TLB error */
142 mtspr IVOR14,r1 /* 14: Instruction TLB error */
144 mtspr IVOR15,r1 /* 15: Debug */
148 * After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e.
149 * 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB
150 * region before we can access any CCSR registers such as L2
151 * registers, Local Access Registers,etc. We will also re-allocate
152 * CFG_CCSRBAR_DEFAULT to CFG_CCSRBAR immediately after TLB1 setup.
154 * Please refer to board-specif directory for TLB1 entry configuration.
155 * (e.g. board/<yourboard>/init.S)
160 lwzu r4,0(r5) /* how many TLB1 entries we actually use */
178 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
179 /* Special sequence needed to update CCSRBAR itself */
180 lis r4,CFG_CCSRBAR_DEFAULT@h
181 ori r4,r4,CFG_CCSRBAR_DEFAULT@l
184 ori r5,r5,CFG_CCSRBAR@l
195 lwz r5,CFG_CCSRBAR@l(r3)
200 /* set up local access windows, defined at board/<boardname>/init.S */
202 ori r7,r7,CFG_CCSRBAR@l
206 lwzu r5,0(r6) /* how many windows we actually use */
209 li r2,0x0c28 /* the first pair is reserved for */
210 li r1,0x0c30 /* boot-over-rio-or-pci */
220 /* Clear and set up some registers. */
225 mtspr DEC,r0 /* prevent dec exceptions */
226 mttbl r0 /* prevent fit & wdt exceptions */
228 mtspr TSR,r1 /* clear all timer exception status */
229 mtspr TCR,r0 /* disable all */
230 mtspr ESR,r0 /* clear exception syndrome register */
231 mtspr MCSR,r0 /* machine check syndrome register */
232 mtxer r0 /* clear integer exception register */
233 lis r1,0x0002 /* set CE bit (Critical Exceptions) */
234 ori r1,r1,0x1200 /* set ME/DE bit */
235 mtmsr r1 /* change MSR */
238 /* Enable Time Base and Select Time Base Clock */
239 lis r0,HID0_EMCP@h /* Enable machine check */
240 #if defined(CONFIG_ENABLE_36BIT_PHYS)
241 ori r0,r0,(HID0_TBEN|HID0_ENMAS7)@l /* Enable Timebase & MAS7 */
243 ori r0,r0,HID0_TBEN@l /* enable Timebase */
247 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
250 /* Enable Branch Prediction */
251 #if defined(CONFIG_BTB)
252 li r0,0x201 /* BBFI = 1, BPEN = 1 */
256 #if defined(CFG_INIT_DBCR)
259 mtspr DBSR,r1 /* Clear all status bits */
260 lis r0,CFG_INIT_DBCR@h /* DBCR0[IDM] must be set */
261 ori r0,r0,CFG_INIT_DBCR@l
265 /* L1 DCache is used for initial RAM */
267 /* Allocate Initial RAM in data cache.
269 lis r3,CFG_INIT_RAM_ADDR@h
270 ori r3,r3,CFG_INIT_RAM_ADDR@l
273 /* cache size * 1024 / (2 * L1 line size) */
274 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
280 addi r3,r3,CFG_CACHELINE_SIZE
283 /* Jump out the last 4K page and continue to 'normal' start */
287 /* Calculate absolute address in FLASH and jump there */
288 /*--------------------------------------------------------------*/
289 lis r3,CFG_MONITOR_BASE@h
290 ori r3,r3,CFG_MONITOR_BASE@l
291 addi r3,r3,_start_cont - _start + _START_OFFSET
299 .long 0x27051956 /* U-BOOT Magic Number */
300 .globl version_string
302 .ascii U_BOOT_VERSION
303 .ascii " (", __DATE__, " - ", __TIME__, ")"
304 .ascii CONFIG_IDENT_STRING, "\0"
309 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
310 lis r1,CFG_INIT_RAM_ADDR@h
311 ori r1,r1,CFG_INIT_SP_OFFSET@l
315 stwu r0,-4(r1) /* Terminate call chain */
317 stwu r1,-8(r1) /* Save back chain and move SP */
318 lis r0,RESET_VECTOR@h /* Address of reset vector */
319 ori r0,r0,RESET_VECTOR@l
320 stwu r1,-8(r1) /* Save back chain and move SP */
321 stw r0,+12(r1) /* Save return addr (underflow vect) */
328 . = EXC_OFF_SYS_RESET
329 .globl _start_of_vectors
332 /* Critical input. */
333 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
336 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
338 /* Data Storage exception. */
339 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
341 /* Instruction Storage exception. */
342 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
344 /* External Interrupt exception. */
345 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
347 /* Alignment exception. */
350 EXCEPTION_PROLOG(SRR0, SRR1)
355 addi r3,r1,STACK_FRAME_OVERHEAD
357 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
358 lwz r6,GOT(transfer_to_handler)
362 .long AlignmentException - _start + _START_OFFSET
363 .long int_return - _start + _START_OFFSET
365 /* Program check exception */
368 EXCEPTION_PROLOG(SRR0, SRR1)
369 addi r3,r1,STACK_FRAME_OVERHEAD
371 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
372 lwz r6,GOT(transfer_to_handler)
376 .long ProgramCheckException - _start + _START_OFFSET
377 .long int_return - _start + _START_OFFSET
379 /* No FPU on MPC85xx. This exception is not supposed to happen.
381 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
385 * r0 - SYSCALL number
389 addis r11,r0,0 /* get functions table addr */
390 ori r11,r11,0 /* Note: this code is patched in trap_init */
391 addis r12,r0,0 /* get number of functions */
397 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
401 li r20,0xd00-4 /* Get stack pointer */
403 subi r12,r12,12 /* Adjust stack pointer */
404 li r0,0xc00+_end_back-SystemCall
405 cmplw 0,r0,r12 /* Check stack overflow */
416 li r12,0xc00+_back-SystemCall
424 mfmsr r11 /* Disable interrupts */
428 SYNC /* Some chip revs need this... */
432 li r12,0xd00-4 /* restore regs */
442 addi r12,r12,12 /* Adjust stack pointer */
450 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
451 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
452 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
454 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
455 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
457 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
459 .globl _end_of_vectors
463 . = . + (0x100 - ( . & 0xff )) /* align for debug */
466 * This code finishes saving the registers to the exception frame
467 * and jumps to the appropriate handler for the exception.
468 * Register r21 is pointer into trap frame, r1 has new stack pointer.
470 .globl transfer_to_handler
482 andi. r24,r23,0x3f00 /* get vector offset */
486 mtspr SPRG2,r22 /* r1 is now kernel sp */
488 lwz r24,0(r23) /* virtual address of handler */
489 lwz r23,4(r23) /* where to go when done */
494 rfi /* jump to handler, enable MMU */
497 mfmsr r28 /* Disable interrupts */
501 SYNC /* Some chip revs need this... */
516 lwz r2,_NIP(r1) /* Restore environment */
527 mfmsr r28 /* Disable interrupts */
531 SYNC /* Some chip revs need this... */
546 lwz r2,_NIP(r1) /* Restore environment */
557 mfmsr r28 /* Disable interrupts */
561 SYNC /* Some chip revs need this... */
576 lwz r2,_NIP(r1) /* Restore environment */
590 ori r0,r0,L1CSR1_ICFI
595 blr /* entire I cache */
599 ori r0,r0,L1CSR0_DCFI
619 .globl icache_disable
632 andi. r3,r3,L1CSR1_ICE
650 .globl dcache_disable
663 andi. r3,r3,L1CSR0_DCE
686 /*------------------------------------------------------------------------------- */
688 /* Description: Input 8 bits */
689 /*------------------------------------------------------------------------------- */
695 /*------------------------------------------------------------------------------- */
697 /* Description: Output 8 bits */
698 /*------------------------------------------------------------------------------- */
705 /*------------------------------------------------------------------------------- */
706 /* Function: out16 */
707 /* Description: Output 16 bits */
708 /*------------------------------------------------------------------------------- */
715 /*------------------------------------------------------------------------------- */
716 /* Function: out16r */
717 /* Description: Byte reverse and output 16 bits */
718 /*------------------------------------------------------------------------------- */
725 /*------------------------------------------------------------------------------- */
726 /* Function: out32 */
727 /* Description: Output 32 bits */
728 /*------------------------------------------------------------------------------- */
735 /*------------------------------------------------------------------------------- */
736 /* Function: out32r */
737 /* Description: Byte reverse and output 32 bits */
738 /*------------------------------------------------------------------------------- */
745 /*------------------------------------------------------------------------------- */
747 /* Description: Input 16 bits */
748 /*------------------------------------------------------------------------------- */
754 /*------------------------------------------------------------------------------- */
755 /* Function: in16r */
756 /* Description: Input 16 bits and byte reverse */
757 /*------------------------------------------------------------------------------- */
763 /*------------------------------------------------------------------------------- */
765 /* Description: Input 32 bits */
766 /*------------------------------------------------------------------------------- */
772 /*------------------------------------------------------------------------------- */
773 /* Function: in32r */
774 /* Description: Input 32 bits and byte reverse */
775 /*------------------------------------------------------------------------------- */
781 /*------------------------------------------------------------------------------- */
782 /* Function: ppcDcbf */
783 /* Description: Data Cache block flush */
784 /* Input: r3 = effective address */
786 /*------------------------------------------------------------------------------- */
792 /*------------------------------------------------------------------------------- */
793 /* Function: ppcDcbi */
794 /* Description: Data Cache block Invalidate */
795 /* Input: r3 = effective address */
797 /*------------------------------------------------------------------------------- */
803 /*--------------------------------------------------------------------------
805 * Description: Data Cache block zero.
806 * Input: r3 = effective address
808 *-------------------------------------------------------------------------- */
815 /*------------------------------------------------------------------------------- */
816 /* Function: ppcSync */
817 /* Description: Processor Synchronize */
820 /*------------------------------------------------------------------------------- */
826 /*------------------------------------------------------------------------------*/
829 * void relocate_code (addr_sp, gd, addr_moni)
831 * This "function" does not return, instead it continues in RAM
832 * after relocating the monitor code.
836 * r5 = length in bytes
841 mr r1,r3 /* Set new stack pointer */
842 mr r9,r4 /* Save copy of Init Data pointer */
843 mr r10,r5 /* Save copy of Destination Address */
845 mr r3,r5 /* Destination Address */
846 lis r4,CFG_MONITOR_BASE@h /* Source Address */
847 ori r4,r4,CFG_MONITOR_BASE@l
848 lwz r5,GOT(__init_end)
850 li r6,CFG_CACHELINE_SIZE /* Cache Line Size */
855 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
861 /* First our own GOT */
863 /* the the one used by the C code */
873 beq cr1,4f /* In place copy is not necessary */
874 beq 7f /* Protect against 0 count */
893 * Now flush the cache: note that we must start from a cache aligned
894 * address. Otherwise we might miss one cache line.
898 beq 7f /* Always flush prefetch queue in any case */
906 sync /* Wait for all dcbst to complete on bus */
912 7: sync /* Wait for all icbi to complete on bus */
916 * Re-point the IVPR at RAM
921 * We are done. Do not return, instead branch to second part of board
922 * initialization, now running from RAM.
925 addi r0,r10,in_ram - _start + _START_OFFSET
927 blr /* NEVER RETURNS! */
932 * Relocation Function, r14 point to got2+0x8000
934 * Adjust got2 pointers, no need to check for 0, this code
935 * already puts a few entries in the table.
937 li r0,__got2_entries@sectoff@l
938 la r3,GOT(_GOT2_TABLE_)
939 lwz r11,GOT(_GOT2_TABLE_)
949 * Now adjust the fixups and the pointers to the fixups
950 * in case we need to move ourselves again.
952 2: li r0,__fixup_entries@sectoff@l
953 lwz r3,GOT(_FIXUP_TABLE_)
967 * Now clear BSS segment
969 lwz r3,GOT(__bss_start)
983 mr r3,r9 /* Init Data pointer */
984 mr r4,r10 /* Destination Address */
988 * Copy exception vector code to low memory
991 * r7: source address, r8: end address, r9: target address
995 lwz r7,GOT(_start_of_vectors)
996 lwz r8,GOT(_end_of_vectors)
998 li r9,0x100 /* reset vector always at 0x100 */
1001 bgelr /* return if r7>=r8 - just in case */
1003 mflr r4 /* save link register */
1013 * relocate `hdlr' and `int_return' entries
1015 li r7,.L_CriticalInput - _start + _START_OFFSET
1017 li r7,.L_MachineCheck - _start + _START_OFFSET
1019 li r7,.L_DataStorage - _start + _START_OFFSET
1021 li r7,.L_InstStorage - _start + _START_OFFSET
1023 li r7,.L_ExtInterrupt - _start + _START_OFFSET
1025 li r7,.L_Alignment - _start + _START_OFFSET
1027 li r7,.L_ProgramCheck - _start + _START_OFFSET
1029 li r7,.L_FPUnavailable - _start + _START_OFFSET
1031 li r7,.L_Decrementer - _start + _START_OFFSET
1033 li r7,.L_IntervalTimer - _start + _START_OFFSET
1034 li r8,_end_of_vectors - _start + _START_OFFSET
1037 addi r7,r7,0x100 /* next exception vector */
1044 mtlr r4 /* restore link register */
1048 * Function: relocate entries for one exception vector
1051 lwz r0,0(r7) /* hdlr ... */
1052 add r0,r0,r3 /* ... += dest_addr */
1055 lwz r0,4(r7) /* int_return ... */
1056 add r0,r0,r3 /* ... += dest_addr */
1061 #ifdef CFG_INIT_RAM_LOCK
1062 .globl unlock_ram_in_cache
1063 unlock_ram_in_cache:
1064 /* invalidate the INIT_RAM section */
1065 lis r3,(CFG_INIT_RAM_ADDR & ~31)@h
1066 ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l
1069 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1073 addi r3,r3,CFG_CACHELINE_SIZE
1075 sync /* Wait for all icbi to complete on bus */