2 * Copyright 2004, 2007-2009 Freescale Semiconductor, Inc.
3 * Copyright (C) 2003 Motorola,Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
26 * The processor starts at 0xfffffffc and the code is first executed in the
27 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
33 #include <timestamp.h>
36 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
38 #include <ppc_asm.tmpl>
41 #include <asm/cache.h>
44 #ifndef CONFIG_IDENT_STRING
45 #define CONFIG_IDENT_STRING ""
49 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
52 * Set up GOT: Global Offset Table
54 * Use r14 to access the GOT
57 GOT_ENTRY(_GOT2_TABLE_)
58 GOT_ENTRY(_FIXUP_TABLE_)
60 #ifndef CONFIG_NAND_SPL
62 GOT_ENTRY(_start_of_vectors)
63 GOT_ENTRY(_end_of_vectors)
64 GOT_ENTRY(transfer_to_handler)
69 GOT_ENTRY(__bss_start)
73 * e500 Startup -- after reset only the last 4KB of the effective
74 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
75 * section is located at THIS LAST page and basically does three
76 * things: clear some registers, set up exception tables and
77 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
78 * continue the boot procedure.
80 * Once the boot rom is mapped by TLB entries we can proceed
81 * with normal startup.
90 /* clear registers/arrays not reset by hardware */
94 mtspr L1CSR0,r0 /* invalidate d-cache */
95 mtspr L1CSR1,r0 /* invalidate i-cache */
98 mtspr DBSR,r1 /* Clear all valid bits */
101 * Enable L1 Caches early
105 #if defined(CONFIG_E500MC) && defined(CONFIG_SYS_CACHE_STASHING)
106 /* set stash id to (coreID) * 2 + 32 + L1 CT (0) */
111 lis r2,L1CSR0_CPE@H /* enable parity */
113 mtspr L1CSR0,r2 /* enable L1 Dcache */
115 mtspr L1CSR1,r2 /* enable L1 Icache */
119 /* Setup interrupt vectors */
124 mtspr IVOR0,r1 /* 0: Critical input */
126 mtspr IVOR1,r1 /* 1: Machine check */
128 mtspr IVOR2,r1 /* 2: Data storage */
130 mtspr IVOR3,r1 /* 3: Instruction storage */
132 mtspr IVOR4,r1 /* 4: External interrupt */
134 mtspr IVOR5,r1 /* 5: Alignment */
136 mtspr IVOR6,r1 /* 6: Program check */
138 mtspr IVOR7,r1 /* 7: floating point unavailable */
140 mtspr IVOR8,r1 /* 8: System call */
141 /* 9: Auxiliary processor unavailable(unsupported) */
143 mtspr IVOR10,r1 /* 10: Decrementer */
145 mtspr IVOR11,r1 /* 11: Interval timer */
147 mtspr IVOR12,r1 /* 12: Watchdog timer */
149 mtspr IVOR13,r1 /* 13: Data TLB error */
151 mtspr IVOR14,r1 /* 14: Instruction TLB error */
153 mtspr IVOR15,r1 /* 15: Debug */
155 /* Clear and set up some registers. */
158 mtspr DEC,r0 /* prevent dec exceptions */
159 mttbl r0 /* prevent fit & wdt exceptions */
161 mtspr TSR,r1 /* clear all timer exception status */
162 mtspr TCR,r0 /* disable all */
163 mtspr ESR,r0 /* clear exception syndrome register */
164 mtspr MCSR,r0 /* machine check syndrome register */
165 mtxer r0 /* clear integer exception register */
167 #ifdef CONFIG_SYS_BOOK3E_HV
168 mtspr MAS8,r0 /* make sure MAS8 is clear */
171 /* Enable Time Base and Select Time Base Clock */
172 lis r0,HID0_EMCP@h /* Enable machine check */
173 #if defined(CONFIG_ENABLE_36BIT_PHYS)
174 ori r0,r0,HID0_ENMAS7@l /* Enable MAS7 */
176 #ifndef CONFIG_E500MC
177 ori r0,r0,HID0_TBEN@l /* Enable Timebase */
181 #ifndef CONFIG_E500MC
182 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
186 /* Enable Branch Prediction */
187 #if defined(CONFIG_BTB)
188 li r0,0x201 /* BBFI = 1, BPEN = 1 */
192 #if defined(CONFIG_SYS_INIT_DBCR)
195 mtspr DBSR,r1 /* Clear all status bits */
196 lis r0,CONFIG_SYS_INIT_DBCR@h /* DBCR0[IDM] must be set */
197 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
201 #ifdef CONFIG_MPC8569
202 #define CONFIG_SYS_LBC_ADDR (CONFIG_SYS_CCSRBAR_DEFAULT + 0x5000)
203 #define CONFIG_SYS_LBCR_ADDR (CONFIG_SYS_LBC_ADDR + 0xd0)
205 /* MPC8569 Rev.0 silcon needs to set bit 13 of LBCR to allow elBC to
206 * use address space which is more than 12bits, and it must be done in
207 * the 4K boot page. So we set this bit here.
210 /* create a temp mapping TLB0[0] for LBCR */
211 lis r6,FSL_BOOKE_MAS0(0, 0, 0)@h
212 ori r6,r6,FSL_BOOKE_MAS0(0, 0, 0)@l
214 lis r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@h
215 ori r7,r7,FSL_BOOKE_MAS1(1, 0, 0, 0, BOOKE_PAGESZ_4K)@l
217 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@h
218 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_LBC_ADDR, MAS2_I|MAS2_G)@l
220 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
221 (MAS3_SX|MAS3_SW|MAS3_SR))@h
222 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_LBC_ADDR, 0,
223 (MAS3_SX|MAS3_SW|MAS3_SR))@l
233 /* Set LBCR register */
234 lis r4,CONFIG_SYS_LBCR_ADDR@h
235 ori r4,r4,CONFIG_SYS_LBCR_ADDR@l
237 lis r5,CONFIG_SYS_LBC_LBCR@h
238 ori r5,r5,CONFIG_SYS_LBC_LBCR@l
242 /* invalidate this temp TLB */
243 lis r4,CONFIG_SYS_LBC_ADDR@h
244 ori r4,r4,CONFIG_SYS_LBC_ADDR@l
248 #endif /* CONFIG_MPC8569 */
250 lis r6,FSL_BOOKE_MAS0(1, 15, 0)@h
251 ori r6,r6,FSL_BOOKE_MAS0(1, 15, 0)@l
253 #ifndef CONFIG_SYS_RAMBOOT
254 /* create a temp mapping in AS=1 to the 4M boot window */
255 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@h
256 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_4M)@l
258 lis r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@h
259 ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE & 0xffc00000, (MAS2_I|MAS2_G))@l
261 /* The 85xx has the default boot window 0xff800000 - 0xffffffff */
262 lis r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
263 ori r9,r9,FSL_BOOKE_MAS3(0xffc00000, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
266 * create a temp mapping in AS=1 to the 1M TEXT_BASE space, the main
267 * image has been relocated to TEXT_BASE on the second stage.
269 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@h
270 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_1M)@l
272 lis r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@h
273 ori r8,r8,FSL_BOOKE_MAS2(TEXT_BASE, (MAS2_I|MAS2_G))@l
275 lis r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
276 ori r9,r9,FSL_BOOKE_MAS3(TEXT_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
287 /* create a temp mapping in AS=1 to the stack */
288 lis r6,FSL_BOOKE_MAS0(1, 14, 0)@h
289 ori r6,r6,FSL_BOOKE_MAS0(1, 14, 0)@l
291 lis r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@h
292 ori r7,r7,FSL_BOOKE_MAS1(1, 1, 0, 1, BOOKE_PAGESZ_16K)@l
294 lis r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@h
295 ori r8,r8,FSL_BOOKE_MAS2(CONFIG_SYS_INIT_RAM_ADDR, 0)@l
297 lis r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@h
298 ori r9,r9,FSL_BOOKE_MAS3(CONFIG_SYS_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))@l
308 lis r6,MSR_IS|MSR_DS@h
309 ori r6,r6,MSR_IS|MSR_DS@l
311 ori r7,r7,switch_as@l
318 /* L1 DCache is used for initial RAM */
320 /* Allocate Initial RAM in data cache.
322 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
323 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
326 /* cache size * 1024 / (2 * L1 line size) */
327 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
333 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
336 /* Jump out the last 4K page and continue to 'normal' start */
337 #ifdef CONFIG_SYS_RAMBOOT
340 /* Calculate absolute address in FLASH and jump there */
341 /*--------------------------------------------------------------*/
342 lis r3,CONFIG_SYS_MONITOR_BASE@h
343 ori r3,r3,CONFIG_SYS_MONITOR_BASE@l
344 addi r3,r3,_start_cont - _start + _START_OFFSET
352 .long 0x27051956 /* U-BOOT Magic Number */
353 .globl version_string
355 .ascii U_BOOT_VERSION
356 .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
357 .ascii CONFIG_IDENT_STRING, "\0"
362 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
363 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
364 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
368 stwu r0,-4(r1) /* Terminate call chain */
370 stwu r1,-8(r1) /* Save back chain and move SP */
371 lis r0,RESET_VECTOR@h /* Address of reset vector */
372 ori r0,r0,RESET_VECTOR@l
373 stwu r1,-8(r1) /* Save back chain and move SP */
374 stw r0,+12(r1) /* Save return addr (underflow vect) */
379 /* switch back to AS = 0 */
380 lis r3,(MSR_CE|MSR_ME|MSR_DE)@h
381 ori r3,r3,(MSR_CE|MSR_ME|MSR_DE)@l
389 #ifndef CONFIG_NAND_SPL
390 . = EXC_OFF_SYS_RESET
391 .globl _start_of_vectors
394 /* Critical input. */
395 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
398 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
400 /* Data Storage exception. */
401 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
403 /* Instruction Storage exception. */
404 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
406 /* External Interrupt exception. */
407 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
409 /* Alignment exception. */
412 EXCEPTION_PROLOG(SRR0, SRR1)
417 addi r3,r1,STACK_FRAME_OVERHEAD
419 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
420 lwz r6,GOT(transfer_to_handler)
424 .long AlignmentException - _start + _START_OFFSET
425 .long int_return - _start + _START_OFFSET
427 /* Program check exception */
430 EXCEPTION_PROLOG(SRR0, SRR1)
431 addi r3,r1,STACK_FRAME_OVERHEAD
433 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
434 lwz r6,GOT(transfer_to_handler)
438 .long ProgramCheckException - _start + _START_OFFSET
439 .long int_return - _start + _START_OFFSET
441 /* No FPU on MPC85xx. This exception is not supposed to happen.
443 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
447 * r0 - SYSCALL number
451 addis r11,r0,0 /* get functions table addr */
452 ori r11,r11,0 /* Note: this code is patched in trap_init */
453 addis r12,r0,0 /* get number of functions */
459 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
463 li r20,0xd00-4 /* Get stack pointer */
465 subi r12,r12,12 /* Adjust stack pointer */
466 li r0,0xc00+_end_back-SystemCall
467 cmplw 0,r0,r12 /* Check stack overflow */
478 li r12,0xc00+_back-SystemCall
486 mfmsr r11 /* Disable interrupts */
490 SYNC /* Some chip revs need this... */
494 li r12,0xd00-4 /* restore regs */
504 addi r12,r12,12 /* Adjust stack pointer */
512 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
513 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
514 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
516 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
517 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
519 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
521 .globl _end_of_vectors
525 . = . + (0x100 - ( . & 0xff )) /* align for debug */
528 * This code finishes saving the registers to the exception frame
529 * and jumps to the appropriate handler for the exception.
530 * Register r21 is pointer into trap frame, r1 has new stack pointer.
532 .globl transfer_to_handler
544 andi. r24,r23,0x3f00 /* get vector offset */
548 mtspr SPRG2,r22 /* r1 is now kernel sp */
550 lwz r24,0(r23) /* virtual address of handler */
551 lwz r23,4(r23) /* where to go when done */
556 rfi /* jump to handler, enable MMU */
559 mfmsr r28 /* Disable interrupts */
563 SYNC /* Some chip revs need this... */
578 lwz r2,_NIP(r1) /* Restore environment */
589 mfmsr r28 /* Disable interrupts */
593 SYNC /* Some chip revs need this... */
608 lwz r2,_NIP(r1) /* Restore environment */
619 mfmsr r28 /* Disable interrupts */
623 SYNC /* Some chip revs need this... */
638 lwz r2,_NIP(r1) /* Restore environment */
650 .globl invalidate_icache
653 ori r0,r0,L1CSR1_ICFI
658 blr /* entire I cache */
660 .globl invalidate_dcache
663 ori r0,r0,L1CSR0_DCFI
683 .globl icache_disable
696 andi. r3,r3,L1CSR1_ICE
714 .globl dcache_disable
727 andi. r3,r3,L1CSR0_DCE
750 /*------------------------------------------------------------------------------- */
752 /* Description: Input 8 bits */
753 /*------------------------------------------------------------------------------- */
759 /*------------------------------------------------------------------------------- */
761 /* Description: Output 8 bits */
762 /*------------------------------------------------------------------------------- */
769 /*------------------------------------------------------------------------------- */
770 /* Function: out16 */
771 /* Description: Output 16 bits */
772 /*------------------------------------------------------------------------------- */
779 /*------------------------------------------------------------------------------- */
780 /* Function: out16r */
781 /* Description: Byte reverse and output 16 bits */
782 /*------------------------------------------------------------------------------- */
789 /*------------------------------------------------------------------------------- */
790 /* Function: out32 */
791 /* Description: Output 32 bits */
792 /*------------------------------------------------------------------------------- */
799 /*------------------------------------------------------------------------------- */
800 /* Function: out32r */
801 /* Description: Byte reverse and output 32 bits */
802 /*------------------------------------------------------------------------------- */
809 /*------------------------------------------------------------------------------- */
811 /* Description: Input 16 bits */
812 /*------------------------------------------------------------------------------- */
818 /*------------------------------------------------------------------------------- */
819 /* Function: in16r */
820 /* Description: Input 16 bits and byte reverse */
821 /*------------------------------------------------------------------------------- */
827 /*------------------------------------------------------------------------------- */
829 /* Description: Input 32 bits */
830 /*------------------------------------------------------------------------------- */
836 /*------------------------------------------------------------------------------- */
837 /* Function: in32r */
838 /* Description: Input 32 bits and byte reverse */
839 /*------------------------------------------------------------------------------- */
844 #endif /* !CONFIG_NAND_SPL */
846 /*------------------------------------------------------------------------------*/
849 * void write_tlb(mas0, mas1, mas2, mas3, mas7)
857 #ifdef CONFIG_ENABLE_36BIT_PHYS
861 #ifdef CONFIG_SYS_BOOK3E_HV
871 * void relocate_code (addr_sp, gd, addr_moni)
873 * This "function" does not return, instead it continues in RAM
874 * after relocating the monitor code.
878 * r5 = length in bytes
883 mr r1,r3 /* Set new stack pointer */
884 mr r9,r4 /* Save copy of Init Data pointer */
885 mr r10,r5 /* Save copy of Destination Address */
887 mr r3,r5 /* Destination Address */
888 lis r4,CONFIG_SYS_MONITOR_BASE@h /* Source Address */
889 ori r4,r4,CONFIG_SYS_MONITOR_BASE@l
890 lwz r5,GOT(__init_end)
892 li r6,CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
897 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
903 /* First our own GOT */
905 /* the the one used by the C code */
915 beq cr1,4f /* In place copy is not necessary */
916 beq 7f /* Protect against 0 count */
935 * Now flush the cache: note that we must start from a cache aligned
936 * address. Otherwise we might miss one cache line.
940 beq 7f /* Always flush prefetch queue in any case */
948 sync /* Wait for all dcbst to complete on bus */
954 7: sync /* Wait for all icbi to complete on bus */
958 * Re-point the IVPR at RAM
963 * We are done. Do not return, instead branch to second part of board
964 * initialization, now running from RAM.
967 addi r0,r10,in_ram - _start + _START_OFFSET
969 blr /* NEVER RETURNS! */
974 * Relocation Function, r14 point to got2+0x8000
976 * Adjust got2 pointers, no need to check for 0, this code
977 * already puts a few entries in the table.
979 li r0,__got2_entries@sectoff@l
980 la r3,GOT(_GOT2_TABLE_)
981 lwz r11,GOT(_GOT2_TABLE_)
993 * Now adjust the fixups and the pointers to the fixups
994 * in case we need to move ourselves again.
996 li r0,__fixup_entries@sectoff@l
997 lwz r3,GOT(_FIXUP_TABLE_)
1011 * Now clear BSS segment
1013 lwz r3,GOT(__bss_start)
1027 mr r3,r9 /* Init Data pointer */
1028 mr r4,r10 /* Destination Address */
1031 #ifndef CONFIG_NAND_SPL
1033 * Copy exception vector code to low memory
1036 * r7: source address, r8: end address, r9: target address
1040 lwz r7,GOT(_start_of_vectors)
1041 lwz r8,GOT(_end_of_vectors)
1043 li r9,0x100 /* reset vector always at 0x100 */
1046 bgelr /* return if r7>=r8 - just in case */
1048 mflr r4 /* save link register */
1058 * relocate `hdlr' and `int_return' entries
1060 li r7,.L_CriticalInput - _start + _START_OFFSET
1062 li r7,.L_MachineCheck - _start + _START_OFFSET
1064 li r7,.L_DataStorage - _start + _START_OFFSET
1066 li r7,.L_InstStorage - _start + _START_OFFSET
1068 li r7,.L_ExtInterrupt - _start + _START_OFFSET
1070 li r7,.L_Alignment - _start + _START_OFFSET
1072 li r7,.L_ProgramCheck - _start + _START_OFFSET
1074 li r7,.L_FPUnavailable - _start + _START_OFFSET
1076 li r7,.L_Decrementer - _start + _START_OFFSET
1078 li r7,.L_IntervalTimer - _start + _START_OFFSET
1079 li r8,_end_of_vectors - _start + _START_OFFSET
1082 addi r7,r7,0x100 /* next exception vector */
1089 mtlr r4 /* restore link register */
1093 * Function: relocate entries for one exception vector
1096 lwz r0,0(r7) /* hdlr ... */
1097 add r0,r0,r3 /* ... += dest_addr */
1100 lwz r0,4(r7) /* int_return ... */
1101 add r0,r0,r3 /* ... += dest_addr */
1106 .globl unlock_ram_in_cache
1107 unlock_ram_in_cache:
1108 /* invalidate the INIT_RAM section */
1109 lis r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@h
1110 ori r3,r3,(CONFIG_SYS_INIT_RAM_ADDR & ~(CONFIG_SYS_CACHELINE_SIZE-1))@l
1113 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1116 addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
1120 /* Invalidate the TLB entries for the cache */
1121 lis r3,CONFIG_SYS_INIT_RAM_ADDR@h
1122 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
1135 mfspr r3,SPRN_L1CFG0
1137 rlwinm r5,r3,9,3 /* Extract cache block size */
1138 twlgti r5,1 /* Only 32 and 64 byte cache blocks
1139 * are currently defined.
1142 subfic r6,r5,2 /* r6 = log2(1KiB / cache block size) -
1143 * log2(number of ways)
1145 slw r5,r4,r5 /* r5 = cache block size */
1147 rlwinm r7,r3,0,0xff /* Extract number of KiB in the cache */
1148 mulli r7,r7,13 /* An 8-way cache will require 13
1153 /* save off HID0 and set DCFA */
1155 ori r9,r8,HID0_DCFA@l
1162 1: lwz r3,0(r4) /* Load... */
1170 1: dcbf 0,r4 /* ...and flush. */
1183 #include "fixed_ivor.S"
1185 #endif /* !CONFIG_NAND_SPL */