2 * Copyright 2004, 2007 Freescale Semiconductor.
3 * Copyright (C) 2003 Motorola,Inc.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 /* U-Boot Startup Code for Motorola 85xx PowerPC based Embedded Boards
26 * The processor starts at 0xfffffffc and the code is first executed in the
27 * last 4K page(0xfffff000-0xffffffff) in flash/rom.
35 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
37 #include <ppc_asm.tmpl>
40 #include <asm/cache.h>
43 #ifndef CONFIG_IDENT_STRING
44 #define CONFIG_IDENT_STRING ""
48 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
51 * Set up GOT: Global Offset Table
53 * Use r14 to access the GOT
56 GOT_ENTRY(_GOT2_TABLE_)
57 GOT_ENTRY(_FIXUP_TABLE_)
60 GOT_ENTRY(_start_of_vectors)
61 GOT_ENTRY(_end_of_vectors)
62 GOT_ENTRY(transfer_to_handler)
66 GOT_ENTRY(__bss_start)
70 * e500 Startup -- after reset only the last 4KB of the effective
71 * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg
72 * section is located at THIS LAST page and basically does three
73 * things: clear some registers, set up exception tables and
74 * add more TLB entries for 'larger spaces'(e.g. the boot rom) to
75 * continue the boot procedure.
77 * Once the boot rom is mapped by TLB entries we can proceed
78 * with normal startup.
87 /* clear registers/arrays not reset by hardware */
91 mtspr L1CSR0,r0 /* invalidate d-cache */
92 mtspr L1CSR1,r0 /* invalidate i-cache */
95 mtspr DBSR,r1 /* Clear all valid bits */
98 * Enable L1 Caches early
102 lis r2,L1CSR0_CPE@H /* enable parity */
104 mtspr L1CSR0,r2 /* enable L1 Dcache */
106 mtspr L1CSR1,r2 /* enable L1 Icache */
110 /* Setup interrupt vectors */
115 mtspr IVOR0,r1 /* 0: Critical input */
117 mtspr IVOR1,r1 /* 1: Machine check */
119 mtspr IVOR2,r1 /* 2: Data storage */
121 mtspr IVOR3,r1 /* 3: Instruction storage */
123 mtspr IVOR4,r1 /* 4: External interrupt */
125 mtspr IVOR5,r1 /* 5: Alignment */
127 mtspr IVOR6,r1 /* 6: Program check */
129 mtspr IVOR7,r1 /* 7: floating point unavailable */
131 mtspr IVOR8,r1 /* 8: System call */
132 /* 9: Auxiliary processor unavailable(unsupported) */
134 mtspr IVOR10,r1 /* 10: Decrementer */
136 mtspr IVOR11,r1 /* 11: Interval timer */
138 mtspr IVOR12,r1 /* 12: Watchdog timer */
140 mtspr IVOR13,r1 /* 13: Data TLB error */
142 mtspr IVOR14,r1 /* 14: Instruction TLB error */
144 mtspr IVOR15,r1 /* 15: Debug */
148 * After reset, CCSRBAR is located at CFG_CCSRBAR_DEFAULT, i.e.
149 * 0xff700000-0xff800000. We need add a TLB1 entry for this 1MB
150 * region before we can access any CCSR registers such as L2
151 * registers, Local Access Registers,etc. We will also re-allocate
152 * CFG_CCSRBAR_DEFAULT to CFG_CCSRBAR immediately after TLB1 setup.
154 * Please refer to board-specif directory for TLB1 entry configuration.
155 * (e.g. board/<yourboard>/init.S)
160 lwzu r4,0(r5) /* how many TLB1 entries we actually use */
178 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
179 /* Special sequence needed to update CCSRBAR itself */
180 lis r4,CFG_CCSRBAR_DEFAULT@h
181 ori r4,r4,CFG_CCSRBAR_DEFAULT@l
184 ori r5,r5,CFG_CCSRBAR@l
195 lwz r5,CFG_CCSRBAR@l(r3)
200 /* set up local access windows, defined at board/<boardname>/init.S */
202 ori r7,r7,CFG_CCSRBAR@l
204 /* Clear and set up some registers. */
209 mtspr DEC,r0 /* prevent dec exceptions */
210 mttbl r0 /* prevent fit & wdt exceptions */
212 mtspr TSR,r1 /* clear all timer exception status */
213 mtspr TCR,r0 /* disable all */
214 mtspr ESR,r0 /* clear exception syndrome register */
215 mtspr MCSR,r0 /* machine check syndrome register */
216 mtxer r0 /* clear integer exception register */
217 lis r1,0x0002 /* set CE bit (Critical Exceptions) */
218 ori r1,r1,0x1200 /* set ME/DE bit */
219 mtmsr r1 /* change MSR */
222 /* Enable Time Base and Select Time Base Clock */
223 lis r0,HID0_EMCP@h /* Enable machine check */
224 #if defined(CONFIG_ENABLE_36BIT_PHYS)
225 ori r0,r0,(HID0_TBEN|HID0_ENMAS7)@l /* Enable Timebase & MAS7 */
227 ori r0,r0,HID0_TBEN@l /* enable Timebase */
231 li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
234 /* Enable Branch Prediction */
235 #if defined(CONFIG_BTB)
236 li r0,0x201 /* BBFI = 1, BPEN = 1 */
240 #if defined(CFG_INIT_DBCR)
243 mtspr DBSR,r1 /* Clear all status bits */
244 lis r0,CFG_INIT_DBCR@h /* DBCR0[IDM] must be set */
245 ori r0,r0,CFG_INIT_DBCR@l
249 /* L1 DCache is used for initial RAM */
251 /* Allocate Initial RAM in data cache.
253 lis r3,CFG_INIT_RAM_ADDR@h
254 ori r3,r3,CFG_INIT_RAM_ADDR@l
257 /* cache size * 1024 / (2 * L1 line size) */
258 slwi r2, r2, (10 - 1 - L1_CACHE_SHIFT)
264 addi r3,r3,CFG_CACHELINE_SIZE
267 /* Jump out the last 4K page and continue to 'normal' start */
271 /* Calculate absolute address in FLASH and jump there */
272 /*--------------------------------------------------------------*/
273 lis r3,CFG_MONITOR_BASE@h
274 ori r3,r3,CFG_MONITOR_BASE@l
275 addi r3,r3,_start_cont - _start + _START_OFFSET
283 .long 0x27051956 /* U-BOOT Magic Number */
284 .globl version_string
286 .ascii U_BOOT_VERSION
287 .ascii " (", __DATE__, " - ", __TIME__, ")"
288 .ascii CONFIG_IDENT_STRING, "\0"
293 /* Setup the stack in initial RAM,could be L2-as-SRAM or L1 dcache*/
294 lis r1,CFG_INIT_RAM_ADDR@h
295 ori r1,r1,CFG_INIT_SP_OFFSET@l
299 stwu r0,-4(r1) /* Terminate call chain */
301 stwu r1,-8(r1) /* Save back chain and move SP */
302 lis r0,RESET_VECTOR@h /* Address of reset vector */
303 ori r0,r0,RESET_VECTOR@l
304 stwu r1,-8(r1) /* Save back chain and move SP */
305 stw r0,+12(r1) /* Save return addr (underflow vect) */
312 . = EXC_OFF_SYS_RESET
313 .globl _start_of_vectors
316 /* Critical input. */
317 CRIT_EXCEPTION(0x0100, CriticalInput, CritcalInputException)
320 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
322 /* Data Storage exception. */
323 STD_EXCEPTION(0x0300, DataStorage, UnknownException)
325 /* Instruction Storage exception. */
326 STD_EXCEPTION(0x0400, InstStorage, UnknownException)
328 /* External Interrupt exception. */
329 STD_EXCEPTION(0x0500, ExtInterrupt, ExtIntException)
331 /* Alignment exception. */
334 EXCEPTION_PROLOG(SRR0, SRR1)
339 addi r3,r1,STACK_FRAME_OVERHEAD
341 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
342 lwz r6,GOT(transfer_to_handler)
346 .long AlignmentException - _start + _START_OFFSET
347 .long int_return - _start + _START_OFFSET
349 /* Program check exception */
352 EXCEPTION_PROLOG(SRR0, SRR1)
353 addi r3,r1,STACK_FRAME_OVERHEAD
355 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
356 lwz r6,GOT(transfer_to_handler)
360 .long ProgramCheckException - _start + _START_OFFSET
361 .long int_return - _start + _START_OFFSET
363 /* No FPU on MPC85xx. This exception is not supposed to happen.
365 STD_EXCEPTION(0x0800, FPUnavailable, UnknownException)
369 * r0 - SYSCALL number
373 addis r11,r0,0 /* get functions table addr */
374 ori r11,r11,0 /* Note: this code is patched in trap_init */
375 addis r12,r0,0 /* get number of functions */
381 rlwinm r0,r0,2,0,31 /* fn_addr = fn_tbl[r0] */
385 li r20,0xd00-4 /* Get stack pointer */
387 subi r12,r12,12 /* Adjust stack pointer */
388 li r0,0xc00+_end_back-SystemCall
389 cmplw 0,r0,r12 /* Check stack overflow */
400 li r12,0xc00+_back-SystemCall
408 mfmsr r11 /* Disable interrupts */
412 SYNC /* Some chip revs need this... */
416 li r12,0xd00-4 /* restore regs */
426 addi r12,r12,12 /* Adjust stack pointer */
434 STD_EXCEPTION(0x0a00, Decrementer, timer_interrupt)
435 STD_EXCEPTION(0x0b00, IntervalTimer, UnknownException)
436 STD_EXCEPTION(0x0c00, WatchdogTimer, UnknownException)
438 STD_EXCEPTION(0x0d00, DataTLBError, UnknownException)
439 STD_EXCEPTION(0x0e00, InstructionTLBError, UnknownException)
441 CRIT_EXCEPTION(0x0f00, DebugBreakpoint, DebugException )
443 .globl _end_of_vectors
447 . = . + (0x100 - ( . & 0xff )) /* align for debug */
450 * This code finishes saving the registers to the exception frame
451 * and jumps to the appropriate handler for the exception.
452 * Register r21 is pointer into trap frame, r1 has new stack pointer.
454 .globl transfer_to_handler
466 andi. r24,r23,0x3f00 /* get vector offset */
470 mtspr SPRG2,r22 /* r1 is now kernel sp */
472 lwz r24,0(r23) /* virtual address of handler */
473 lwz r23,4(r23) /* where to go when done */
478 rfi /* jump to handler, enable MMU */
481 mfmsr r28 /* Disable interrupts */
485 SYNC /* Some chip revs need this... */
500 lwz r2,_NIP(r1) /* Restore environment */
511 mfmsr r28 /* Disable interrupts */
515 SYNC /* Some chip revs need this... */
530 lwz r2,_NIP(r1) /* Restore environment */
541 mfmsr r28 /* Disable interrupts */
545 SYNC /* Some chip revs need this... */
560 lwz r2,_NIP(r1) /* Restore environment */
574 ori r0,r0,L1CSR1_ICFI
579 blr /* entire I cache */
583 ori r0,r0,L1CSR0_DCFI
603 .globl icache_disable
616 andi. r3,r3,L1CSR1_ICE
634 .globl dcache_disable
647 andi. r3,r3,L1CSR0_DCE
670 /*------------------------------------------------------------------------------- */
672 /* Description: Input 8 bits */
673 /*------------------------------------------------------------------------------- */
679 /*------------------------------------------------------------------------------- */
681 /* Description: Output 8 bits */
682 /*------------------------------------------------------------------------------- */
689 /*------------------------------------------------------------------------------- */
690 /* Function: out16 */
691 /* Description: Output 16 bits */
692 /*------------------------------------------------------------------------------- */
699 /*------------------------------------------------------------------------------- */
700 /* Function: out16r */
701 /* Description: Byte reverse and output 16 bits */
702 /*------------------------------------------------------------------------------- */
709 /*------------------------------------------------------------------------------- */
710 /* Function: out32 */
711 /* Description: Output 32 bits */
712 /*------------------------------------------------------------------------------- */
719 /*------------------------------------------------------------------------------- */
720 /* Function: out32r */
721 /* Description: Byte reverse and output 32 bits */
722 /*------------------------------------------------------------------------------- */
729 /*------------------------------------------------------------------------------- */
731 /* Description: Input 16 bits */
732 /*------------------------------------------------------------------------------- */
738 /*------------------------------------------------------------------------------- */
739 /* Function: in16r */
740 /* Description: Input 16 bits and byte reverse */
741 /*------------------------------------------------------------------------------- */
747 /*------------------------------------------------------------------------------- */
749 /* Description: Input 32 bits */
750 /*------------------------------------------------------------------------------- */
756 /*------------------------------------------------------------------------------- */
757 /* Function: in32r */
758 /* Description: Input 32 bits and byte reverse */
759 /*------------------------------------------------------------------------------- */
765 /*------------------------------------------------------------------------------- */
766 /* Function: ppcDcbf */
767 /* Description: Data Cache block flush */
768 /* Input: r3 = effective address */
770 /*------------------------------------------------------------------------------- */
776 /*------------------------------------------------------------------------------- */
777 /* Function: ppcDcbi */
778 /* Description: Data Cache block Invalidate */
779 /* Input: r3 = effective address */
781 /*------------------------------------------------------------------------------- */
787 /*--------------------------------------------------------------------------
789 * Description: Data Cache block zero.
790 * Input: r3 = effective address
792 *-------------------------------------------------------------------------- */
799 /*------------------------------------------------------------------------------- */
800 /* Function: ppcSync */
801 /* Description: Processor Synchronize */
804 /*------------------------------------------------------------------------------- */
810 /*------------------------------------------------------------------------------*/
813 * void relocate_code (addr_sp, gd, addr_moni)
815 * This "function" does not return, instead it continues in RAM
816 * after relocating the monitor code.
820 * r5 = length in bytes
825 mr r1,r3 /* Set new stack pointer */
826 mr r9,r4 /* Save copy of Init Data pointer */
827 mr r10,r5 /* Save copy of Destination Address */
829 mr r3,r5 /* Destination Address */
830 lis r4,CFG_MONITOR_BASE@h /* Source Address */
831 ori r4,r4,CFG_MONITOR_BASE@l
832 lwz r5,GOT(__init_end)
834 li r6,CFG_CACHELINE_SIZE /* Cache Line Size */
839 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
845 /* First our own GOT */
847 /* the the one used by the C code */
857 beq cr1,4f /* In place copy is not necessary */
858 beq 7f /* Protect against 0 count */
877 * Now flush the cache: note that we must start from a cache aligned
878 * address. Otherwise we might miss one cache line.
882 beq 7f /* Always flush prefetch queue in any case */
890 sync /* Wait for all dcbst to complete on bus */
896 7: sync /* Wait for all icbi to complete on bus */
900 * Re-point the IVPR at RAM
905 * We are done. Do not return, instead branch to second part of board
906 * initialization, now running from RAM.
909 addi r0,r10,in_ram - _start + _START_OFFSET
911 blr /* NEVER RETURNS! */
916 * Relocation Function, r14 point to got2+0x8000
918 * Adjust got2 pointers, no need to check for 0, this code
919 * already puts a few entries in the table.
921 li r0,__got2_entries@sectoff@l
922 la r3,GOT(_GOT2_TABLE_)
923 lwz r11,GOT(_GOT2_TABLE_)
933 * Now adjust the fixups and the pointers to the fixups
934 * in case we need to move ourselves again.
936 2: li r0,__fixup_entries@sectoff@l
937 lwz r3,GOT(_FIXUP_TABLE_)
951 * Now clear BSS segment
953 lwz r3,GOT(__bss_start)
967 mr r3,r9 /* Init Data pointer */
968 mr r4,r10 /* Destination Address */
972 * Copy exception vector code to low memory
975 * r7: source address, r8: end address, r9: target address
979 lwz r7,GOT(_start_of_vectors)
980 lwz r8,GOT(_end_of_vectors)
982 li r9,0x100 /* reset vector always at 0x100 */
985 bgelr /* return if r7>=r8 - just in case */
987 mflr r4 /* save link register */
997 * relocate `hdlr' and `int_return' entries
999 li r7,.L_CriticalInput - _start + _START_OFFSET
1001 li r7,.L_MachineCheck - _start + _START_OFFSET
1003 li r7,.L_DataStorage - _start + _START_OFFSET
1005 li r7,.L_InstStorage - _start + _START_OFFSET
1007 li r7,.L_ExtInterrupt - _start + _START_OFFSET
1009 li r7,.L_Alignment - _start + _START_OFFSET
1011 li r7,.L_ProgramCheck - _start + _START_OFFSET
1013 li r7,.L_FPUnavailable - _start + _START_OFFSET
1015 li r7,.L_Decrementer - _start + _START_OFFSET
1017 li r7,.L_IntervalTimer - _start + _START_OFFSET
1018 li r8,_end_of_vectors - _start + _START_OFFSET
1021 addi r7,r7,0x100 /* next exception vector */
1028 mtlr r4 /* restore link register */
1032 * Function: relocate entries for one exception vector
1035 lwz r0,0(r7) /* hdlr ... */
1036 add r0,r0,r3 /* ... += dest_addr */
1039 lwz r0,4(r7) /* int_return ... */
1040 add r0,r0,r3 /* ... += dest_addr */
1045 #ifdef CFG_INIT_RAM_LOCK
1046 .globl unlock_ram_in_cache
1047 unlock_ram_in_cache:
1048 /* invalidate the INIT_RAM section */
1049 lis r3,(CFG_INIT_RAM_ADDR & ~31)@h
1050 ori r3,r3,(CFG_INIT_RAM_ADDR & ~31)@l
1053 slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
1057 addi r3,r3,CFG_CACHELINE_SIZE
1059 sync /* Wait for all icbi to complete on bus */