cpu/mpc85xx/spd_sdram.c

   1 /*
   2  * (C) Copyright 2003 Motorola Inc.
   3  * Xianghua Xiao (X.Xiao@motorola.com)
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/processor.h>
  26 #include <i2c.h>
  27 #include <spd.h>
  28 #include <asm/mmu.h>
  29
  30 #ifdef CONFIG_SPD_EEPROM
  31
  32 #undef DEBUG
  33
  34 #if defined(DEBUG)
  35 #define DEB(x)      x
  36 #else
  37 #define DEB(x)
  38 #endif
  39
  40 #define ns2clk(ns) ((ns) / (2000000000 /get_bus_freq(0) + 1))
  41
  42 long int spd_sdram(void) {
  43         volatile immap_t *immap = (immap_t *)CFG_IMMR;
  44         volatile ccsr_ddr_t *ddr = &immap->im_ddr;
  45         volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
  46         spd_eeprom_t spd;
  47         unsigned int memsize,tmp,tmp1,tmp2;
  48         unsigned char caslat;
  49
  50         i2c_read (SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
  51
  52         if ( spd.nrows > 2 ) {
  53                 printf("DDR:Only two chip selects are supported on ADS.\n");
  54                 return 0;
  55         }
  56
  57         if ( spd.nrow_addr < 12 || spd.nrow_addr > 14 || spd.ncol_addr < 8 || spd.ncol_addr > 11) {
  58                 printf("DDR:Row or Col number unsupported.\n");
  59                 return 0;
  60         }
  61
  62         ddr->cs0_bnds = ((spd.row_dens>>2) - 1);
  63         ddr->cs0_config = ( 1<<31 | (spd.nrow_addr-12)<<8 | (spd.ncol_addr-8) );
  64         DEB(printf("\n"));
  65         DEB(printf("cs0_bnds = 0x%08x\n",ddr->cs0_bnds));
  66         DEB(printf("cs0_config = 0x%08x\n",ddr->cs0_config));
  67         if ( spd.nrows == 2 ) {
  68                 ddr->cs1_bnds = ((spd.row_dens<<14) | ((spd.row_dens>>1) - 1));
  69                 ddr->cs1_config = ( 1<<31 | (spd.nrow_addr-12)<<8 | (spd.ncol_addr-8) );
  70                 DEB(printf("cs1_bnds = 0x%08x\n",ddr->cs1_bnds));
  71                 DEB(printf("cs1_config = 0x%08x\n",ddr->cs1_config));
  72         }
  73
  74         memsize = spd.nrows * (4 * spd.row_dens);
  75         if( spd.mem_type == 0x07 ) {
  76                 printf("DDR module detected, total size:%dMB.\n",memsize);
  77         } else {
  78                 printf("No DDR module found!\n");
  79                 return 0;
  80         }
  81
  82         switch(memsize) {
  83                 case 16:
  84                         tmp = 7;     /* TLB size */
  85                         tmp1 = 1;    /* TLB entry number */
  86                         tmp2 = 23;   /* Local Access Window size */
  87                         break;
  88                 case 32:
  89                         tmp = 7;
  90                         tmp1 = 2;
  91                         tmp2 = 24;
  92                         break;
  93                 case 64:
  94                         tmp = 8;
  95                         tmp1 = 1;
  96                         tmp2 = 25;
  97                         break;
  98                 case 128:
  99                         tmp = 8;
 100                         tmp1 = 2;
 101                         tmp2 = 26;
 102                         break;
 103                 case 256:
 104                         tmp = 9;
 105                         tmp1 = 1;
 106                         tmp2 = 27;
 107                         break;
 108                 case 512:
 109                         tmp = 9;
 110                         tmp1 = 2;
 111                         tmp2 = 28;
 112                         break;
 113                 case 1024:
 114                         tmp = 10;
 115                         tmp1 = 1;
 116                         tmp2 = 29;
 117                         break;
 118                 default:
 119                         printf("DDR:we only added support 16M,32M,64M,128M,256M,512M and 1G DDR I.\n");
 120                         return 0;
 121                         break;
 122         }
 123
 124         /* configure DDR TLB to TLB1 Entry 4,5 */
 125         mtspr(MAS0, TLB1_MAS0(1,4,0));
 126         mtspr(MAS1, TLB1_MAS1(1,1,0,0,tmp));
 127         mtspr(MAS2, TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,0,0,0));
 128         mtspr(MAS3, TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1));
 129         asm volatile("isync;msync;tlbwe;isync");
 130         DEB(printf("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,4,0)));
 131         DEB(printf("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp)));
 132         DEB(printf("DDR:MAS2=0x%08x\n",TLB1_MAS2(((CFG_DDR_SDRAM_BASE>>12) \
 133                 & 0xfffff),0,0,0,0,0,0,0,0)));
 134         DEB(printf("DDR:MAS3=0x%08x\n",TLB1_MAS3(((CFG_DDR_SDRAM_BASE>>12) \
 135                 & 0xfffff),0,0,0,0,0,1,0,1,0,1)));
 136
 137         if(tmp1 == 2) {
 138                 mtspr(MAS0, TLB1_MAS0(1,5,0));
 139                 mtspr(MAS1, TLB1_MAS1(1,1,0,0,tmp));
 140                 mtspr(MAS2, TLB1_MAS2((((CFG_DDR_SDRAM_BASE+(memsize*1024*1024)/2)>>12) \
 141                         & 0xfffff),0,0,0,0,0,0,0,0));
 142                 mtspr(MAS3, TLB1_MAS3((((CFG_DDR_SDRAM_BASE+(memsize*1024*1024)/2)>>12) \
 143                         & 0xfffff),0,0,0,0,0,1,0,1,0,1));
 144                 asm volatile("isync;msync;tlbwe;isync");
 145                 DEB(printf("DDR:MAS0=0x%08x\n",TLB1_MAS0(1,5,0)));
 146                 DEB(printf("DDR:MAS1=0x%08x\n",TLB1_MAS1(1,1,0,0,tmp)));
 147                 DEB(printf("DDR:MAS2=0x%08x\n",TLB1_MAS2((((CFG_DDR_SDRAM_BASE \
 148                         +(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,0,0,0)));
 149                 DEB(printf("DDR:MAS3=0x%08x\n",TLB1_MAS3((((CFG_DDR_SDRAM_BASE \
 150                         +(memsize*1024*1024)/2)>>12) & 0xfffff),0,0,0,0,0,1,0,1,0,1)));
 151         }
 152
 153 #if defined(CONFIG_RAM_AS_FLASH)
 154         ecm->lawbar2 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
 155         ecm->lawar2 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & tmp2));
 156         DEB(printf("DDR:LAWBAR2=0x%08x\n",ecm->lawbar2));
 157         DEB(printf("DDR:LARAR2=0x%08x\n",ecm->lawar2));
 158 #else
 159         ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
 160         ecm->lawar1 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & tmp2));
 161         DEB(printf("DDR:LAWBAR1=0x%08x\n",ecm->lawbar1));
 162         DEB(printf("DDR:LARAR1=0x%08x\n",ecm->lawar1));
 163 #endif
 164
 165         tmp = 20000/(((spd.clk_cycle & 0xF0) >> 4) * 10 + (spd.clk_cycle & 0x0f));
 166         DEB(printf("DDR:Module maximum data rate is: %dMhz\n",tmp));
 167
 168         /* find the largest CAS */
 169         if(spd.cas_lat & 0x40) {
 170                 caslat = 7;
 171         } else if (spd.cas_lat & 0x20) {
 172                 caslat = 6;
 173         } else if (spd.cas_lat & 0x10) {
 174                 caslat = 5;
 175         } else if (spd.cas_lat & 0x08) {
 176                 caslat = 4;
 177         } else if (spd.cas_lat & 0x04) {
 178                 caslat = 3;
 179         } else if (spd.cas_lat & 0x02) {
 180                 caslat = 2;
 181         } else if (spd.cas_lat & 0x01) {
 182                 caslat = 1;
 183         } else {
 184                 printf("DDR:no valid CAS Latency information.\n");
 185                 return 0;
 186         }
 187
 188         tmp1 = get_bus_freq(0)/1000000;
 189         if(tmp1<230 && tmp1>=90 && tmp>=230) {         /* 90~230 range, treated as DDR 200 */
 190                 if(spd.clk_cycle3 == 0xa0) caslat -= 2;
 191                 else if(spd.clk_cycle2 == 0xa0) caslat--;
 192         } else if(tmp1<280 && tmp1>=230 && tmp>=280) { /* 230-280 range, treated as DDR 266 */
 193                 if(spd.clk_cycle3 == 0x75) caslat -= 2;
 194                 else if(spd.clk_cycle2 == 0x75) caslat--;
 195         } else if(tmp1<350 && tmp1>=280 && tmp>=350) { /* 280~350 range, treated as DDR 333 */
 196                 if(spd.clk_cycle3 == 0x60) caslat -= 2;
 197                 else if(spd.clk_cycle2 == 0x60) caslat--;
 198         } else if(tmp1<90 || tmp1 >=350) { /* DDR rate out-of-range */
 199                 printf("DDR:platform frequency is not fit for DDR rate\n");
 200                 return 0;
 201         }
 202
 203         /* note: caslat must also be programmed into ddr->sdram_mode register */
 204         /* note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,use conservative value here */
 205 #if 1
 206         ddr->timing_cfg_1 =     (((ns2clk(spd.trp/4) & 0x07) << 28 ) | \
 207                                 ((ns2clk(spd.tras) & 0x0f ) << 24 ) | \
 208                                 ((ns2clk(spd.trcd/4) & 0x07) << 20 ) | \
 209                                 ((caslat & 0x07)<< 16 ) | \
 210                                 (((ns2clk(spd.sset[6]) - 8) & 0x0f) << 12 ) | \
 211                                 ( 0x300 ) | \
 212                                 ((ns2clk(spd.trrd/4) & 0x07) << 4) | 1);
 213 #else
 214         ddr->timing_cfg_1 = 0x37344321;
 215         caslat = 4;
 216 #endif
 217         DEB(printf("DDR:timing_cfg_1=0x%08x\n",ddr->timing_cfg_1));
 218
 219         /* note: hand-coded value for timing_cfg_2, see Errata DDR1*/
 220 #if defined(CONFIG_MPC85xx_REV1)
 221         ddr->timing_cfg_2 = 0x00000800;
 222 #endif
 223         DEB(printf("DDR:timing_cfg_2=0x%08x\n",ddr->timing_cfg_2));
 224
 225         /* only DDR I is supported, DDR I and II have different mode-register-set definition */
 226         /* burst length is always 4 */
 227         switch(caslat) {
 228                 case 2:
 229                         ddr->sdram_mode = 0x52; /* 1.5 */
 230                         break;
 231                 case 3:
 232                         ddr->sdram_mode = 0x22; /* 2.0 */
 233                         break;
 234                 case 4:
 235                         ddr->sdram_mode = 0x62; /* 2.5 */
 236                         break;
 237                 case 5:
 238                         ddr->sdram_mode = 0x32; /* 3.0 */
 239                         break;
 240                 default:
 241                         printf("DDR:only CAS Latency 1.5,2.0,2.5,3.0 is supported.\n");
 242                         return 0;
 243         }
 244         DEB(printf("DDR:sdram_mode=0x%08x\n",ddr->sdram_mode));
 245
 246         switch(spd.refresh) {
 247                 case 0x00:
 248                 case 0x80:
 249                         tmp = ns2clk(15625);
 250                         break;
 251                 case 0x01:
 252                 case 0x81:
 253                         tmp = ns2clk(3900);
 254                         break;
 255                 case 0x02:
 256                 case 0x82:
 257                         tmp = ns2clk(7800);
 258                         break;
 259                 case 0x03:
 260                 case 0x83:
 261                         tmp = ns2clk(31300);
 262                         break;
 263                 case 0x04:
 264                 case 0x84:
 265                         tmp = ns2clk(62500);
 266                         break;
 267                 case 0x05:
 268                 case 0x85:
 269                         tmp = ns2clk(125000);
 270                         break;
 271                 default:
 272                         tmp = 0x512;
 273                         break;
 274         }
 275
 276         /* set BSTOPRE to 0x100 for page mode, if auto-charge is used, set BSTOPRE = 0 */
 277         ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
 278         DEB(printf("DDR:sdram_interval=0x%08x\n",ddr->sdram_interval));
 279
 280         /* is this an ECC DDR chip? */
 281 #if defined(CONFIG_DDR_ECC)
 282         if(spd.config == 0x02) {
 283                 ddr->err_disable = 0x0000000d;
 284                 ddr->err_sbe = 0x00ff0000;
 285         }
 286         DEB(printf("DDR:err_disable=0x%08x\n",ddr->err_disable));
 287         DEB(printf("DDR:err_sbe=0x%08x\n",ddr->err_sbe));
 288 #endif
 289         asm("sync;isync;msync");
 290
 291         udelay(500);
 292
 293         /* registered or unbuffered? */
 294 #if defined(CONFIG_DDR_ECC)
 295         ddr->sdram_cfg = (spd.config == 0x02)?0x20000000:0x0;
 296 #endif
 297         ddr->sdram_cfg = 0xc2000000|((spd.mod_attr == 0x20) ? 0x0 : \
 298                 ((spd.mod_attr == 0x26) ? 0x10000000:0x0));
 299         asm("sync;isync;msync");
 300
 301         udelay(500);
 302
 303         DEB(printf("DDR:sdram_cfg=0x%08x\n",ddr->sdram_cfg));
 304
 305         return (memsize*1024*1024);
 306 }
 307
 308 #endif /* CONFIG_SPD_EEPROM */