2 * Copyright 2008-2009 Freescale Semiconductor, Inc.
3 * Kumar Gala <kumar.gala@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
30 #include <ppc_asm.tmpl>
33 #include <asm/cache.h>
36 /* To boot secondary cpus, we need a place for them to start up.
37 * Normally, they start at 0xfffffffc, but that's usually the
38 * firmware, and we don't want to have to run the firmware again.
39 * Instead, the primary cpu will set the BPTR to point here to
40 * this page. We then set up the core, and head to
41 * start_secondary. Note that this means that the code below
42 * must never exceed 1023 instructions (the branch at the end
43 * would then be the 1024th).
45 .globl __secondary_start_page
47 __secondary_start_page:
48 /* First do some preliminary setup */
49 lis r3, HID0_EMCP@h /* enable machine check */
51 ori r3,r3,HID0_TBEN@l /* enable Timebase */
53 #ifdef CONFIG_PHYS_64BIT
54 ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */
59 li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
63 /* Enable branch prediction */
72 /* Enable/invalidate the I-Cache */
74 ori r0,r0,(L1CSR1_ICFI|L1CSR1_ICE)
78 /* Enable/invalidate the D-Cache */
80 ori r0,r0,(L1CSR0_DCFI|L1CSR0_DCE)
86 #define toreset(x) (x - __secondary_start_page + 0xfffff000)
88 /* get our PIR to figure out our table entry */
89 lis r3,toreset(__spin_table)@h
90 ori r3,r3,toreset(__spin_table)@l
92 /* r10 has the base address for the entry */
102 #ifdef CONFIG_BACKSIDE_L2_CACHE
103 /* Enable/invalidate the L2 cache */
105 lis r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@h
106 ori r3,r3,(L2CSR0_L2FI|L2CSR0_L2LFC)@l
110 andis. r1,r3,L2CSR0_L2FI@h
113 lis r3,CONFIG_SYS_INIT_L2CSR0@h
114 ori r3,r3,CONFIG_SYS_INIT_L2CSR0@l
119 #define EPAPR_MAGIC (0x45504150)
120 #define ENTRY_ADDR_UPPER 0
121 #define ENTRY_ADDR_LOWER 4
122 #define ENTRY_R3_UPPER 8
123 #define ENTRY_R3_LOWER 12
124 #define ENTRY_RESV 16
126 #define ENTRY_R6_UPPER 24
127 #define ENTRY_R6_LOWER 28
128 #define ENTRY_SIZE 32
130 /* setup the entry */
133 stw r0,ENTRY_PIR(r10)
134 stw r3,ENTRY_ADDR_UPPER(r10)
135 stw r8,ENTRY_ADDR_LOWER(r10)
136 stw r3,ENTRY_R3_UPPER(r10)
137 stw r4,ENTRY_R3_LOWER(r10)
138 stw r3,ENTRY_R6_UPPER(r10)
139 stw r3,ENTRY_R6_LOWER(r10)
141 /* load r13 with the address of the 'bootpg' in SDRAM */
142 lis r13,toreset(__bootpg_addr)@h
143 ori r13,r13,toreset(__bootpg_addr)@l
146 /* setup mapping for AS = 1, and jump there */
147 lis r11,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h
149 lis r11,(MAS1_VALID|MAS1_IPROT)@h
150 ori r11,r11,(MAS1_TS|MAS1_TSIZE(BOOKE_PAGESZ_4K))@l
152 oris r11,r13,(MAS2_I)@h
153 ori r11,r13,(MAS2_I)@l
155 oris r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@h
156 ori r11,r13,(MAS3_SX|MAS3_SW|MAS3_SR)@l
163 * OR in 0xfff to create a mask of the bootpg SDRAM address. We use
164 * this mask to fixup the cpu spin table and the address that we want
165 * to jump to, eg change them from 0xfffffxxx to 0x7ffffxxx if the
166 * bootpg is at 0x7ffff000 in SDRAM.
174 ori r12,r13,MSR_IS|MSR_DS@l
180 /* spin waiting for addr */
182 lwz r4,ENTRY_ADDR_LOWER(r10)
187 /* setup IVORs to match fixed offsets */
188 #include "fixed_ivor.S"
190 /* get the upper bits of the addr */
191 lwz r11,ENTRY_ADDR_UPPER(r10)
193 /* setup branch addr */
196 /* mark the entry as released */
198 stw r8,ENTRY_ADDR_LOWER(r10)
200 /* mask by ~64M to setup our tlb we will jump to */
203 /* setup r3, r4, r5, r6, r7, r8, r9 */
204 lwz r3,ENTRY_R3_LOWER(r10)
207 lwz r6,ENTRY_R6_LOWER(r10)
208 lis r7,(64*1024*1024)@h
212 /* load up the pir */
213 lwz r0,ENTRY_PIR(r10)
216 stw r0,ENTRY_PIR(r10)
220 * Coming here, we know the cpu has one TLB mapping in TLB1[0]
221 * which maps 0xfffff000-0xffffffff one-to-one. We set up a
222 * second mapping that maps addr 1:1 for 64M, and then we jump to
225 lis r10,(MAS0_TLBSEL(1)|MAS0_ESEL(0))@h
227 lis r10,(MAS1_VALID|MAS1_IPROT)@h
228 ori r10,r10,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l
230 /* WIMGE = 0b00000 for now */
232 ori r12,r12,(MAS3_SX|MAS3_SW|MAS3_SR)
234 #ifdef CONFIG_ENABLE_36BIT_PHYS
239 /* Now we have another mapping for this page, so we jump to that
246 * Allocate some space for the SDRAM address of the bootpg.
247 * This variable has to be in the boot page so that it can
248 * be accessed by secondary cores when they come out of reset.
254 .align L1_CACHE_SHIFT
257 .space CONFIG_MAX_CPUS*ENTRY_SIZE
259 /* Fill in the empty space. The actual reset vector is
260 * the last word of the page */
261 __secondary_start_code_end:
262 .space 4092 - (__secondary_start_code_end - __secondary_start_page)
263 __secondary_reset_vector:
264 b __secondary_start_page