cpu/mpc85xx/pci.c

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * Copyright (C) 2003 Motorola Inc.
   4  * Xianghua Xiao (x.xiao@motorola.com)
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * PCI Configuration space access support for MPC85xx PCI Bridge
  27  */
  28 #include <common.h>
  29 #include <asm/cpm_85xx.h>
  30 #include <pci.h>
  31
  32 #if defined(CONFIG_PCI) && !defined(CONFIG_FSL_PCI_INIT)
  33
  34 #ifndef CONFIG_SYS_PCI1_MEM_BUS
  35 #define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE
  36 #endif
  37
  38 #ifndef CONFIG_SYS_PCI2_MEM_BUS
  39 #define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI2_MEM_BASE
  40 #endif
  41
  42 static struct pci_controller *pci_hose;
  43
  44 void
  45 pci_mpc85xx_init(struct pci_controller *board_hose)
  46 {
  47         u16 reg16;
  48         u32 dev;
  49
  50         volatile ccsr_pcix_t *pcix = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
  51 #ifdef CONFIG_MPC85XX_PCI2
  52         volatile ccsr_pcix_t *pcix2 = (void *)(CONFIG_SYS_MPC85xx_PCIX2_ADDR);
  53 #endif
  54         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  55         struct pci_controller * hose;
  56
  57         pci_hose = board_hose;
  58
  59         hose = &pci_hose[0];
  60
  61         hose->first_busno = 0;
  62         hose->last_busno = 0xff;
  63
  64         pci_setup_indirect(hose,
  65                            (CONFIG_SYS_IMMR+0x8000),
  66                            (CONFIG_SYS_IMMR+0x8004));
  67
  68         /*
  69          * Hose scan.
  70          */
  71         dev = PCI_BDF(hose->first_busno, 0, 0);
  72         pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
  73         reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  74         pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
  75
  76         /*
  77          * Clear non-reserved bits in status register.
  78          */
  79         pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
  80
  81         if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
  82                 /* PCI-X init */
  83                 if (CONFIG_SYS_CLK_FREQ < 66000000)
  84                         printf("PCI-X will only work at 66 MHz\n");
  85
  86                 reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
  87                         | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
  88                 pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
  89         }
  90
  91         pcix->potar1   = (CONFIG_SYS_PCI1_MEM_BUS >> 12) & 0x000fffff;
  92         pcix->potear1  = 0x00000000;
  93         pcix->powbar1  = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff;
  94         pcix->powbear1 = 0x00000000;
  95         pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
  96                         POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1));
  97
  98         pcix->potar2  = (CONFIG_SYS_PCI1_IO_BASE >> 12) & 0x000fffff;
  99         pcix->potear2  = 0x00000000;
 100         pcix->powbar2  = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff;
 101         pcix->powbear2 = 0x00000000;
 102         pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
 103                         POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI1_IO_SIZE) - 1));
 104
 105         pcix->pitar1 = 0x00000000;
 106         pcix->piwbar1 = 0x00000000;
 107         pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
 108                         PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
 109
 110         pcix->powar3 = 0;
 111         pcix->powar4 = 0;
 112         pcix->piwar2 = 0;
 113         pcix->piwar3 = 0;
 114
 115         pci_set_region(hose->regions + 0,
 116                        CONFIG_SYS_PCI1_MEM_BUS,
 117                        CONFIG_SYS_PCI1_MEM_PHYS,
 118                        CONFIG_SYS_PCI1_MEM_SIZE,
 119                        PCI_REGION_MEM);
 120
 121         pci_set_region(hose->regions + 1,
 122                        CONFIG_SYS_PCI1_IO_BASE,
 123                        CONFIG_SYS_PCI1_IO_PHYS,
 124                        CONFIG_SYS_PCI1_IO_SIZE,
 125                        PCI_REGION_IO);
 126
 127         hose->region_count = 2;
 128
 129         pci_register_hose(hose);
 130
 131 #if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
 132         /*
 133          * This is a SW workaround for an apparent HW problem
 134          * in the PCI controller on the MPC85555/41 CDS boards.
 135          * The first config cycle must be to a valid, known
 136          * device on the PCI bus in order to trick the PCI
 137          * controller state machine into a known valid state.
 138          * Without this, the first config cycle has the chance
 139          * of hanging the controller permanently, just leaving
 140          * it in a semi-working state, or leaving it working.
 141          *
 142          * Pick on the Tundra, Device 17, to get it right.
 143          */
 144         {
 145                 u8 header_type;
 146
 147                 pci_hose_read_config_byte(hose,
 148                                           PCI_BDF(0,BRIDGE_ID,0),
 149                                           PCI_HEADER_TYPE,
 150                                           &header_type);
 151         }
 152 #endif
 153
 154         hose->last_busno = pci_hose_scan(hose);
 155
 156 #ifdef CONFIG_MPC85XX_PCI2
 157         hose = &pci_hose[1];
 158
 159         hose->first_busno = pci_hose[0].last_busno + 1;
 160         hose->last_busno = 0xff;
 161
 162         pci_setup_indirect(hose,
 163                            (CONFIG_SYS_IMMR+0x9000),
 164                            (CONFIG_SYS_IMMR+0x9004));
 165
 166         dev = PCI_BDF(hose->first_busno, 0, 0);
 167         pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
 168         reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 169         pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
 170
 171         /*
 172          * Clear non-reserved bits in status register.
 173          */
 174         pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
 175
 176         pcix2->potar1   = (CONFIG_SYS_PCI2_MEM_BUS >> 12) & 0x000fffff;
 177         pcix2->potear1  = 0x00000000;
 178         pcix2->powbar1  = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff;
 179         pcix2->powbear1 = 0x00000000;
 180         pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
 181                         POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1));
 182
 183         pcix2->potar2  = (CONFIG_SYS_PCI2_IO_BASE >> 12) & 0x000fffff;
 184         pcix2->potear2  = 0x00000000;
 185         pcix2->powbar2  = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff;
 186         pcix2->powbear2 = 0x00000000;
 187         pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
 188                         POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI2_IO_SIZE) - 1));
 189
 190         pcix2->pitar1 = 0x00000000;
 191         pcix2->piwbar1 = 0x00000000;
 192         pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
 193                         PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
 194
 195         pcix2->powar3 = 0;
 196         pcix2->powar4 = 0;
 197         pcix2->piwar2 = 0;
 198         pcix2->piwar3 = 0;
 199
 200         pci_set_region(hose->regions + 0,
 201                        CONFIG_SYS_PCI2_MEM_BUS,
 202                        CONFIG_SYS_PCI2_MEM_PHYS,
 203                        CONFIG_SYS_PCI2_MEM_SIZE,
 204                        PCI_REGION_MEM);
 205
 206         pci_set_region(hose->regions + 1,
 207                        CONFIG_SYS_PCI2_IO_BASE,
 208                        CONFIG_SYS_PCI2_IO_PHYS,
 209                        CONFIG_SYS_PCI2_IO_SIZE,
 210                        PCI_REGION_IO);
 211
 212         hose->region_count = 2;
 213
 214         /*
 215          * Hose scan.
 216          */
 217         pci_register_hose(hose);
 218
 219         hose->last_busno = pci_hose_scan(hose);
 220 #endif
 221 }
 222 #endif /* CONFIG_PCI */