2 * Copyright 2004 Freescale Semiconductor.
3 * Copyright (C) 2003 Motorola Inc.
4 * Xianghua Xiao (x.xiao@motorola.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * PCI Configuration space access support for MPC85xx PCI Bridge
29 #include <asm/cpm_85xx.h>
33 #if defined(CONFIG_PCI)
37 * Initialize PCI Devices, report devices found.
40 #ifndef CONFIG_PCI_PNP
41 static struct pci_config_table pci_mpc85xxads_config_table[] = {
42 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
43 PCI_IDSEL_NUMBER, PCI_ANY_ID,
44 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
52 struct pci_controller local_hose = {
53 #ifndef CONFIG_PCI_PNP
54 config_table: pci_mpc85xxads_config_table,
59 void pci_init_board (void)
61 struct pci_controller *hose = (struct pci_controller *) &local_hose;
62 volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
63 volatile ccsr_pcix_t *pcix = &immap->im_pcix;
67 hose->first_busno = 0;
68 hose->last_busno = 0xff;
70 pci_set_region (hose->regions + 0,
72 CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
74 pci_set_region (hose->regions + 1,
76 CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
78 hose->region_count = 2;
80 pci_setup_indirect (hose, (CFG_IMMR + 0x8000), (CFG_IMMR + 0x8004));
82 pci_read_config_word (PCI_BDF (0, 0, 0), PCI_COMMAND, ®16);
83 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
84 pci_write_config_word (PCI_BDF (0, 0, 0), PCI_COMMAND, reg16);
87 * Clear non-reserved bits in status register.
89 pci_write_config_word (PCI_BDF (0, 0, 0), PCI_STATUS, 0xffff);
90 pci_write_config_byte (PCI_BDF (0, 0, 0), PCI_LATENCY_TIMER, 0x80);
92 pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
93 pcix->potear1 = 0x00000000;
94 pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
95 pcix->powbear1 = 0x00000000;
96 pcix->powar1 = 0x8004401c; /* 512M MEM space */
98 pcix->potar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
99 pcix->potear2 = 0x00000000;
100 pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
101 pcix->powbear2 = 0x00000000;
102 pcix->powar2 = 0x80088017; /* 16M IO space */
104 pcix->pitar1 = 0x00000000;
105 pcix->piwbar1 = 0x00000000;
106 pcix->piwar1 = 0xa0F5501f;
111 pci_register_hose (hose);
112 hose->last_busno = pci_hose_scan (hose);
115 #endif /* CONFIG_PCI */