2 * Copyright 2004 Freescale Semiconductor.
3 * Copyright (C) 2003 Motorola Inc.
4 * Xianghua Xiao (x.xiao@motorola.com)
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * PCI Configuration space access support for MPC85xx PCI Bridge
29 #include <asm/cpm_85xx.h>
33 #if defined(CONFIG_PCI)
36 pci_mpc85xx_init(struct pci_controller *hose)
38 volatile immap_t *immap = (immap_t *)CFG_CCSRBAR;
39 volatile ccsr_pcix_t *pcix = &immap->im_pcix;
43 hose->first_busno = 0;
44 hose->last_busno = 0xff;
46 pci_set_region(hose->regions + 0,
52 pci_set_region(hose->regions + 1,
58 hose->region_count = 2;
60 pci_setup_indirect(hose,
64 pci_read_config_word (PCI_BDF(0,0,0), PCI_COMMAND, ®16);
65 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
66 pci_write_config_word(PCI_BDF(0,0,0), PCI_COMMAND, reg16);
69 * Clear non-reserved bits in status register.
71 pci_write_config_word(PCI_BDF(0,0,0), PCI_STATUS, 0xffff);
72 pci_write_config_byte(PCI_BDF(0,0,0), PCI_LATENCY_TIMER,0x80);
74 pcix->potar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
75 pcix->potear1 = 0x00000000;
76 pcix->powbar1 = (CFG_PCI1_MEM_BASE >> 12) & 0x000fffff;
77 pcix->powbear1 = 0x00000000;
78 pcix->powar1 = 0x8004401c; /* 512M MEM space */
80 pcix->potar2 = 0x00000000;
81 pcix->potear2 = 0x00000000;
82 pcix->powbar2 = (CFG_PCI1_IO_BASE >> 12) & 0x000fffff;
83 pcix->powbear2 = 0x00000000;
84 pcix->powar2 = 0x80088017; /* 16M IO space */
86 pcix->pitar1 = 0x00000000;
87 pcix->piwbar1 = 0x00000000;
88 pcix->piwar1 = 0xa0f5501e; /* Enable, Prefetch, Local Mem,
94 pci_register_hose(hose);
96 #if defined(CONFIG_MPC8555CDS) || defined(CONFIG_MPC8541CDS)
98 * This is a SW workaround for an apparent HW problem
99 * in the PCI controller on the MPC85555/41 CDS boards.
100 * The first config cycle must be to a valid, known
101 * device on the PCI bus in order to trick the PCI
102 * controller state machine into a known valid state.
103 * Without this, the first config cycle has the chance
104 * of hanging the controller permanently, just leaving
105 * it in a semi-working state, or leaving it working.
107 * Pick on the Tundra, Device 17, to get it right.
112 pci_hose_read_config_byte(hose,
119 hose->last_busno = pci_hose_scan(hose);
122 #endif /* CONFIG_PCI */