2 * Copyright 2008-2009 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #include <asm/processor.h>
29 #include <asm/fsl_law.h>
32 DECLARE_GLOBAL_DATA_PTR;
36 return mfspr(SPRN_PIR);
41 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
42 out_be32(&pic->pir, 1 << nr);
43 /* the dummy read works around an errata on early 85xx MP PICs */
44 (void)in_be32(&pic->pir);
45 out_be32(&pic->pir, 0x0);
50 int cpu_status(int nr)
52 u32 *table, id = get_my_id();
55 table = (u32 *)get_spin_addr();
56 printf("table base @ 0x%p\n", table);
58 table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY;
59 printf("Running on cpu %d\n", id);
61 printf("table @ 0x%p\n", table);
62 printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR_LOWER]);
63 printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]);
64 printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]);
65 printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6_LOWER]);
71 static u8 boot_entry_map[4] = {
78 int cpu_release(int nr, int argc, char *argv[])
80 u32 i, val, *table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY;
83 if (nr == get_my_id()) {
84 printf("Invalid to release the boot core.\n\n");
89 printf("Invalid number of arguments to release.\n\n");
93 #ifdef CONFIG_SYS_64BIT_STRTOUL
94 boot_addr = simple_strtoull(argv[0], NULL, 16);
96 boot_addr = simple_strtoul(argv[0], NULL, 16);
99 /* handle pir, r3, r6 */
100 for (i = 1; i < 4; i++) {
101 if (argv[i][0] != '-') {
102 u8 entry = boot_entry_map[i];
103 val = simple_strtoul(argv[i], NULL, 16);
108 table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32);
110 /* ensure all table updates complete before final address write */
113 table[BOOT_ENTRY_ADDR_LOWER] = (u32)(boot_addr & 0xffffffff);
118 u32 determine_mp_bootpg(void)
120 /* if we have 4G or more of memory, put the boot page at 4Gb-4k */
121 if ((u64)gd->ram_size > 0xfffff000)
124 return (gd->ram_size - 4096);
127 ulong get_spin_addr(void)
129 extern ulong __secondary_start_page;
130 extern ulong __spin_table;
133 (ulong)&__spin_table - (ulong)&__secondary_start_page;
139 #ifdef CONFIG_FSL_CORENET
140 static void plat_mp_up(unsigned long bootpg)
142 u32 up, cpu_up_mask, whoami;
143 u32 *table = (u32 *)get_spin_addr();
144 volatile ccsr_gur_t *gur;
145 volatile ccsr_local_t *ccm;
146 volatile ccsr_rcpm_t *rcpm;
147 volatile ccsr_pic_t *pic;
152 gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
153 ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
154 rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
155 pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
157 nr_cpus = ((in_be32(&pic->frr) >> 8) & 0xff) + 1;
159 whoami = in_be32(&pic->whoami);
160 cpu_up_mask = 1 << whoami;
161 out_be32(&ccm->bstrl, bootpg);
163 e = find_law(bootpg);
164 out_be32(&ccm->bstrar, LAW_EN | e.trgt_id << 20 | LAW_SIZE_4K);
166 /* disable time base at the platform */
167 out_be32(&rcpm->ctbenrl, cpu_up_mask);
169 /* release the hounds */
170 up = ((1 << nr_cpus) - 1);
171 out_be32(&gur->brrl, up);
173 /* wait for everyone */
176 for (i = 0; i < nr_cpus; i++) {
177 if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
178 cpu_up_mask |= (1 << i);
181 if ((cpu_up_mask & up) == up)
189 printf("CPU up timeout. CPU up mask is %x should be %x\n",
192 /* enable time base at the platform */
193 out_be32(&rcpm->ctbenrl, 0);
196 out_be32(&rcpm->ctbenrl, (1 << nr_cpus) - 1);
199 static void plat_mp_up(unsigned long bootpg)
201 u32 up, cpu_up_mask, whoami;
202 u32 *table = (u32 *)get_spin_addr();
204 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
205 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
206 volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC85xx_PIC_ADDR);
210 whoami = in_be32(&pic->whoami);
211 out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12));
213 /* disable time base at the platform */
214 devdisr = in_be32(&gur->devdisr);
216 devdisr |= MPC85xx_DEVDISR_TB0;
218 devdisr |= MPC85xx_DEVDISR_TB1;
219 out_be32(&gur->devdisr, devdisr);
221 /* release the hounds */
222 up = ((1 << cpu_numcores()) - 1);
223 bpcr = in_be32(&ecm->eebpcr);
225 out_be32(&ecm->eebpcr, bpcr);
226 asm("sync; isync; msync");
228 cpu_up_mask = 1 << whoami;
229 /* wait for everyone */
232 for (i = 0; i < cpu_numcores(); i++) {
233 if (table[i * NUM_BOOT_ENTRY + BOOT_ENTRY_ADDR_LOWER])
234 cpu_up_mask |= (1 << i);
237 if ((cpu_up_mask & up) == up)
245 printf("CPU up timeout. CPU up mask is %x should be %x\n",
248 /* enable time base at the platform */
250 devdisr |= MPC85xx_DEVDISR_TB1;
252 devdisr |= MPC85xx_DEVDISR_TB0;
253 out_be32(&gur->devdisr, devdisr);
257 devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1);
258 out_be32(&gur->devdisr, devdisr);
262 void cpu_mp_lmb_reserve(struct lmb *lmb)
264 u32 bootpg = determine_mp_bootpg();
266 lmb_reserve(lmb, bootpg, 4096);
271 extern ulong __secondary_start_page;
272 ulong fixup = (ulong)&__secondary_start_page;
273 u32 bootpg = determine_mp_bootpg();
275 /* look for the tlb covering the reset page, there better be one */
276 int i = find_tlb_idx((void *)0xfffff000, 1);
278 /* we found a match */
280 /* map reset page to bootpg so we can copy code there */
283 set_tlb(1, 0xfffff000, bootpg, /* tlb, epn, rpn */
284 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, /* perms, wimge */
285 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
287 memcpy((void *)0xfffff000, (void *)fixup, 4096);
288 flush_cache(0xfffff000, 4096);
292 /* setup reset page back to 1:1, we'll use HW boot translation
293 * to map this where we want
295 set_tlb(1, 0xfffff000, 0xfffff000, /* tlb, epn, rpn */
296 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I, /* perms, wimge */
297 0, i, BOOKE_PAGESZ_4K, 1); /* ts, esel, tsize, iprot */
301 puts("WARNING: No reset page TLB. "
302 "Skipping secondary core setup\n");