cpu/mpc85xx/fdt.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2000
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #include <common.h>
  27 #include <libfdt.h>
  28 #include <fdt_support.h>
  29 #include <asm/processor.h>
  30 #ifdef CONFIG_FSL_ESDHC
  31 #include <fsl_esdhc.h>
  32 #endif
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 extern void ft_qe_setup(void *blob);
  37
  38 #ifdef CONFIG_MP
  39 #include "mp.h"
  40
  41 void ft_fixup_cpu(void *blob, u64 memory_limit)
  42 {
  43         int off;
  44         ulong spin_tbl_addr = get_spin_addr();
  45         u32 bootpg = determine_mp_bootpg();
  46         u32 id = get_my_id();
  47
  48         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  49         while (off != -FDT_ERR_NOTFOUND) {
  50                 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
  51
  52                 if (reg) {
  53                         if (*reg == id) {
  54                                 fdt_setprop_string(blob, off, "status", "okay");
  55                         } else {
  56                                 u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
  57                                 val = cpu_to_fdt32(val);
  58                                 fdt_setprop_string(blob, off, "status",
  59                                                                 "disabled");
  60                                 fdt_setprop_string(blob, off, "enable-method",
  61                                                                 "spin-table");
  62                                 fdt_setprop(blob, off, "cpu-release-addr",
  63                                                 &val, sizeof(val));
  64                         }
  65                 } else {
  66                         printf ("cpu NULL\n");
  67                 }
  68                 off = fdt_node_offset_by_prop_value(blob, off,
  69                                 "device_type", "cpu", 4);
  70         }
  71
  72         /* Reserve the boot page so OSes dont use it */
  73         if ((u64)bootpg < memory_limit) {
  74                 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
  75                 if (off < 0)
  76                         printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
  77         }
  78 }
  79 #endif
  80
  81 #define ft_fixup_l3cache(x, y)
  82
  83 #if defined(CONFIG_L2_CACHE)
  84 /* return size in kilobytes */
  85 static inline u32 l2cache_size(void)
  86 {
  87         volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
  88         volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
  89         u32 ver = SVR_SOC_VER(get_svr());
  90
  91         switch (l2siz_field) {
  92         case 0x0:
  93                 break;
  94         case 0x1:
  95                 if (ver == SVR_8540 || ver == SVR_8560   ||
  96                     ver == SVR_8541 || ver == SVR_8541_E ||
  97                     ver == SVR_8555 || ver == SVR_8555_E)
  98                         return 128;
  99                 else
 100                         return 256;
 101                 break;
 102         case 0x2:
 103                 if (ver == SVR_8540 || ver == SVR_8560   ||
 104                     ver == SVR_8541 || ver == SVR_8541_E ||
 105                     ver == SVR_8555 || ver == SVR_8555_E)
 106                         return 256;
 107                 else
 108                         return 512;
 109                 break;
 110         case 0x3:
 111                 return 1024;
 112                 break;
 113         }
 114
 115         return 0;
 116 }
 117
 118 static inline void ft_fixup_l2cache(void *blob)
 119 {
 120         int len, off;
 121         u32 *ph;
 122         struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
 123         char compat_buf[38];
 124
 125         const u32 line_size = 32;
 126         const u32 num_ways = 8;
 127         const u32 size = l2cache_size() * 1024;
 128         const u32 num_sets = size / (line_size * num_ways);
 129
 130         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 131         if (off < 0) {
 132                 debug("no cpu node fount\n");
 133                 return;
 134         }
 135
 136         ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
 137
 138         if (ph == NULL) {
 139                 debug("no next-level-cache property\n");
 140                 return ;
 141         }
 142
 143         off = fdt_node_offset_by_phandle(blob, *ph);
 144         if (off < 0) {
 145                 printf("%s: %s\n", __func__, fdt_strerror(off));
 146                 return ;
 147         }
 148
 149         if (cpu) {
 150                 len = sprintf(compat_buf, "fsl,mpc%s-l2-cache-controller",
 151                                 cpu->name);
 152                 sprintf(&compat_buf[len + 1], "cache");
 153         }
 154         fdt_setprop(blob, off, "cache-unified", NULL, 0);
 155         fdt_setprop_cell(blob, off, "cache-block-size", line_size);
 156         fdt_setprop_cell(blob, off, "cache-size", size);
 157         fdt_setprop_cell(blob, off, "cache-sets", num_sets);
 158         fdt_setprop_cell(blob, off, "cache-level", 2);
 159         fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf));
 160
 161         /* we dont bother w/L3 since no platform of this type has one */
 162 }
 163 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
 164 static inline void ft_fixup_l2cache(void *blob)
 165 {
 166         int off, l2_off, l3_off = -1;
 167         u32 *ph;
 168         u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 169         u32 size, line_size, num_ways, num_sets;
 170
 171         size = (l2cfg0 & 0x3fff) * 64 * 1024;
 172         num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
 173         line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
 174         num_sets = size / (line_size * num_ways);
 175
 176         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 177
 178         while (off != -FDT_ERR_NOTFOUND) {
 179                 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
 180
 181                 if (ph == NULL) {
 182                         debug("no next-level-cache property\n");
 183                         goto next;
 184                 }
 185
 186                 l2_off = fdt_node_offset_by_phandle(blob, *ph);
 187                 if (l2_off < 0) {
 188                         printf("%s: %s\n", __func__, fdt_strerror(off));
 189                         goto next;
 190                 }
 191
 192                 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
 193                 fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size);
 194                 fdt_setprop_cell(blob, l2_off, "cache-size", size);
 195                 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
 196                 fdt_setprop_cell(blob, l2_off, "cache-level", 2);
 197                 fdt_setprop(blob, l2_off, "compatible", "cache", 6);
 198
 199                 if (l3_off < 0) {
 200                         ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
 201
 202                         if (ph == NULL) {
 203                                 debug("no next-level-cache property\n");
 204                                 goto next;
 205                         }
 206                         l3_off = *ph;
 207                 }
 208 next:
 209                 off = fdt_node_offset_by_prop_value(blob, off,
 210                                 "device_type", "cpu", 4);
 211         }
 212         if (l3_off > 0) {
 213                 l3_off = fdt_node_offset_by_phandle(blob, l3_off);
 214                 if (l3_off < 0) {
 215                         printf("%s: %s\n", __func__, fdt_strerror(off));
 216                         return ;
 217                 }
 218                 ft_fixup_l3cache(blob, l3_off);
 219         }
 220 }
 221 #else
 222 #define ft_fixup_l2cache(x)
 223 #endif
 224
 225 static inline void ft_fixup_cache(void *blob)
 226 {
 227         int off;
 228
 229         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 230
 231         while (off != -FDT_ERR_NOTFOUND) {
 232                 u32 l1cfg0 = mfspr(SPRN_L1CFG0);
 233                 u32 l1cfg1 = mfspr(SPRN_L1CFG1);
 234                 u32 isize, iline_size, inum_sets, inum_ways;
 235                 u32 dsize, dline_size, dnum_sets, dnum_ways;
 236
 237                 /* d-side config */
 238                 dsize = (l1cfg0 & 0x7ff) * 1024;
 239                 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
 240                 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
 241                 dnum_sets = dsize / (dline_size * dnum_ways);
 242
 243                 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
 244                 fdt_setprop_cell(blob, off, "d-cache-size", dsize);
 245                 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
 246
 247                 /* i-side config */
 248                 isize = (l1cfg1 & 0x7ff) * 1024;
 249                 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
 250                 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
 251                 inum_sets = isize / (iline_size * inum_ways);
 252
 253                 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
 254                 fdt_setprop_cell(blob, off, "i-cache-size", isize);
 255                 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
 256
 257                 off = fdt_node_offset_by_prop_value(blob, off,
 258                                 "device_type", "cpu", 4);
 259         }
 260
 261         ft_fixup_l2cache(blob);
 262 }
 263
 264
 265 void fdt_add_enet_stashing(void *fdt)
 266 {
 267         do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
 268
 269         do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
 270
 271         do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
 272 }
 273
 274 void ft_cpu_setup(void *blob, bd_t *bd)
 275 {
 276         int off;
 277         int val;
 278         sys_info_t sysinfo;
 279
 280         /* delete crypto node if not on an E-processor */
 281         if (!IS_E_PROCESSOR(get_svr()))
 282                 fdt_fixup_crypto_node(blob, 0);
 283
 284         fdt_fixup_ethernet(blob);
 285
 286         fdt_add_enet_stashing(blob);
 287
 288         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 289                 "timebase-frequency", bd->bi_busfreq / 8, 1);
 290         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 291                 "bus-frequency", bd->bi_busfreq, 1);
 292         get_sys_info(&sysinfo);
 293         off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 294         while (off != -FDT_ERR_NOTFOUND) {
 295                 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
 296                 val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]);
 297                 fdt_setprop(blob, off, "clock-frequency", &val, 4);
 298                 off = fdt_node_offset_by_prop_value(blob, off, "device_type",
 299                                                         "cpu", 4);
 300         }
 301         do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
 302                 "bus-frequency", bd->bi_busfreq, 1);
 303
 304         do_fixup_by_compat_u32(blob, "fsl,pq3-localbus",
 305                 "bus-frequency", gd->lbc_clk, 1);
 306         do_fixup_by_compat_u32(blob, "fsl,elbc",
 307                 "bus-frequency", gd->lbc_clk, 1);
 308 #ifdef CONFIG_QE
 309         ft_qe_setup(blob);
 310 #endif
 311
 312 #ifdef CONFIG_SYS_NS16550
 313         do_fixup_by_compat_u32(blob, "ns16550",
 314                 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 315 #endif
 316
 317 #ifdef CONFIG_CPM2
 318         do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
 319                 "current-speed", bd->bi_baudrate, 1);
 320
 321         do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
 322                 "clock-frequency", bd->bi_brgfreq, 1);
 323 #endif
 324
 325         fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 326
 327 #ifdef CONFIG_MP
 328         ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
 329 #endif
 330
 331         ft_fixup_cache(blob);
 332
 333 #if defined(CONFIG_FSL_ESDHC)
 334         fdt_fixup_esdhc(blob, bd);
 335 #endif
 336 }