2 * Copyright 2007 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <fdt_support.h>
29 #include <asm/processor.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 extern void ft_qe_setup(void *blob);
38 void ft_fixup_cpu(void *blob, u64 memory_limit)
41 ulong spin_tbl_addr = get_spin_addr();
42 u32 bootpg, id = get_my_id();
44 /* if we have 4G or more of memory, put the boot page at 4Gb-4k */
45 if ((u64)gd->ram_size > 0xfffff000)
48 bootpg = gd->ram_size - 4096;
50 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
51 while (off != -FDT_ERR_NOTFOUND) {
52 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
56 fdt_setprop_string(blob, off, "status", "okay");
58 u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
59 val = cpu_to_fdt32(val);
60 fdt_setprop_string(blob, off, "status",
62 fdt_setprop_string(blob, off, "enable-method",
64 fdt_setprop(blob, off, "cpu-release-addr",
68 printf ("cpu NULL\n");
70 off = fdt_node_offset_by_prop_value(blob, off,
71 "device_type", "cpu", 4);
74 /* Reserve the boot page so OSes dont use it */
75 if ((u64)bootpg < memory_limit) {
76 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
78 printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
83 #ifdef CONFIG_L2_CACHE
84 /* return size in kilobytes */
85 static inline u32 l2cache_size(void)
87 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
88 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
89 u32 ver = SVR_SOC_VER(get_svr());
91 switch (l2siz_field) {
95 if (ver == SVR_8540 || ver == SVR_8560 ||
96 ver == SVR_8541 || ver == SVR_8541_E ||
97 ver == SVR_8555 || ver == SVR_8555_E)
103 if (ver == SVR_8540 || ver == SVR_8560 ||
104 ver == SVR_8541 || ver == SVR_8541_E ||
105 ver == SVR_8555 || ver == SVR_8555_E)
118 static inline void ft_fixup_l2cache(void *blob)
122 struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
125 const u32 line_size = 32;
126 const u32 num_ways = 8;
127 const u32 size = l2cache_size() * 1024;
128 const u32 num_sets = size / (line_size * num_ways);
130 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
132 debug("no cpu node fount\n");
136 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
139 debug("no next-level-cache property\n");
143 off = fdt_node_offset_by_phandle(blob, *ph);
145 printf("%s: %s\n", __func__, fdt_strerror(off));
150 len = sprintf(compat_buf, "fsl,mpc%s-l2-cache-controller",
152 sprintf(&compat_buf[len + 1], "cache");
154 fdt_setprop(blob, off, "cache-unified", NULL, 0);
155 fdt_setprop_cell(blob, off, "cache-block-size", line_size);
156 fdt_setprop_cell(blob, off, "cache-size", size);
157 fdt_setprop_cell(blob, off, "cache-sets", num_sets);
158 fdt_setprop_cell(blob, off, "cache-level", 2);
159 fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf));
162 #define ft_fixup_l2cache(x)
165 static inline void ft_fixup_cache(void *blob)
169 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
171 while (off != -FDT_ERR_NOTFOUND) {
172 u32 l1cfg0 = mfspr(SPRN_L1CFG0);
173 u32 l1cfg1 = mfspr(SPRN_L1CFG1);
174 u32 isize, iline_size, inum_sets, inum_ways;
175 u32 dsize, dline_size, dnum_sets, dnum_ways;
178 dsize = (l1cfg0 & 0x7ff) * 1024;
179 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
180 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
181 dnum_sets = dsize / (dline_size * dnum_ways);
183 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
184 fdt_setprop_cell(blob, off, "d-cache-size", dsize);
185 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
188 isize = (l1cfg1 & 0x7ff) * 1024;
189 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
190 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
191 inum_sets = isize / (iline_size * inum_ways);
193 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
194 fdt_setprop_cell(blob, off, "i-cache-size", isize);
195 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
197 off = fdt_node_offset_by_prop_value(blob, off,
198 "device_type", "cpu", 4);
201 ft_fixup_l2cache(blob);
205 void fdt_add_enet_stashing(void *fdt)
207 do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
209 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
211 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
214 void ft_cpu_setup(void *blob, bd_t *bd)
216 /* delete crypto node if not on an E-processor */
217 if (!IS_E_PROCESSOR(get_svr()))
218 fdt_fixup_crypto_node(blob, 0);
220 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
221 defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
222 fdt_fixup_ethernet(blob);
224 fdt_add_enet_stashing(blob);
227 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
228 "timebase-frequency", bd->bi_busfreq / 8, 1);
229 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
230 "bus-frequency", bd->bi_busfreq, 1);
231 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
232 "clock-frequency", bd->bi_intfreq, 1);
233 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
234 "bus-frequency", bd->bi_busfreq, 1);
236 do_fixup_by_compat_u32(blob, "fsl,pq3-localbus",
237 "bus-frequency", gd->lbc_clk, 1);
238 do_fixup_by_compat_u32(blob, "fsl,elbc",
239 "bus-frequency", gd->lbc_clk, 1);
244 #ifdef CONFIG_SYS_NS16550
245 do_fixup_by_compat_u32(blob, "ns16550",
246 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
250 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
251 "current-speed", bd->bi_baudrate, 1);
253 do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
254 "clock-frequency", bd->bi_brgfreq, 1);
257 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
260 ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
263 ft_fixup_cache(blob);