2 * Copyright 2007 Freescale Semiconductor, Inc.
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <fdt_support.h>
29 #include <asm/processor.h>
31 DECLARE_GLOBAL_DATA_PTR;
33 extern void ft_qe_setup(void *blob);
38 void ft_fixup_cpu(void *blob, u64 memory_limit)
41 ulong spin_tbl_addr = get_spin_addr();
42 u32 bootpg = determine_mp_bootpg();
45 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
46 while (off != -FDT_ERR_NOTFOUND) {
47 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
51 fdt_setprop_string(blob, off, "status", "okay");
53 u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
54 val = cpu_to_fdt32(val);
55 fdt_setprop_string(blob, off, "status",
57 fdt_setprop_string(blob, off, "enable-method",
59 fdt_setprop(blob, off, "cpu-release-addr",
63 printf ("cpu NULL\n");
65 off = fdt_node_offset_by_prop_value(blob, off,
66 "device_type", "cpu", 4);
69 /* Reserve the boot page so OSes dont use it */
70 if ((u64)bootpg < memory_limit) {
71 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
73 printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
78 #define ft_fixup_l3cache(x, y)
80 #if defined(CONFIG_L2_CACHE)
81 /* return size in kilobytes */
82 static inline u32 l2cache_size(void)
84 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
85 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
86 u32 ver = SVR_SOC_VER(get_svr());
88 switch (l2siz_field) {
92 if (ver == SVR_8540 || ver == SVR_8560 ||
93 ver == SVR_8541 || ver == SVR_8541_E ||
94 ver == SVR_8555 || ver == SVR_8555_E)
100 if (ver == SVR_8540 || ver == SVR_8560 ||
101 ver == SVR_8541 || ver == SVR_8541_E ||
102 ver == SVR_8555 || ver == SVR_8555_E)
115 static inline void ft_fixup_l2cache(void *blob)
119 struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
122 const u32 line_size = 32;
123 const u32 num_ways = 8;
124 const u32 size = l2cache_size() * 1024;
125 const u32 num_sets = size / (line_size * num_ways);
127 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
129 debug("no cpu node fount\n");
133 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
136 debug("no next-level-cache property\n");
140 off = fdt_node_offset_by_phandle(blob, *ph);
142 printf("%s: %s\n", __func__, fdt_strerror(off));
147 len = sprintf(compat_buf, "fsl,mpc%s-l2-cache-controller",
149 sprintf(&compat_buf[len + 1], "cache");
151 fdt_setprop(blob, off, "cache-unified", NULL, 0);
152 fdt_setprop_cell(blob, off, "cache-block-size", line_size);
153 fdt_setprop_cell(blob, off, "cache-size", size);
154 fdt_setprop_cell(blob, off, "cache-sets", num_sets);
155 fdt_setprop_cell(blob, off, "cache-level", 2);
156 fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf));
158 /* we dont bother w/L3 since no platform of this type has one */
160 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
161 static inline void ft_fixup_l2cache(void *blob)
163 int off, l2_off, l3_off = -1;
165 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
166 u32 size, line_size, num_ways, num_sets;
168 size = (l2cfg0 & 0x3fff) * 64 * 1024;
169 num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
170 line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
171 num_sets = size / (line_size * num_ways);
173 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
175 while (off != -FDT_ERR_NOTFOUND) {
176 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
179 debug("no next-level-cache property\n");
183 l2_off = fdt_node_offset_by_phandle(blob, *ph);
185 printf("%s: %s\n", __func__, fdt_strerror(off));
189 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
190 fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size);
191 fdt_setprop_cell(blob, l2_off, "cache-size", size);
192 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
193 fdt_setprop_cell(blob, l2_off, "cache-level", 2);
194 fdt_setprop(blob, l2_off, "compatible", "cache", 6);
197 ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
200 debug("no next-level-cache property\n");
206 off = fdt_node_offset_by_prop_value(blob, off,
207 "device_type", "cpu", 4);
210 l3_off = fdt_node_offset_by_phandle(blob, l3_off);
212 printf("%s: %s\n", __func__, fdt_strerror(off));
215 ft_fixup_l3cache(blob, l3_off);
219 #define ft_fixup_l2cache(x)
222 static inline void ft_fixup_cache(void *blob)
226 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
228 while (off != -FDT_ERR_NOTFOUND) {
229 u32 l1cfg0 = mfspr(SPRN_L1CFG0);
230 u32 l1cfg1 = mfspr(SPRN_L1CFG1);
231 u32 isize, iline_size, inum_sets, inum_ways;
232 u32 dsize, dline_size, dnum_sets, dnum_ways;
235 dsize = (l1cfg0 & 0x7ff) * 1024;
236 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
237 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
238 dnum_sets = dsize / (dline_size * dnum_ways);
240 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
241 fdt_setprop_cell(blob, off, "d-cache-size", dsize);
242 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
245 isize = (l1cfg1 & 0x7ff) * 1024;
246 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
247 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
248 inum_sets = isize / (iline_size * inum_ways);
250 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
251 fdt_setprop_cell(blob, off, "i-cache-size", isize);
252 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
254 off = fdt_node_offset_by_prop_value(blob, off,
255 "device_type", "cpu", 4);
258 ft_fixup_l2cache(blob);
262 void fdt_add_enet_stashing(void *fdt)
264 do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
266 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
268 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
271 void ft_cpu_setup(void *blob, bd_t *bd)
277 /* delete crypto node if not on an E-processor */
278 if (!IS_E_PROCESSOR(get_svr()))
279 fdt_fixup_crypto_node(blob, 0);
281 fdt_fixup_ethernet(blob);
283 fdt_add_enet_stashing(blob);
285 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
286 "timebase-frequency", bd->bi_busfreq / 8, 1);
287 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
288 "bus-frequency", bd->bi_busfreq, 1);
289 get_sys_info(&sysinfo);
290 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
291 while (off != -FDT_ERR_NOTFOUND) {
292 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
293 val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]);
294 fdt_setprop(blob, off, "clock-frequency", &val, 4);
295 off = fdt_node_offset_by_prop_value(blob, off, "device_type",
298 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
299 "bus-frequency", bd->bi_busfreq, 1);
301 do_fixup_by_compat_u32(blob, "fsl,pq3-localbus",
302 "bus-frequency", gd->lbc_clk, 1);
303 do_fixup_by_compat_u32(blob, "fsl,elbc",
304 "bus-frequency", gd->lbc_clk, 1);
309 #ifdef CONFIG_SYS_NS16550
310 do_fixup_by_compat_u32(blob, "ns16550",
311 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
315 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
316 "current-speed", bd->bi_baudrate, 1);
318 do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
319 "clock-frequency", bd->bi_brgfreq, 1);
322 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
325 ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
328 ft_fixup_cache(blob);