2 * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 #include <asm/cache.h>
38 #define CPU_TYPE_ENTRY(x) {#x, SVR_##x}
40 struct cpu_type cpu_type_list [] = {
42 CPU_TYPE_ENTRY(8533_E),
45 CPU_TYPE_ENTRY(8541_E),
47 CPU_TYPE_ENTRY(8543_E),
49 CPU_TYPE_ENTRY(8544_E),
51 CPU_TYPE_ENTRY(8545_E),
52 CPU_TYPE_ENTRY(8547_E),
54 CPU_TYPE_ENTRY(8548_E),
56 CPU_TYPE_ENTRY(8555_E),
59 CPU_TYPE_ENTRY(8567_E),
61 CPU_TYPE_ENTRY(8568_E),
63 CPU_TYPE_ENTRY(8572_E),
69 uint lcrr; /* local bus clock ratio register */
70 uint clkdiv; /* clock divider portion of lcrr */
77 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
80 ver = SVR_SOC_VER(svr);
86 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
87 if (cpu_type_list[i].soc_ver == ver) {
88 puts(cpu_type_list[i].name);
92 if (i == ARRAY_SIZE(cpu_type_list))
95 printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
100 major = PVR_MAJ(pvr);
101 minor = PVR_MIN(pvr);
105 case PVR_FAM(PVR_85xx):
112 printf(", Version: %d.%d, (0x%08x)\n", major, minor, pvr);
114 get_sys_info(&sysinfo);
116 puts("Clock Configuration:\n");
117 printf(" CPU:%4lu MHz, ", sysinfo.freqProcessor / 1000000);
118 printf("CCB:%4lu MHz,\n", sysinfo.freqSystemBus / 1000000);
120 ddr_ratio = ((gur->porpllsr) & 0x00003e00) >> 9;
123 printf(" DDR:%4lu MHz, ", sysinfo.freqDDRBus / 2000000);
126 printf(" DDR:%4lu MHz (Synchronous), ", sysinfo.freqDDRBus / 2000000);
129 printf(" DDR:%4lu MHz (Asynchronous), ", sysinfo.freqDDRBus / 2000000);
133 #if defined(CFG_LBC_LCRR)
137 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
142 clkdiv = lcrr & 0x0f;
143 if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
144 #if defined(CONFIG_MPC8548) || defined(CONFIG_MPC8544)
146 * Yes, the entire PQ38 family use the same
147 * bit-representation for twice the clock divider values.
151 printf("LBC:%4lu MHz\n",
152 sysinfo.freqSystemBus / 1000000 / clkdiv);
154 printf("LBC: unknown (lcrr: 0x%08x)\n", lcrr);
158 printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000);
161 puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n");
167 /* ------------------------------------------------------------------------- */
169 int do_reset (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
176 /* e500 v2 core has reset control register */
177 volatile unsigned int * rstcr;
178 rstcr = (volatile unsigned int *)(CFG_IMMR + 0xE00B0);
179 *rstcr = 0x2; /* HRESET_REQ */
182 * Initiate hard reset in debug control register DBCR0
183 * Make sure MSR[DE] = 1
185 unsigned long val, msr;
200 * Get timebase clock frequency
202 unsigned long get_tbclk (void)
207 get_sys_info(&sys_info);
208 return ((sys_info.freqSystemBus + 7L) / 8L);
212 #if defined(CONFIG_WATCHDOG)
216 int re_enable = disable_interrupts();
217 reset_85xx_watchdog();
218 if (re_enable) enable_interrupts();
222 reset_85xx_watchdog(void)
225 * Clear TSR(WIS) bit by writing 1
228 val = mfspr(SPRN_TSR);
230 mtspr(SPRN_TSR, val);
232 #endif /* CONFIG_WATCHDOG */
234 #if defined(CONFIG_DDR_ECC)
235 void dma_init(void) {
236 volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
238 dma->satr0 = 0x02c40000;
239 dma->datr0 = 0x02c40000;
240 dma->sr0 = 0xfffffff; /* clear any errors */
241 asm("sync; isync; msync");
245 uint dma_check(void) {
246 volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
247 volatile uint status = dma->sr0;
249 /* While the channel is busy, spin */
250 while((status & 4) == 4) {
254 /* clear MR0[CS] channel start bit */
255 dma->mr0 &= 0x00000001;
256 asm("sync;isync;msync");
259 printf ("DMA Error: status = %x\n", status);
264 int dma_xfer(void *dest, uint count, void *src) {
265 volatile ccsr_dma_t *dma = (void *)(CFG_MPC85xx_DMA_ADDR);
267 dma->dar0 = (uint) dest;
268 dma->sar0 = (uint) src;
270 dma->mr0 = 0xf000004;
271 asm("sync;isync;msync");
272 dma->mr0 = 0xf000005;
273 asm("sync;isync;msync");