2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright Freescale Semiconductor, Inc. 2004, 2006. All rights reserved.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * U-Boot - Startup Code for MPC83xx PowerPC based Embedded Boards
34 #define CONFIG_83XX 1 /* needed for Linux kernel header files*/
35 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
37 #include <ppc_asm.tmpl>
40 #include <asm/cache.h>
43 #ifndef CONFIG_IDENT_STRING
44 #define CONFIG_IDENT_STRING "MPC83XX"
47 /* We don't want the MMU yet.
52 * Floating Point enable, Machine Check and Recoverable Interr.
55 #define MSR_KERNEL (MSR_FP|MSR_RI)
57 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
61 * Set up GOT: Global Offset Table
63 * Use r14 to access the GOT
66 GOT_ENTRY(_GOT2_TABLE_)
67 GOT_ENTRY(_FIXUP_TABLE_)
70 GOT_ENTRY(_start_of_vectors)
71 GOT_ENTRY(_end_of_vectors)
72 GOT_ENTRY(transfer_to_handler)
76 GOT_ENTRY(__bss_start)
80 * The Hard Reset Configuration Word (HRCW) table is in the first 64
81 * (0x40) bytes of flash. It has 8 bytes, but each byte is repeated 8
82 * times so the processor can fetch it out of flash whether the flash
83 * is 8, 16, 32, or 64 bits wide (hardware trickery).
86 #define _HRCW_TABLE_ENTRY(w) \
87 .fill 8,1,(((w)>>24)&0xff); \
88 .fill 8,1,(((w)>>16)&0xff); \
89 .fill 8,1,(((w)>> 8)&0xff); \
90 .fill 8,1,(((w) )&0xff)
92 _HRCW_TABLE_ENTRY(CFG_HRCW_LOW)
93 _HRCW_TABLE_ENTRY(CFG_HRCW_HIGH)
96 * Magic number and version string - put it after the HRCW since it
97 * cannot be first in flash like it is in many other processors.
99 .long 0x27051956 /* U-Boot Magic Number */
101 .globl version_string
103 .ascii U_BOOT_VERSION
104 .ascii " (", __DATE__, " - ", __TIME__, ")"
105 .ascii " ", CONFIG_IDENT_STRING, "\0"
108 #ifndef CONFIG_DEFAULT_IMMR
109 #error CONFIG_DEFAULT_IMMR must be defined
110 #endif /* CFG_DEFAULT_IMMR */
112 #define CFG_IMMR CONFIG_DEFAULT_IMMR
113 #endif /* CFG_IMMR */
116 * After configuration, a system reset exception is executed using the
117 * vector at offset 0x100 relative to the base set by MSR[IP]. If
118 * MSR[IP] is 0, the base address is 0x00000000. If MSR[IP] is 1, the
119 * base address is 0xfff00000. In the case of a Power On Reset or Hard
120 * Reset, the value of MSR[IP] is determined by the CIP field in the
123 * Other bits in the HRCW set up the Base Address and Port Size in BR0.
124 * This determines the location of the boot ROM (flash or EPROM) in the
125 * processor's address space at boot time. As long as the HRCW is set up
126 * so that we eventually end up executing the code below when the
127 * processor executes the reset exception, the actual values used should
130 * Once we have got here, the address mask in OR0 is cleared so that the
131 * bottom 32K of the boot ROM is effectively repeated all throughout the
132 * processor's address space, after which we can jump to the absolute
133 * address at which the boot ROM was linked at compile time, and proceed
134 * to initialise the memory controller without worrying if the rug will
135 * be pulled out from under us, so to speak (it will be fine as long as
136 * we configure BR0 with the same boot ROM link address).
138 . = EXC_OFF_SYS_RESET
141 _start: /* time t 0 */
142 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/
146 . = EXC_OFF_SYS_RESET + 0x10
150 li r21, BOOTFLAG_WARM /* Software reboot */
154 boot_cold: /* time t 3 */
155 lis r4, CONFIG_DEFAULT_IMMR@h
157 boot_warm: /* time t 5 */
158 mfmsr r5 /* save msr contents */
160 ori r3, r3, CFG_IMMR@l
163 /* Initialise the E300 processor core */
164 /*------------------------------------------*/
170 /* Inflate flash location so it appears everywhere, calculate */
171 /* the absolute address in final location of the FLASH, jump */
172 /* there and deflate the flash size back to minimal size */
173 /*------------------------------------------------------------*/
175 lis r4, (CFG_MONITOR_BASE)@h
176 ori r4, r4, (CFG_MONITOR_BASE)@l
177 addi r5, r4, in_flash - _start + EXC_OFF_SYS_RESET
181 #if 1 /* Remapping flash with LAW0. */
182 bl remap_flash_by_law0
184 #endif /* CFG_RAMBOOT */
191 * Cache must be enabled here for stack-in-cache trick.
192 * This means we need to enable the BATS.
194 * 1) for the EVB, original gt regs need to be mapped
195 * 2) need to have an IBAT for the 0xf region,
196 * we are running there!
197 * Cache should be turned on after BATs, since by default
198 * everything is write-through.
199 * The init-mem BAT can be reused after reloc. The old
200 * gt-regs BAT can be reused after board_init_f calls
201 * board_early_init_f (EVB only).
203 /* enable address translation */
207 /* enable and invalidate the data cache */
210 #ifdef CFG_INIT_RAM_LOCK
215 /* set up the stack pointer in our newly created
217 lis r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
218 ori r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
220 li r0, 0 /* Make room for stack frame header and */
221 stwu r0, -4(r1) /* clear final stack frame so that */
222 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
225 /* let the C-code set up the rest */
227 /* Be careful to keep code relocatable & stack humble */
228 /*------------------------------------------------------*/
230 GET_GOT /* initialize GOT access */
234 /* run low-level CPU init code (in Flash)*/
239 /* run 1st part of board init code (in Flash)*/
246 .globl _start_of_vectors
250 STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
252 /* Data Storage exception. */
253 STD_EXCEPTION(0x300, DataStorage, UnknownException)
255 /* Instruction Storage exception. */
256 STD_EXCEPTION(0x400, InstStorage, UnknownException)
258 /* External Interrupt exception. */
260 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
263 /* Alignment exception. */
266 EXCEPTION_PROLOG(SRR0, SRR1)
271 addi r3,r1,STACK_FRAME_OVERHEAD
273 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
274 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
275 lwz r6,GOT(transfer_to_handler)
279 .long AlignmentException - _start + EXC_OFF_SYS_RESET
280 .long int_return - _start + EXC_OFF_SYS_RESET
282 /* Program check exception */
285 EXCEPTION_PROLOG(SRR0, SRR1)
286 addi r3,r1,STACK_FRAME_OVERHEAD
288 rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
289 rlwimi r20,r23,0,25,25 /* copy IP bit from saved MSR */
290 lwz r6,GOT(transfer_to_handler)
294 .long ProgramCheckException - _start + EXC_OFF_SYS_RESET
295 .long int_return - _start + EXC_OFF_SYS_RESET
297 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
299 /* I guess we could implement decrementer, and may have
300 * to someday for timekeeping.
302 STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
304 STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
305 STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
306 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
307 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
309 STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
310 STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
312 STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
313 STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
314 STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
318 * This exception occurs when the program counter matches the
319 * Instruction Address Breakpoint Register (IABR).
321 * I want the cpu to halt if this occurs so I can hunt around
322 * with the debugger and look at things.
324 * When DEBUG is defined, both machine check enable (in the MSR)
325 * and checkstop reset enable (in the reset mode register) are
326 * turned off and so a checkstop condition will result in the cpu
329 * I force the cpu into a checkstop condition by putting an illegal
330 * instruction here (at least this is the theory).
332 * well - that didnt work, so just do an infinite loop!
336 STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
338 STD_EXCEPTION(0x1400, SMI, UnknownException)
340 STD_EXCEPTION(0x1500, Trap_15, UnknownException)
341 STD_EXCEPTION(0x1600, Trap_16, UnknownException)
342 STD_EXCEPTION(0x1700, Trap_17, UnknownException)
343 STD_EXCEPTION(0x1800, Trap_18, UnknownException)
344 STD_EXCEPTION(0x1900, Trap_19, UnknownException)
345 STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
346 STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
347 STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
348 STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
349 STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
350 STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
351 STD_EXCEPTION(0x2000, Trap_20, UnknownException)
352 STD_EXCEPTION(0x2100, Trap_21, UnknownException)
353 STD_EXCEPTION(0x2200, Trap_22, UnknownException)
354 STD_EXCEPTION(0x2300, Trap_23, UnknownException)
355 STD_EXCEPTION(0x2400, Trap_24, UnknownException)
356 STD_EXCEPTION(0x2500, Trap_25, UnknownException)
357 STD_EXCEPTION(0x2600, Trap_26, UnknownException)
358 STD_EXCEPTION(0x2700, Trap_27, UnknownException)
359 STD_EXCEPTION(0x2800, Trap_28, UnknownException)
360 STD_EXCEPTION(0x2900, Trap_29, UnknownException)
361 STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
362 STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
363 STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
364 STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
365 STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
366 STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
369 .globl _end_of_vectors
375 * This code finishes saving the registers to the exception frame
376 * and jumps to the appropriate handler for the exception.
377 * Register r21 is pointer into trap frame, r1 has new stack pointer.
379 .globl transfer_to_handler
390 andi. r24,r23,0x3f00 /* get vector offset */
394 lwz r24,0(r23) /* virtual address of handler */
395 lwz r23,4(r23) /* where to go when done */
400 rfi /* jump to handler, enable MMU */
403 mfmsr r28 /* Disable interrupts */
407 SYNC /* Some chip revs need this... */
422 lwz r2,_NIP(r1) /* Restore environment */
433 * This code initialises the E300 processor core
434 * (conforms to PowerPC 603e spec)
435 * Note: expects original MSR contents to be in r5.
437 .globl init_e300_core
438 init_e300_core: /* time t 10 */
439 /* Initialize machine status; enable machine check interrupt */
440 /*-----------------------------------------------------------*/
442 li r3, MSR_KERNEL /* Set ME and RI flags */
443 rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
445 rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
447 SYNC /* Some chip revs need this... */
450 mtspr SRR1, r3 /* Make SRR1 match MSR */
454 #if defined(CONFIG_WATCHDOG)
455 /* Initialise the Wathcdog values and reset it (if req) */
456 /*------------------------------------------------------*/
457 lis r4, CFG_WATCHDOG_VALUE
458 ori r4, r4, (SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR)
468 /* Disable Wathcdog */
469 /*-------------------*/
471 /* Check to see if its enabled for disabling
472 once disabled by SW you can't re-enable */
478 #endif /* CONFIG_WATCHDOG */
480 /* Initialize the Hardware Implementation-dependent Registers */
481 /* HID0 also contains cache control */
482 /*------------------------------------------------------*/
484 lis r3, CFG_HID0_INIT@h
485 ori r3, r3, CFG_HID0_INIT@l
489 lis r3, CFG_HID0_FINAL@h
490 ori r3, r3, CFG_HID0_FINAL@l
495 ori r3, r3, CFG_HID2@l
499 /* clear all BAT's */
500 /*----------------------------------*/
521 /* invalidate all tlb's
523 * From the 603e User Manual: "The 603e provides the ability to
524 * invalidate a TLB entry. The TLB Invalidate Entry (tlbie)
525 * instruction invalidates the TLB entry indexed by the EA, and
526 * operates on both the instruction and data TLBs simultaneously
527 * invalidating four TLB entries (both sets in each TLB). The
528 * index corresponds to bits 15-19 of the EA. To invalidate all
529 * entries within both TLBs, 32 tlbie instructions should be
530 * issued, incrementing this field by one each time."
532 * "Note that the tlbia instruction is not implemented on the
535 * bits 15-19 correspond to addresses 0x00000000 to 0x0001F000
536 * incrementing by 0x1000 each time. The code below is sort of
537 * based on code in "flush_tlbs" from arch/ppc/kernel/head.S
550 /*------------------------------*/
553 .globl invalidate_bats
555 /* invalidate BATs */
560 #if (CFG_HID2 & HID2_HBE)
571 #if (CFG_HID2 & HID2_HBE)
581 /* setup_bats - set them up to some initial state */
587 addis r4, r0, CFG_IBAT0L@h
588 ori r4, r4, CFG_IBAT0L@l
589 addis r3, r0, CFG_IBAT0U@h
590 ori r3, r3, CFG_IBAT0U@l
596 addis r4, r0, CFG_DBAT0L@h
597 ori r4, r4, CFG_DBAT0L@l
598 addis r3, r0, CFG_DBAT0U@h
599 ori r3, r3, CFG_DBAT0U@l
605 addis r4, r0, CFG_IBAT1L@h
606 ori r4, r4, CFG_IBAT1L@l
607 addis r3, r0, CFG_IBAT1U@h
608 ori r3, r3, CFG_IBAT1U@l
614 addis r4, r0, CFG_DBAT1L@h
615 ori r4, r4, CFG_DBAT1L@l
616 addis r3, r0, CFG_DBAT1U@h
617 ori r3, r3, CFG_DBAT1U@l
623 addis r4, r0, CFG_IBAT2L@h
624 ori r4, r4, CFG_IBAT2L@l
625 addis r3, r0, CFG_IBAT2U@h
626 ori r3, r3, CFG_IBAT2U@l
632 addis r4, r0, CFG_DBAT2L@h
633 ori r4, r4, CFG_DBAT2L@l
634 addis r3, r0, CFG_DBAT2U@h
635 ori r3, r3, CFG_DBAT2U@l
641 addis r4, r0, CFG_IBAT3L@h
642 ori r4, r4, CFG_IBAT3L@l
643 addis r3, r0, CFG_IBAT3U@h
644 ori r3, r3, CFG_IBAT3U@l
650 addis r4, r0, CFG_DBAT3L@h
651 ori r4, r4, CFG_DBAT3L@l
652 addis r3, r0, CFG_DBAT3U@h
653 ori r3, r3, CFG_DBAT3U@l
658 #if (CFG_HID2 & HID2_HBE)
660 addis r4, r0, CFG_IBAT4L@h
661 ori r4, r4, CFG_IBAT4L@l
662 addis r3, r0, CFG_IBAT4U@h
663 ori r3, r3, CFG_IBAT4U@l
669 addis r4, r0, CFG_DBAT4L@h
670 ori r4, r4, CFG_DBAT4L@l
671 addis r3, r0, CFG_DBAT4U@h
672 ori r3, r3, CFG_DBAT4U@l
678 addis r4, r0, CFG_IBAT5L@h
679 ori r4, r4, CFG_IBAT5L@l
680 addis r3, r0, CFG_IBAT5U@h
681 ori r3, r3, CFG_IBAT5U@l
687 addis r4, r0, CFG_DBAT5L@h
688 ori r4, r4, CFG_DBAT5L@l
689 addis r3, r0, CFG_DBAT5U@h
690 ori r3, r3, CFG_DBAT5U@l
696 addis r4, r0, CFG_IBAT6L@h
697 ori r4, r4, CFG_IBAT6L@l
698 addis r3, r0, CFG_IBAT6U@h
699 ori r3, r3, CFG_IBAT6U@l
705 addis r4, r0, CFG_DBAT6L@h
706 ori r4, r4, CFG_DBAT6L@l
707 addis r3, r0, CFG_DBAT6U@h
708 ori r3, r3, CFG_DBAT6U@l
714 addis r4, r0, CFG_IBAT7L@h
715 ori r4, r4, CFG_IBAT7L@l
716 addis r3, r0, CFG_IBAT7U@h
717 ori r3, r3, CFG_IBAT7U@l
723 addis r4, r0, CFG_DBAT7L@h
724 ori r4, r4, CFG_DBAT7L@l
725 addis r3, r0, CFG_DBAT7U@h
726 ori r3, r3, CFG_DBAT7U@l
733 * -> for (val = 0; val < 0x20000; val+=0x1000)
747 .globl enable_addr_trans
749 /* enable address translation */
751 ori r5, r5, (MSR_IR | MSR_DR)
756 .globl disable_addr_trans
758 /* disable address translation */
761 andi. r0, r3, (MSR_IR | MSR_DR)
770 * Note: requires that all cache bits in
771 * HID0 are in the low half word.
778 ori r4, r4, HID0_ILOCK
780 ori r4, r3, HID0_ICFI
782 mtspr HID0, r4 /* sets enable and invalidate, clears lock */
784 mtspr HID0, r3 /* clears invalidate */
787 .globl icache_disable
791 ori r4, r4, HID0_ICE|HID0_ILOCK
793 ori r4, r3, HID0_ICFI
795 mtspr HID0, r4 /* sets invalidate, clears enable and lock*/
797 mtspr HID0, r3 /* clears invalidate */
803 rlwinm r3, r3, (31 - HID0_ICE_SHIFT + 1), 31, 31
809 li r5, HID0_DCFI|HID0_DLOCK
811 mtspr HID0, r3 /* no invalidate, unlock */
813 ori r5, r3, HID0_DCFI
814 mtspr HID0, r5 /* enable + invalidate */
815 mtspr HID0, r3 /* enable */
819 .globl dcache_disable
823 ori r4, r4, HID0_DCE|HID0_DLOCK
827 mtspr HID0, r4 /* sets invalidate, clears enable and lock */
829 mtspr HID0, r3 /* clears invalidate */
835 rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31
855 /*-------------------------------------------------------------------*/
858 * void relocate_code (addr_sp, gd, addr_moni)
860 * This "function" does not return, instead it continues in RAM
861 * after relocating the monitor code.
865 * r5 = length in bytes
870 mr r1, r3 /* Set new stack pointer */
871 mr r9, r4 /* Save copy of Global Data pointer */
872 mr r10, r5 /* Save copy of Destination Address */
874 mr r3, r5 /* Destination Address */
875 lis r4, CFG_MONITOR_BASE@h /* Source Address */
876 ori r4, r4, CFG_MONITOR_BASE@l
877 lwz r5, GOT(__init_end)
879 li r6, CFG_CACHELINE_SIZE /* Cache Line Size */
884 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE)
885 * + Destination Address
891 /* First our own GOT */
893 /* then the one used by the C code */
903 beq cr1,4f /* In place copy is not necessary */
904 beq 7f /* Protect against 0 count */
933 2: slwi r0,r0,2 /* re copy in reverse order ... y do we needed it? */
941 * Now flush the cache: note that we must start from a cache aligned
942 * address. Otherwise we might miss one cache line.
946 beq 7f /* Always flush prefetch queue in any case */
954 sync /* Wait for all dcbst to complete on bus */
960 7: sync /* Wait for all icbi to complete on bus */
964 * We are done. Do not return, instead branch to second part of board
965 * initialization, now running from RAM.
967 addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
974 * Relocation Function, r14 point to got2+0x8000
976 * Adjust got2 pointers, no need to check for 0, this code
977 * already puts a few entries in the table.
979 li r0,__got2_entries@sectoff@l
980 la r3,GOT(_GOT2_TABLE_)
981 lwz r11,GOT(_GOT2_TABLE_)
991 * Now adjust the fixups and the pointers to the fixups
992 * in case we need to move ourselves again.
994 2: li r0,__fixup_entries@sectoff@l
995 lwz r3,GOT(_FIXUP_TABLE_)
1009 * Now clear BSS segment
1011 lwz r3,GOT(__bss_start)
1012 #if defined(CONFIG_HYMOD)
1014 * For HYMOD - the environment is the very last item in flash.
1015 * The real .bss stops just before environment starts, so only
1016 * clear up to that point.
1018 * taken from mods for FADS board
1020 lwz r4,GOT(environment)
1036 mr r3, r9 /* Global Data pointer */
1037 mr r4, r10 /* Destination Address */
1041 * Copy exception vector code to low memory
1044 * r7: source address, r8: end address, r9: target address
1049 lwz r8, GOT(_end_of_vectors)
1051 li r9, 0x100 /* reset vector always at 0x100 */
1054 bgelr /* return if r7>=r8 - just in case */
1056 mflr r4 /* save link register */
1066 * relocate `hdlr' and `int_return' entries
1068 li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
1069 li r8, Alignment - _start + EXC_OFF_SYS_RESET
1072 addi r7, r7, 0x100 /* next exception vector */
1076 li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
1079 li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
1082 li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
1083 li r8, SystemCall - _start + EXC_OFF_SYS_RESET
1086 addi r7, r7, 0x100 /* next exception vector */
1090 li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
1091 li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
1094 addi r7, r7, 0x100 /* next exception vector */
1098 mfmsr r3 /* now that the vectors have */
1099 lis r7, MSR_IP@h /* relocated into low memory */
1100 ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
1101 andc r3, r3, r7 /* (if it was on) */
1102 SYNC /* Some chip revs need this... */
1106 mtlr r4 /* restore link register */
1110 * Function: relocate entries for one exception vector
1113 lwz r0, 0(r7) /* hdlr ... */
1114 add r0, r0, r3 /* ... += dest_addr */
1117 lwz r0, 4(r7) /* int_return ... */
1118 add r0, r0, r3 /* ... += dest_addr */
1123 #ifdef CFG_INIT_RAM_LOCK
1125 /* Allocate Initial RAM in data cache.
1127 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
1128 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
1129 li r2, ((CFG_INIT_RAM_END & ~31) + \
1130 (CFG_INIT_RAM_ADDR & 31) + 31) / 32
1137 /* Lock the data cache */
1145 .globl unlock_ram_in_cache
1146 unlock_ram_in_cache:
1147 /* invalidate the INIT_RAM section */
1148 lis r3, (CFG_INIT_RAM_ADDR & ~31)@h
1149 ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
1156 sync /* Wait for all icbi to complete on bus */
1159 /* Unlock the data cache and invalidate it */
1161 li r5, HID0_DLOCK|HID0_DCFI
1162 andc r3, r3, r5 /* no invalidate, unlock */
1163 ori r5, r3, HID0_DCFI /* invalidate, unlock */
1164 mtspr HID0, r5 /* invalidate, unlock */
1165 mtspr HID0, r3 /* no invalidate, unlock */
1171 /* When booting from ROM (Flash or EPROM), clear the */
1172 /* Address Mask in OR0 so ROM appears everywhere */
1173 /*----------------------------------------------------*/
1174 lis r3, (CFG_IMMR)@h /* r3 <= CFG_IMMR */
1176 li r5, 0x7fff /* r5 <= 0x00007FFFF */
1178 stw r4, OR0@l(r3) /* OR0 <= OR0 & 0x00007FFFF */
1180 /* As MPC8349E User's Manual presented, when RCW[BMS] is set to 0,
1181 * system will boot from 0x0000_0100, and the LBLAWBAR0[BASE_ADDR]
1182 * reset value is 0x00000; when RCW[BMS] is set to 1, system will boot
1183 * from 0xFFF0_0100, and the LBLAWBAR0[BASE_ADDR] reset value is
1184 * 0xFF800. From the hard resetting to here, the processor fetched and
1185 * executed the instructions one by one. There is not absolutely
1186 * jumping happened. Laterly, the u-boot code has to do an absolutely
1187 * jumping to tell the CPU instruction fetching component what the
1188 * u-boot TEXT base address is. Because the TEXT base resides in the
1189 * boot ROM memory space, to garantee the code can run smoothly after
1190 * that jumping, we must map in the entire boot ROM by Local Access
1191 * Window. Sometimes, we desire an non-0x00000 or non-0xFF800 starting
1192 * address for boot ROM, such as 0xFE000000. In this case, the default
1193 * LBIU Local Access Widow 0 will not cover this memory space. So, we
1194 * need another window to map in it.
1196 lis r4, (CFG_FLASH_BASE)@h
1197 ori r4, r4, (CFG_FLASH_BASE)@l
1198 stw r4, LBLAWBAR1(r3) /* LBLAWBAR1 <= CFG_FLASH_BASE */
1200 /* Store 0x80000012 + log2(CFG_FLASH_SIZE) into LBLAWAR1 */
1201 lis r4, (0x80000012)@h
1202 ori r4, r4, (0x80000012)@l
1203 li r5, CFG_FLASH_SIZE
1204 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1208 stw r4, LBLAWAR1(r3) /* LBLAWAR1 <= 8MB Flash Size */
1211 /* Though all the LBIU Local Access Windows and LBC Banks will be
1212 * initialized in the C code, we'd better configure boot ROM's
1213 * window 0 and bank 0 correctly at here.
1215 remap_flash_by_law0:
1216 /* Initialize the BR0 with the boot ROM starting address. */
1220 lis r5, (CFG_FLASH_BASE & 0xFFFF8000)@h
1221 ori r5, r5, (CFG_FLASH_BASE & 0xFFFF8000)@l
1223 stw r5, BR0(r3) /* r5 <= (CFG_FLASH_BASE & 0xFFFF8000) | (BR0 & 0x00007FFF) */
1226 lis r5, ~((CFG_FLASH_SIZE << 4) - 1)
1230 lis r4, (CFG_FLASH_BASE)@h
1231 ori r4, r4, (CFG_FLASH_BASE)@l
1232 stw r4, LBLAWBAR0(r3) /* LBLAWBAR0 <= CFG_FLASH_BASE */
1234 /* Store 0x80000012 + log2(CFG_FLASH_SIZE) into LBLAWAR0 */
1235 lis r4, (0x80000012)@h
1236 ori r4, r4, (0x80000012)@l
1237 li r5, CFG_FLASH_SIZE
1238 1: srawi. r5, r5, 1 /* r5 = r5 >> 1 */
1241 stw r4, LBLAWAR0(r3) /* LBLAWAR0 <= Flash Size */
1245 stw r4, LBLAWBAR1(r3)
1246 stw r4, LBLAWAR1(r3) /* Off LBIU LAW1 */