2 * (C) Copyright 2000-2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright 2004 Freescale Semiconductor, Inc.
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * 20050101: Eran Liberty (liberty@freescale.com)
28 * Initial file creating (porting from 85XX & 8260)
33 #include <asm/processor.h>
35 /* ----------------------------------------------------------------- */
53 mult_t core_csb_ratio;
57 corecnf_t corecnf_tab[] = {
58 { _byp, _byp}, /* 0x00 */
59 { _byp, _byp}, /* 0x01 */
60 { _byp, _byp}, /* 0x02 */
61 { _byp, _byp}, /* 0x03 */
62 { _byp, _byp}, /* 0x04 */
63 { _byp, _byp}, /* 0x05 */
64 { _byp, _byp}, /* 0x06 */
65 { _byp, _byp}, /* 0x07 */
66 { _1x, _x2}, /* 0x08 */
67 { _1x, _x4}, /* 0x09 */
68 { _1x, _x8}, /* 0x0A */
69 { _1x, _x8}, /* 0x0B */
70 {_1_5x, _x2}, /* 0x0C */
71 {_1_5x, _x4}, /* 0x0D */
72 {_1_5x, _x8}, /* 0x0E */
73 {_1_5x, _x8}, /* 0x0F */
74 { _2x, _x2}, /* 0x10 */
75 { _2x, _x4}, /* 0x11 */
76 { _2x, _x8}, /* 0x12 */
77 { _2x, _x8}, /* 0x13 */
78 {_2_5x, _x2}, /* 0x14 */
79 {_2_5x, _x4}, /* 0x15 */
80 {_2_5x, _x8}, /* 0x16 */
81 {_2_5x, _x8}, /* 0x17 */
82 { _3x, _x2}, /* 0x18 */
83 { _3x, _x4}, /* 0x19 */
84 { _3x, _x8}, /* 0x1A */
85 { _3x, _x8}, /* 0x1B */
88 /* ----------------------------------------------------------------- */
95 DECLARE_GLOBAL_DATA_PTR;
96 volatile immap_t *im = (immap_t *)CFG_IMMRBAR;
101 u32 corecnf_tab_index;
117 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
120 #ifndef CFG_HRCW_HIGH
121 # error "CFG_HRCW_HIGH must be defined in board config file"
122 #endif /* CFG_HCWD_HIGH */
124 #if (CFG_HRCW_HIGH & HRCWH_PCI_HOST)
126 # ifndef CONFIG_83XX_CLKIN
127 # error "In PCI Host Mode, CONFIG_83XX_CLKIN must be defined in board config file"
128 # endif /* CONFIG_83XX_CLKIN */
129 # ifdef CONFIG_83XX_PCICLK
130 # warning "In PCI Host Mode, CONFIG_83XX_PCICLK in board config file is igonred"
131 # endif /* CONFIG_83XX_PCICLK */
134 if (!(im->reset.rcwh & RCWH_PCIHOST)) {
135 /* though RCWH_PCIHOST is defined in CFG_HRCW_HIGH
136 * the im->reset.rcwhr PCI Host Mode is disabled
137 * FIXME: findout if there is a way to issue some warning */
140 if (im->clk.spmr & SPMR_CKID) {
141 /* PCI Clock is half CONFIG_83XX_CLKIN */
142 pci_sync_in = CONFIG_83XX_CLKIN / 2;
145 pci_sync_in = CONFIG_83XX_CLKIN;
148 #else /* (CFG_HRCW_HIGH & HRCWH_PCI_HOST) */
150 # ifdef CONFIG_83XX_CLKIN
151 # warning "In PCI Agent Mode, CONFIG_83XX_CLKIN in board config file is igonred"
152 # endif /* CONFIG_83XX_CLKIN */
153 # ifndef CONFIG_83XX_PCICLK
154 # error "In PCI Agent Mode, CONFIG_83XX_PCICLK must be defined in board config file"
155 # endif /* CONFIG_83XX_PCICLK */
158 if (im->reset.rcwh & RCWH_PCIHOST) {
159 /* though RCWH_PCIHOST is not defined in CFG_HRCW_HIGH
160 * the im->reset.rcwhr PCI Host Mode is enabled */
163 pci_sync_in = CONFIG_83XX_PCICLK;
165 #endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST) */
167 /* we have up to date pci_sync_in */
168 spmf = ((im->reset.rcwl & RCWL_SPMF) >> RCWL_SPMF_SHIFT);
169 clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
171 if ((im->reset.rcwl & RCWL_LBIUCM) || (im->reset.rcwl & RCWL_DDRCM)) {
172 csb_clk = (pci_sync_in * spmf * (1 + clkin_div)) / 2;
175 csb_clk = pci_sync_in * spmf * (1 + clkin_div);
179 switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
187 tsec1_clk = csb_clk / 2;
190 tsec1_clk = csb_clk / 3;
193 /* unkown SCCR_TSEC1CM value */
197 switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
205 tsec2_clk = csb_clk / 2;
208 tsec2_clk = csb_clk / 3;
211 /* unkown SCCR_TSEC2CM value */
216 switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
224 enc_clk = csb_clk / 2;
227 enc_clk = csb_clk / 3;
230 /* unkown SCCR_ENCCM value */
234 switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
239 usbmph_clk = csb_clk;
242 usbmph_clk = csb_clk / 2;
245 usbmph_clk = csb_clk / 3;
248 /* unkown SCCR_USBMPHCM value */
252 switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
260 usbdr_clk = csb_clk / 2;
263 usbdr_clk = csb_clk / 3;
266 /* unkown SCCR_USBDRCM value */
272 && usbmph_clk != usbdr_clk ) {
273 /* if USB MPH clock is not disabled and USB DR clock is not disabled than USB MPH & USB DR must have the same rate */
277 lbiu_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_LBIUCM) >> RCWL_LBIUCM_SHIFT));
278 lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
283 lclk_clk = lbiu_clk / lcrr;
290 ddr_clk = csb_clk * (1 + ((im->reset.rcwl & RCWL_DDRCM) >> RCWL_DDRCM_SHIFT));
292 corepll = (im->reset.rcwl & RCWL_COREPLL) >> RCWL_COREPLL_SHIFT;
293 corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
294 if (corecnf_tab_index > (sizeof(corecnf_tab)/sizeof(corecnf_t)) ) {
295 /* corecnf_tab_index is too high, possibly worng value */
298 switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
305 core_clk = (3 * csb_clk) / 2;
308 core_clk = 2 * csb_clk;
311 core_clk = ( 5 * csb_clk) / 2;
314 core_clk = 3 * csb_clk;
317 /* unkown core to csb ratio */
321 gd->csb_clk = csb_clk ;
322 gd->tsec1_clk = tsec1_clk ;
323 gd->tsec2_clk = tsec2_clk ;
324 gd->core_clk = core_clk ;
325 gd->usbmph_clk = usbmph_clk;
326 gd->usbdr_clk = usbdr_clk ;
327 gd->i2c_clk = i2c_clk ;
328 gd->enc_clk = enc_clk ;
329 gd->lbiu_clk = lbiu_clk ;
330 gd->lclk_clk = lclk_clk ;
331 gd->ddr_clk = ddr_clk ;
333 gd->cpu_clk = gd->core_clk;
334 gd->bus_clk = gd->lbiu_clk;
338 /********************************************
340 * return system bus freq in Hz
341 *********************************************/
342 ulong get_bus_freq (ulong dummy)
344 DECLARE_GLOBAL_DATA_PTR;
348 int print_clock_conf (void)
350 DECLARE_GLOBAL_DATA_PTR;
352 printf("Clock configuration:\n");
353 printf(" Coherent System Bus: %4d MHz\n",gd->csb_clk/1000000);
354 printf(" Core: %4d MHz\n",gd->core_clk/1000000);
355 debug(" Local Bus Controller:%4d MHz\n",gd->lbiu_clk/1000000);
356 printf(" Local Bus: %4d MHz\n",gd->lclk_clk/1000000);
357 debug(" DDR: %4d MHz\n",gd->ddr_clk/1000000);
358 debug(" I2C: %4d MHz\n",gd->i2c_clk/1000000);
359 debug(" TSEC1: %4d MHz\n",gd->tsec1_clk/1000000);
360 debug(" TSEC2: %4d MHz\n",gd->tsec2_clk/1000000);
361 debug(" USB MPH: %4d MHz\n",gd->usbmph_clk/1000000);
362 debug(" USB DR: %4d MHz\n",gd->usbdr_clk/1000000);