2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 DECLARE_GLOBAL_DATA_PTR;
30 extern qe_iop_conf_t qe_iop_conf_tab[];
31 extern void qe_config_iopin(u8 port, u8 pin, int dir,
32 int open_drain, int assign);
33 extern void qe_init(uint qe_base);
34 extern void qe_reset(void);
36 static void config_qe_ioports(void)
39 int dir, open_drain, assign;
42 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
43 port = qe_iop_conf_tab[i].port;
44 pin = qe_iop_conf_tab[i].pin;
45 dir = qe_iop_conf_tab[i].dir;
46 open_drain = qe_iop_conf_tab[i].open_drain;
47 assign = qe_iop_conf_tab[i].assign;
48 qe_config_iopin(port, pin, dir, open_drain, assign);
54 * Breathe some life into the CPU...
56 * Set up the memory map,
57 * initialize a bunch of registers,
58 * initialize the UPM's
60 void cpu_init_f (volatile immap_t * im)
62 /* Pointer is writable since we allocated a register for it */
63 gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
65 /* Clear initial global data */
66 memset ((void *) gd, 0, sizeof (gd_t));
68 /* system performance tweaking */
70 #ifdef CFG_ACR_PIPE_DEP
71 /* Arbiter pipeline depth */
72 im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
73 (CFG_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
77 /* Arbiter repeat count */
78 im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
79 (CFG_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
83 /* Optimize transactions between CSB and other devices */
84 im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
85 (CFG_SPCR_OPT << SPCR_OPT_SHIFT);
88 #ifdef CFG_SPCR_TSECEP
89 /* all eTSEC's Emergency priority */
90 im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) |
91 (CFG_SPCR_TSECEP << SPCR_TSECEP_SHIFT);
94 #ifdef CFG_SPCR_TSEC1EP
95 /* TSEC1 Emergency priority */
96 im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) |
97 (CFG_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
100 #ifdef CFG_SPCR_TSEC2EP
101 /* TSEC2 Emergency priority */
102 im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) |
103 (CFG_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
106 #ifdef CFG_SCCR_ENCCM
107 /* Encryption clock mode */
108 im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) |
109 (CFG_SCCR_ENCCM << SCCR_PCICM_SHIFT);
112 #ifdef CFG_SCCR_PCICM
113 /* PCI & DMA clock mode */
114 im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) |
115 (CFG_SCCR_PCICM << SCCR_PCICM_SHIFT);
118 #ifdef CFG_SCCR_TSECCM
119 /* all TSEC's clock mode */
120 im->clk.sccr = (im->clk.sccr & ~SCCR_TSECCM) |
121 (CFG_SCCR_TSECCM << SCCR_TSECCM_SHIFT);
124 #ifdef CFG_SCCR_TSEC1CM
125 /* TSEC1 clock mode */
126 im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) |
127 (CFG_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
130 #ifdef CFG_SCCR_TSEC2CM
131 /* TSEC2 clock mode */
132 im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) |
133 (CFG_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
136 #ifdef CFG_SCCR_TSEC1ON
137 /* TSEC1 clock switch */
138 im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) |
139 (CFG_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT);
142 #ifdef CFG_SCCR_TSEC2ON
143 /* TSEC2 clock switch */
144 im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) |
145 (CFG_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT);
148 #ifdef CFG_SCCR_USBMPHCM
149 /* USB MPH clock mode */
150 im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) |
151 (CFG_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
154 #ifdef CFG_SCCR_USBDRCM
155 /* USB DR clock mode */
156 im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) |
157 (CFG_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
160 #ifdef CFG_SCCR_SATACM
161 /* SATA controller clock mode */
162 im->clk.sccr = (im->clk.sccr & ~SCCR_SATACM) |
163 (CFG_SCCR_SATACM << SCCR_SATACM_SHIFT);
166 /* RSR - Reset Status Register - clear all status (4.6.1.3) */
167 gd->reset_status = im->reset.rsr;
168 im->reset.rsr = ~(RSR_RES);
170 /* AER - Arbiter Event Register - store status */
171 gd->arbiter_event_attributes = im->arbiter.aeatr;
172 gd->arbiter_event_address = im->arbiter.aeadr;
175 * RMR - Reset Mode Register
176 * contains checkstop reset enable (4.6.1.4)
178 im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT));
180 /* LCRR - Clock Ratio Register (10.3.1.16) */
181 im->lbus.lcrr = CFG_LCRR;
183 /* Enable Time Base & Decrimenter ( so we will have udelay() )*/
184 im->sysconf.spcr |= SPCR_TBEN;
186 /* System General Purpose Register */
188 #if defined(CONFIG_MPC834X) || defined(CONFIG_MPC8313)
189 /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
190 im->sysconf.sicrh = (im->sysconf.sicrh & 0x0000000C) | CFG_SICRH;
192 im->sysconf.sicrh = CFG_SICRH;
196 im->sysconf.sicrl = CFG_SICRL;
198 /* DDR control driver register */
200 im->sysconf.ddrcdr = CFG_DDRCDR;
202 /* Output buffer impedance register */
204 im->sysconf.obir = CFG_OBIR;
208 /* Config QE ioports */
216 /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
217 * addresses - these have to be modified later when FLASH size
218 * has been determined
221 #if defined(CFG_BR0_PRELIM) \
222 && defined(CFG_OR0_PRELIM) \
223 && defined(CFG_LBLAWBAR0_PRELIM) \
224 && defined(CFG_LBLAWAR0_PRELIM)
225 im->lbus.bank[0].br = CFG_BR0_PRELIM;
226 im->lbus.bank[0].or = CFG_OR0_PRELIM;
227 im->sysconf.lblaw[0].bar = CFG_LBLAWBAR0_PRELIM;
228 im->sysconf.lblaw[0].ar = CFG_LBLAWAR0_PRELIM;
230 #error CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined
233 #if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
234 im->lbus.bank[1].br = CFG_BR1_PRELIM;
235 im->lbus.bank[1].or = CFG_OR1_PRELIM;
237 #if defined(CFG_LBLAWBAR1_PRELIM) && defined(CFG_LBLAWAR1_PRELIM)
238 im->sysconf.lblaw[1].bar = CFG_LBLAWBAR1_PRELIM;
239 im->sysconf.lblaw[1].ar = CFG_LBLAWAR1_PRELIM;
241 #if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
242 im->lbus.bank[2].br = CFG_BR2_PRELIM;
243 im->lbus.bank[2].or = CFG_OR2_PRELIM;
245 #if defined(CFG_LBLAWBAR2_PRELIM) && defined(CFG_LBLAWAR2_PRELIM)
246 im->sysconf.lblaw[2].bar = CFG_LBLAWBAR2_PRELIM;
247 im->sysconf.lblaw[2].ar = CFG_LBLAWAR2_PRELIM;
249 #if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
250 im->lbus.bank[3].br = CFG_BR3_PRELIM;
251 im->lbus.bank[3].or = CFG_OR3_PRELIM;
253 #if defined(CFG_LBLAWBAR3_PRELIM) && defined(CFG_LBLAWAR3_PRELIM)
254 im->sysconf.lblaw[3].bar = CFG_LBLAWBAR3_PRELIM;
255 im->sysconf.lblaw[3].ar = CFG_LBLAWAR3_PRELIM;
257 #if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
258 im->lbus.bank[4].br = CFG_BR4_PRELIM;
259 im->lbus.bank[4].or = CFG_OR4_PRELIM;
261 #if defined(CFG_LBLAWBAR4_PRELIM) && defined(CFG_LBLAWAR4_PRELIM)
262 im->sysconf.lblaw[4].bar = CFG_LBLAWBAR4_PRELIM;
263 im->sysconf.lblaw[4].ar = CFG_LBLAWAR4_PRELIM;
265 #if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
266 im->lbus.bank[5].br = CFG_BR5_PRELIM;
267 im->lbus.bank[5].or = CFG_OR5_PRELIM;
269 #if defined(CFG_LBLAWBAR5_PRELIM) && defined(CFG_LBLAWAR5_PRELIM)
270 im->sysconf.lblaw[5].bar = CFG_LBLAWBAR5_PRELIM;
271 im->sysconf.lblaw[5].ar = CFG_LBLAWAR5_PRELIM;
273 #if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
274 im->lbus.bank[6].br = CFG_BR6_PRELIM;
275 im->lbus.bank[6].or = CFG_OR6_PRELIM;
277 #if defined(CFG_LBLAWBAR6_PRELIM) && defined(CFG_LBLAWAR6_PRELIM)
278 im->sysconf.lblaw[6].bar = CFG_LBLAWBAR6_PRELIM;
279 im->sysconf.lblaw[6].ar = CFG_LBLAWAR6_PRELIM;
281 #if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
282 im->lbus.bank[7].br = CFG_BR7_PRELIM;
283 im->lbus.bank[7].or = CFG_OR7_PRELIM;
285 #if defined(CFG_LBLAWBAR7_PRELIM) && defined(CFG_LBLAWAR7_PRELIM)
286 im->sysconf.lblaw[7].bar = CFG_LBLAWBAR7_PRELIM;
287 im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM;
289 #ifdef CFG_GPIO1_PRELIM
290 im->gpio[0].dat = CFG_GPIO1_DAT;
291 im->gpio[0].dir = CFG_GPIO1_DIR;
293 #ifdef CFG_GPIO2_PRELIM
294 im->gpio[1].dat = CFG_GPIO2_DAT;
295 im->gpio[1].dir = CFG_GPIO2_DIR;
299 int cpu_init_r (void)
302 uint qe_base = CFG_IMMR + 0x00100000; /* QE immr base */
310 * Print out the bus arbiter event
312 #if defined(CONFIG_DISPLAY_AER_FULL)
313 static int print_83xx_arb_event(int force)
315 static char* event[] = {
318 "Address Only Transfer Type",
319 "External Control Word Transfer Type",
320 "Reserved Transfer Type",
325 static char* master[] = {
326 "e300 Core Data Transaction",
328 "e300 Core Instruction Fetch",
335 "I2C Boot Sequencer",
359 static char *transfer[] = {
360 "Address-only, Clean Block",
361 "Address-only, lwarx reservation set",
362 "Single-beat or Burst write",
364 "Address-only, Flush Block",
368 "Address-only, sync",
369 "Address-only, tlbsync",
370 "Single-beat or Burst read",
371 "Single-beat or Burst read",
372 "Address-only, Kill Block",
373 "Address-only, icbi",
376 "Address-only, eieio",
380 "ecowx - Illegal single-beat write",
384 "Address-only, TLB Invalidate",
386 "Single-beat or Burst read",
388 "eciwx - Illegal single-beat read",
394 int etype = (gd->arbiter_event_attributes & AEATR_EVENT)
395 >> AEATR_EVENT_SHIFT;
396 int mstr_id = (gd->arbiter_event_attributes & AEATR_MSTR_ID)
397 >> AEATR_MSTR_ID_SHIFT;
398 int tbst = (gd->arbiter_event_attributes & AEATR_TBST)
400 int tsize = (gd->arbiter_event_attributes & AEATR_TSIZE)
401 >> AEATR_TSIZE_SHIFT;
402 int ttype = (gd->arbiter_event_attributes & AEATR_TTYPE)
403 >> AEATR_TTYPE_SHIFT;
405 if (!force && !gd->arbiter_event_address)
408 puts("Arbiter Event Status:\n");
409 printf(" Event Address: 0x%08lX\n", gd->arbiter_event_address);
410 printf(" Event Type: 0x%1x = %s\n", etype, event[etype]);
411 printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]);
412 printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize,
413 tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
414 printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
416 return gd->arbiter_event_address;
419 #elif defined(CONFIG_DISPLAY_AER_BRIEF)
421 static int print_83xx_arb_event(int force)
423 if (!force && !gd->arbiter_event_address)
426 printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
427 gd->arbiter_event_attributes, gd->arbiter_event_address);
429 return gd->arbiter_event_address;
431 #endif /* CONFIG_DISPLAY_AER_xxxx */
434 * Figure out the cause of the reset
436 int prt_83xx_rsr(void)
443 RSR_SWSR, "Software Soft"}, {
444 RSR_SWHR, "Software Hard"}, {
445 RSR_JSRS, "JTAG Soft"}, {
446 RSR_CSHR, "Check Stop"}, {
447 RSR_SWRS, "Software Watchdog"}, {
448 RSR_BMRS, "Bus Monitor"}, {
449 RSR_SRS, "External/Internal Soft"}, {
450 RSR_HRS, "External/Internal Hard"}
452 static int n = sizeof bits / sizeof bits[0];
453 ulong rsr = gd->reset_status;
457 puts("Reset Status:");
460 for (i = 0; i < n; i++)
461 if (rsr & bits[i].mask) {
462 printf("%s%s", sep, bits[i].desc);
467 #if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
468 print_83xx_arb_event(rsr & RSR_BMRS);