2 * Copyright 2004 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * 20050101: Eran Liberty (liberty@freescale.com)
25 * Initial file creating (porting from 85XX & 8260)
29 * CPU specific code for the MPC83xx family.
31 * Derived from the MPC8260 and MPC85xx.
39 #include <asm/processor.h>
44 DECLARE_GLOBAL_DATA_PTR;
45 ulong clock = gd->cpu_clk;
49 if ((pvr & 0xFFFF0000) != PVR_83xx) {
50 puts("Not MPC83xx Family!!!\n");
54 puts("CPU: MPC83xx, ");
61 puts("Rev: Unknown\n");
62 return -1; /* Not sure what this is */
64 printf("Rev: %d.%d at %s MHz\n", (pvr & 0xf0) >> 4,
65 (pvr & 0x0f), strmhz(buf, clock));
71 void upmconfig (uint upm, uint *table, uint size)
73 hang(); /* FIXME: upconfig() needed? */
78 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
85 volatile immap_t *immap = (immap_t *) CFG_IMMRBAR;
88 /* Interrupts and MMU off */
89 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
91 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
92 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
94 /* enable Reset Control Reg */
95 immap->reset.rpr = 0x52535445;
97 /* confirm Reset Control Reg is enabled */
98 while(!((immap->reset.rcer) & RCER_CRE));
100 printf("Resetting the board.");
105 /* perform reset, only one bit */
106 immap->reset.rcr = RCR_SWHR;
108 #else /* ! MPC83xx_RESET */
110 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
112 /* Interrupts and MMU off */
113 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
115 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
116 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
119 * Trying to execute the next instruction at a non-existing address
120 * should cause a machine check, resulting in reset
122 addr = CFG_RESET_ADDRESS;
124 printf("resetting the board.");
126 ((void (*)(void)) addr) ();
127 #endif /* MPC83xx_RESET */
134 * Get timebase clock frequency (like cpu_clk in Hz)
137 unsigned long get_tbclk(void)
139 DECLARE_GLOBAL_DATA_PTR;
143 tbclk = (gd->bus_clk + 3L) / 4L;
149 #if defined(CONFIG_WATCHDOG)
150 void watchdog_reset (void)
152 hang(); /* FIXME: implement watchdog_reset()? */
154 #endif /* CONFIG_WATCHDOG */
156 #if defined(CONFIG_OF_FLAT_TREE)
158 ft_cpu_setup(void *blob, bd_t *bd)
164 clock = bd->bi_busfreq;
165 p = ft_get_prop(blob, "/cpus/" OF_CPU "/bus-frequency", &len);
167 *p = cpu_to_be32(clock);
169 p = ft_get_prop(blob, "/" OF_SOC "/bus-frequency", &len);
171 *p = cpu_to_be32(clock);
173 p = ft_get_prop(blob, "/" OF_SOC "/serial@4500/clock-frequency", &len);
175 *p = cpu_to_be32(clock);
177 p = ft_get_prop(blob, "/" OF_SOC "/serial@4600/clock-frequency", &len);
179 *p = cpu_to_be32(clock);
181 #ifdef CONFIG_MPC83XX_TSEC1
182 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/address", &len);
183 memcpy(p, bd->bi_enetaddr, 6);
186 #ifdef CONFIG_MPC83XX_TSEC2
187 p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/address", &len);
188 memcpy(p, bd->bi_enet1addr, 6);