2 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * CPU specific code for the MPC83xx family.
26 * Derived from the MPC8260 and MPC85xx.
33 #include <asm/processor.h>
37 #include <fsl_esdhc.h>
38 #ifdef CONFIG_BOOTCOUNT_LIMIT
39 #include <asm/immap_qe.h>
43 DECLARE_GLOBAL_DATA_PTR;
47 volatile immap_t *immr;
48 ulong clock = gd->cpu_clk;
54 const struct cpu_type {
57 } cpu_type_list [] = {
65 CPU_TYPE_ENTRY(8347_TBGA_),
66 CPU_TYPE_ENTRY(8347_PBGA_),
68 CPU_TYPE_ENTRY(8358_TBGA_),
69 CPU_TYPE_ENTRY(8358_PBGA_),
76 immr = (immap_t *)CONFIG_SYS_IMMR;
80 switch (pvr & 0xffff0000) {
98 printf("Unknown core, ");
101 spridr = immr->sysconf.spridr;
103 for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
104 if (cpu_type_list[i].partid == PARTID_NO_E(spridr)) {
106 puts(cpu_type_list[i].name);
107 if (IS_E_PROCESSOR(spridr))
109 if (REVID_MAJOR(spridr) >= 2)
111 printf(", Rev: %d.%d", REVID_MAJOR(spridr),
112 REVID_MINOR(spridr));
116 if (i == ARRAY_SIZE(cpu_type_list))
117 printf("(SPRIDR %08x unknown), ", spridr);
119 printf(" at %s MHz, ", strmhz(buf, clock));
121 printf("CSB: %s MHz\n", strmhz(buf, gd->csb_clk));
128 * Program a UPM with the code supplied in the table.
130 * The 'dummy' variable is used to increment the MAD. 'dummy' is
131 * supposed to be a pointer to the memory of the device being
132 * programmed by the UPM. The data in the MDR is written into
133 * memory and the MAD is incremented every time there's a write
134 * to 'dummy'. Unfortunately, the current prototype for this
135 * function doesn't allow for passing the address of this
136 * device, and changing the prototype will break a number lots
137 * of other code, so we need to use a round-about way of finding
138 * the value for 'dummy'.
140 * The value can be extracted from the base address bits of the
141 * Base Register (BR) associated with the specific UPM. To find
142 * that BR, we need to scan all 8 BRs until we find the one that
143 * has its MSEL bits matching the UPM we want. Once we know the
144 * right BR, we can extract the base address bits from it.
146 * The MxMR and the BR and OR of the chosen bank should all be
147 * configured before calling this function.
150 * upm: 0=UPMA, 1=UPMB, 2=UPMC
151 * table: Pointer to an array of values to program
152 * size: Number of elements in the array. Must be 64 or less.
154 void upmconfig (uint upm, uint *table, uint size)
156 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
157 volatile fsl_lbus_t *lbus = &immap->lbus;
158 volatile uchar *dummy = NULL;
159 const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
160 volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
163 /* Scan all the banks to determine the base address of the device */
164 for (i = 0; i < 8; i++) {
165 if ((lbus->bank[i].br & BR_MSEL) == msel) {
166 dummy = (uchar *) (lbus->bank[i].br & BR_BA);
172 printf("Error: %s() could not find matching BR\n", __FUNCTION__);
176 /* Set the OP field in the MxMR to "write" and the MAD field to 000000 */
177 *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
179 for (i = 0; i < size; i++) {
180 lbus->mdr = table[i];
181 __asm__ __volatile__ ("sync");
182 *dummy = 0; /* Write the value to memory and increment MAD */
183 __asm__ __volatile__ ("sync");
184 while(((*mxmr & 0x3f) != ((i + 1) & 0x3f)));
187 /* Set the OP field in the MxMR to "normal" and the MAD field to 000000 */
193 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
196 #ifndef MPC83xx_RESET
200 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
203 /* Interrupts and MMU off */
204 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
206 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
207 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
209 /* enable Reset Control Reg */
210 immap->reset.rpr = 0x52535445;
211 __asm__ __volatile__ ("sync");
212 __asm__ __volatile__ ("isync");
214 /* confirm Reset Control Reg is enabled */
215 while(!((immap->reset.rcer) & RCER_CRE));
217 printf("Resetting the board.");
222 /* perform reset, only one bit */
223 immap->reset.rcr = RCR_SWHR;
225 #else /* ! MPC83xx_RESET */
227 immap->reset.rmr = RMR_CSRE; /* Checkstop Reset enable */
229 /* Interrupts and MMU off */
230 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
232 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
233 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
236 * Trying to execute the next instruction at a non-existing address
237 * should cause a machine check, resulting in reset
239 addr = CONFIG_SYS_RESET_ADDRESS;
241 printf("resetting the board.");
243 ((void (*)(void)) addr) ();
244 #endif /* MPC83xx_RESET */
251 * Get timebase clock frequency (like cpu_clk in Hz)
254 unsigned long get_tbclk(void)
258 tbclk = (gd->bus_clk + 3L) / 4L;
264 #if defined(CONFIG_WATCHDOG)
265 void watchdog_reset (void)
267 int re_enable = disable_interrupts();
269 /* Reset the 83xx watchdog */
270 volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
271 immr->wdt.swsrr = 0x556c;
272 immr->wdt.swsrr = 0xaa39;
275 enable_interrupts ();
279 #if defined(CONFIG_DDR_ECC)
282 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
283 volatile dma83xx_t *dma = &immap->dma;
284 volatile u32 status = swab32(dma->dmasr0);
285 volatile u32 dmamr0 = swab32(dma->dmamr0);
289 /* initialize DMASARn, DMADAR and DMAABCRn */
290 dma->dmadar0 = (u32)0;
291 dma->dmasar0 = (u32)0;
294 __asm__ __volatile__ ("sync");
295 __asm__ __volatile__ ("isync");
298 dmamr0 &= ~DMA_CHANNEL_START;
299 dma->dmamr0 = swab32(dmamr0);
300 __asm__ __volatile__ ("sync");
301 __asm__ __volatile__ ("isync");
303 /* while the channel is busy, spin */
304 while(status & DMA_CHANNEL_BUSY) {
305 status = swab32(dma->dmasr0);
308 debug("DMA-init end\n");
313 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
314 volatile dma83xx_t *dma = &immap->dma;
315 volatile u32 status = swab32(dma->dmasr0);
316 volatile u32 byte_count = swab32(dma->dmabcr0);
318 /* while the channel is busy, spin */
319 while (status & DMA_CHANNEL_BUSY) {
320 status = swab32(dma->dmasr0);
323 if (status & DMA_CHANNEL_TRANSFER_ERROR) {
324 printf ("DMA Error: status = %x @ %d\n", status, byte_count);
330 int dma_xfer(void *dest, u32 count, void *src)
332 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
333 volatile dma83xx_t *dma = &immap->dma;
336 /* initialize DMASARn, DMADAR and DMAABCRn */
337 dma->dmadar0 = swab32((u32)dest);
338 dma->dmasar0 = swab32((u32)src);
339 dma->dmabcr0 = swab32(count);
341 __asm__ __volatile__ ("sync");
342 __asm__ __volatile__ ("isync");
344 /* init direct transfer, clear CS bit */
345 dmamr0 = (DMA_CHANNEL_TRANSFER_MODE_DIRECT |
346 DMA_CHANNEL_SOURCE_ADDRESS_HOLD_8B |
347 DMA_CHANNEL_SOURCE_ADRESSS_HOLD_EN);
349 dma->dmamr0 = swab32(dmamr0);
351 __asm__ __volatile__ ("sync");
352 __asm__ __volatile__ ("isync");
354 /* set CS to start DMA transfer */
355 dmamr0 |= DMA_CHANNEL_START;
356 dma->dmamr0 = swab32(dmamr0);
357 __asm__ __volatile__ ("sync");
358 __asm__ __volatile__ ("isync");
360 return ((int)dma_check());
362 #endif /*CONFIG_DDR_ECC*/
365 * Initializes on-chip ethernet controllers.
366 * to override, implement board_eth_init()
368 int cpu_eth_init(bd_t *bis)
370 #if defined(CONFIG_UEC_ETH1)
373 #if defined(CONFIG_UEC_ETH2)
376 #if defined(CONFIG_UEC_ETH3)
379 #if defined(CONFIG_UEC_ETH4)
382 #if defined(CONFIG_UEC_ETH5)
385 #if defined(CONFIG_UEC_ETH6)
388 #if defined(CONFIG_TSEC_ENET)
389 tsec_standard_init(bis);
395 * Initializes on-chip MMC controllers.
396 * to override, implement board_mmc_init()
398 int cpu_mmc_init(bd_t *bis)
400 #ifdef CONFIG_FSL_ESDHC
401 return fsl_esdhc_mmc_init(bis);
407 #ifdef CONFIG_BOOTCOUNT_LIMIT
409 #if !defined(CONFIG_MPC8360)
410 #error "CONFIG_BOOTCOUNT_LIMIT only for MPC8360 implemented"
413 #if !defined(CONFIG_BOOTCOUNT_ADDR)
414 #define CONFIG_BOOTCOUNT_ADDR (0x110000 + QE_MURAM_SIZE - 2 * sizeof(unsigned long))
419 void bootcount_store (ulong a)
421 void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR);
423 out_be32 (reg + 4, BOOTCOUNT_MAGIC);
426 ulong bootcount_load (void)
428 void *reg = (void *)(CONFIG_SYS_IMMR + CONFIG_BOOTCOUNT_ADDR);
430 if (in_be32 (reg + 4) != BOOTCOUNT_MAGIC)
433 return in_be32 (reg);
435 #endif /* CONFIG_BOOTCOUNT_LIMIT */