3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (c) 2005 MontaVista Software, Inc.
6 * Vitaly Bordug <vbordug@ru.mvista.com>
7 * Added support for PCI bridge on MPC8272ADS
9 * See file CREDITS for list of people who contributed to this
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
34 #include <asm/m8260_pci.h>
37 * Local->PCI map (from CPU) controlled by
38 * MPC826x master window
40 * 0x80000000 - 0xBFFFFFFF CPU2PCI space PCIBR0
41 * 0xF4000000 - 0xF7FFFFFF CPU2PCI space PCIBR1
43 * 0x80000000 - 0x9FFFFFFF 0x80000000 - 0x9FFFFFFF (Outbound ATU #1)
44 * PCI Mem with prefetch
46 * 0xA0000000 - 0xBFFFFFFF 0xA0000000 - 0xBFFFFFFF (Outbound ATU #2)
47 * PCI Mem w/o prefetch
49 * 0xF4000000 - 0xF7FFFFFF 0x00000000 - 0x03FFFFFF (Outbound ATU #3)
52 * PCI->Local map (from PCI)
53 * MPC826x slave window controlled by
55 * 0x00000000 - 0x1FFFFFFF 0x00000000 - 0x1FFFFFFF (Inbound ATU #1)
56 * MPC826x local memory
60 * Slave window that allows PCI masters to access MPC826x local memory.
61 * This window is set up using the first set of Inbound ATU registers
64 #ifndef CFG_PCI_SLV_MEM_LOCAL
65 #define PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */
67 #define PCI_SLV_MEM_LOCAL CFG_PCI_SLV_MEM_LOCAL
70 #ifndef CFG_PCI_SLV_MEM_BUS
71 #define PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
73 #define PCI_SLV_MEM_BUS CFG_PCI_SLV_MEM_BUS
76 #ifndef CFG_PICMR0_MASK_ATTRIB
77 #define PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
80 #define PICMR0_MASK_ATTRIB CFG_PICMR0_MASK_ATTRIB
84 * These are the windows that allow the CPU to access PCI address space.
85 * All three PCI master windows, which allow the CPU to access PCI
86 * prefetch, non prefetch, and IO space (see below), must all fit within
91 #ifndef CFG_PCI_MSTR0_LOCAL
92 #define PCI_MSTR0_LOCAL 0x80000000 /* Local base */
94 #define PCI_MSTR0_LOCAL CFG_PCI_MSTR0_LOCAL
97 #ifndef CFG_PCIMSK0_MASK
98 #define PCIMSK0_MASK PCIMSK_1GB /* Size of window */
100 #define PCIMSK0_MASK CFG_PCIMSK0_MASK
104 #ifndef CFG_PCI_MSTR1_LOCAL
105 #define PCI_MSTR1_LOCAL 0xF4000000 /* Local base */
107 #define PCI_MSTR1_LOCAL CFG_PCI_MSTR1_LOCAL
110 #ifndef CFG_PCIMSK1_MASK
111 #define PCIMSK1_MASK PCIMSK_64MB /* Size of window */
113 #define PCIMSK1_MASK CFG_PCIMSK1_MASK
117 * Master window that allows the CPU to access PCI Memory (prefetch).
118 * This window will be setup with the first set of Outbound ATU registers
122 #ifndef CFG_PCI_MSTR_MEM_LOCAL
123 #define PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
125 #define PCI_MSTR_MEM_LOCAL CFG_PCI_MSTR_MEM_LOCAL
128 #ifndef CFG_PCI_MSTR_MEM_BUS
129 #define PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
131 #define PCI_MSTR_MEM_BUS CFG_PCI_MSTR_MEM_BUS
134 #ifndef CFG_CPU_PCI_MEM_START
135 #define CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
137 #define CPU_PCI_MEM_START CFG_CPU_PCI_MEM_START
140 #ifndef CFG_PCI_MSTR_MEM_SIZE
141 #define PCI_MSTR_MEM_SIZE 0x10000000 /* 256MB */
143 #define PCI_MSTR_MEM_SIZE CFG_PCI_MSTR_MEM_SIZE
146 #ifndef CFG_POCMR0_MASK_ATTRIB
147 #define POCMR0_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
149 #define POCMR0_MASK_ATTRIB CFG_POCMR0_MASK_ATTRIB
153 * Master window that allows the CPU to access PCI Memory (non-prefetch).
154 * This window will be setup with the second set of Outbound ATU registers
158 #ifndef CFG_PCI_MSTR_MEMIO_LOCAL
159 #define PCI_MSTR_MEMIO_LOCAL 0x90000000 /* Local base */
161 #define PCI_MSTR_MEMIO_LOCAL CFG_PCI_MSTR_MEMIO_LOCAL
164 #ifndef CFG_PCI_MSTR_MEMIO_BUS
165 #define PCI_MSTR_MEMIO_BUS 0x90000000 /* PCI base */
167 #define PCI_MSTR_MEMIO_BUS CFG_PCI_MSTR_MEMIO_BUS
170 #ifndef CFG_CPU_PCI_MEMIO_START
171 #define CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
173 #define CPU_PCI_MEMIO_START CFG_CPU_PCI_MEMIO_START
176 #ifndef CFG_PCI_MSTR_MEMIO_SIZE
177 #define PCI_MSTR_MEMIO_SIZE 0x10000000 /* 256 MB */
179 #define PCI_MSTR_MEMIO_SIZE CFG_PCI_MSTR_MEMIO_SIZE
182 #ifndef CFG_POCMR1_MASK_ATTRIB
183 #define POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
185 #define POCMR1_MASK_ATTRIB CFG_POCMR1_MASK_ATTRIB
189 * Master window that allows the CPU to access PCI IO space.
190 * This window will be setup with the third set of Outbound ATU registers
194 #ifndef CFG_PCI_MSTR_IO_LOCAL
195 #define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */
197 #define PCI_MSTR_IO_LOCAL CFG_PCI_MSTR_IO_LOCAL
200 #ifndef CFG_PCI_MSTR_IO_BUS
201 #define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */
203 #define PCI_MSTR_IO_BUS CFG_PCI_MSTR_IO_BUS
206 #ifndef CFG_CPU_PCI_IO_START
207 #define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
209 #define CPU_PCI_IO_START CFG_CPU_PCI_IO_START
212 #ifndef CFG_PCI_MSTR_IO_SIZE
213 #define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */
215 #define PCI_MSTR_IO_SIZE CFG_PCI_MSTR_IO_SIZE
218 #ifndef CFG_POCMR2_MASK_ATTRIB
219 #define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
221 #define POCMR2_MASK_ATTRIB CFG_POCMR2_MASK_ATTRIB
224 /* PCI bus configuration registers.
227 #define PCI_CLASS_BRIDGE_CTLR 0x06
230 static inline void pci_outl (u32 addr, u32 data)
232 *(volatile u32 *) addr = cpu_to_le32 (data);
235 void pci_mpc8250_init (struct pci_controller *hose)
237 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
238 DECLARE_GLOBAL_DATA_PTR;
242 volatile immap_t *immap = (immap_t *) CFG_IMMR;
243 pci_dev_t host_devno = PCI_BDF (0, 0, 0);
245 pci_setup_indirect (hose, CFG_IMMR + PCI_CFG_ADDR_REG,
246 CFG_IMMR + PCI_CFG_DATA_REG);
249 * Setting required to enable local bus for PCI (SIUMCR [LBPC]).
251 #ifdef CONFIG_MPC8266ADS
252 immap->im_siu_conf.sc_siumcr =
253 (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
255 #elif defined CONFIG_MPC8272
256 immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
278 * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]),
279 * and local bus for PCI (SIUMCR [LBPC]).
281 immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
290 /* Make PCI lowest priority */
291 /* Each 4 bits is a device bus request and the MS 4bits
292 is highest priority */
302 External Master 1 0b0111
303 External Master 2 0b1000
304 External Master 3 0b1001
305 The rest are reserved */
306 immap->im_siu_conf.sc_ppc_alrh = 0x61207893;
308 /* Park bus on core while modifying PCI Bus accesses */
309 immap->im_siu_conf.sc_ppc_acr = 0x6;
312 * Set up master windows that allow the CPU to access PCI space. These
313 * windows are set up using the two SIU PCIBR registers.
315 immap->im_memctl.memc_pcimsk0 = PCIMSK0_MASK;
316 immap->im_memctl.memc_pcibr0 = PCI_MSTR0_LOCAL | PCIBR_ENABLE;
318 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
319 immap->im_memctl.memc_pcimsk1 = PCIMSK1_MASK;
320 immap->im_memctl.memc_pcibr1 = PCI_MSTR1_LOCAL | PCIBR_ENABLE;
323 /* Release PCI RST (by default the PCI RST signal is held low) */
324 immap->im_pci.pci_gcr = cpu_to_le32 (PCIGCR_PCI_BUS_EN);
326 /* give it some time */
328 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
329 /* Give the PCI cards more time to initialize before query
330 This might be good for other boards also
334 for (i = 0; i < 1000; ++i)
340 * Set up master window that allows the CPU to access PCI Memory (prefetch)
341 * space. This window is set up using the first set of Outbound ATU registers.
343 immap->im_pci.pci_potar0 = cpu_to_le32 (PCI_MSTR_MEM_BUS >> 12); /* PCI base */
344 immap->im_pci.pci_pobar0 = cpu_to_le32 (PCI_MSTR_MEM_LOCAL >> 12); /* Local base */
345 immap->im_pci.pci_pocmr0 = cpu_to_le32 (POCMR0_MASK_ATTRIB); /* Size & attribute */
348 * Set up master window that allows the CPU to access PCI Memory (non-prefetch)
349 * space. This window is set up using the second set of Outbound ATU registers.
351 immap->im_pci.pci_potar1 = cpu_to_le32 (PCI_MSTR_MEMIO_BUS >> 12); /* PCI base */
352 immap->im_pci.pci_pobar1 = cpu_to_le32 (PCI_MSTR_MEMIO_LOCAL >> 12); /* Local base */
353 immap->im_pci.pci_pocmr1 = cpu_to_le32 (POCMR1_MASK_ATTRIB); /* Size & attribute */
356 * Set up master window that allows the CPU to access PCI IO space. This window
357 * is set up using the third set of Outbound ATU registers.
359 immap->im_pci.pci_potar2 = cpu_to_le32 (PCI_MSTR_IO_BUS >> 12); /* PCI base */
360 immap->im_pci.pci_pobar2 = cpu_to_le32 (PCI_MSTR_IO_LOCAL >> 12); /* Local base */
361 immap->im_pci.pci_pocmr2 = cpu_to_le32 (POCMR2_MASK_ATTRIB); /* Size & attribute */
364 * Set up slave window that allows PCI masters to access MPC826x local memory.
365 * This window is set up using the first set of Inbound ATU registers
367 immap->im_pci.pci_pitar0 = cpu_to_le32 (PCI_SLV_MEM_LOCAL >> 12); /* PCI base */
368 immap->im_pci.pci_pibar0 = cpu_to_le32 (PCI_SLV_MEM_BUS >> 12); /* Local base */
369 immap->im_pci.pci_picmr0 = cpu_to_le32 (PICMR0_MASK_ATTRIB); /* Size & attribute */
371 /* See above for description - puts PCI request as highest priority */
372 #ifdef CONFIG_MPC8272
373 immap->im_siu_conf.sc_ppc_alrh = 0x01236745;
375 immap->im_siu_conf.sc_ppc_alrh = 0x03124567;
378 /* Park the bus on the PCI */
379 immap->im_siu_conf.sc_ppc_acr = PPC_ACR_BUS_PARK_PCI;
381 /* Host mode - specify the bridge as a host-PCI bridge */
383 pci_hose_write_config_byte (hose, host_devno, PCI_CLASS_CODE,
384 PCI_CLASS_BRIDGE_CTLR);
386 /* Enable the host bridge to be a master on the PCI bus, and to act as a PCI memory target */
387 pci_hose_read_config_word (hose, host_devno, PCI_COMMAND, &tempShort);
388 pci_hose_write_config_word (hose, host_devno, PCI_COMMAND,
389 tempShort | PCI_COMMAND_MASTER |
392 /* do some bridge init, should be done on all 8260 based bridges */
393 pci_hose_write_config_byte (hose, host_devno, PCI_CACHE_LINE_SIZE,
395 pci_hose_write_config_byte (hose, host_devno, PCI_LATENCY_TIMER,
398 hose->first_busno = 0;
399 hose->last_busno = 0xff;
401 /* System memory space */
402 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
403 pci_set_region (hose->regions + 0,
406 gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
408 pci_set_region (hose->regions + 0,
411 0x4000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
414 /* PCI memory space */
415 #if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272
416 pci_set_region (hose->regions + 1,
418 PCI_MSTR_MEMIO_LOCAL,
419 PCI_MSTR_MEMIO_SIZE, PCI_REGION_MEM);
421 pci_set_region (hose->regions + 1,
424 PCI_MSTR_MEM_SIZE, PCI_REGION_MEM);
428 pci_set_region (hose->regions + 2,
430 PCI_MSTR_IO_LOCAL, PCI_MSTR_IO_SIZE, PCI_REGION_IO);
432 hose->region_count = 3;
434 pci_register_hose (hose);
435 /* Mask off master abort machine checks */
436 immap->im_pci.pci_emr &= cpu_to_le32 (~PCI_ERROR_PCI_NO_RSP);
439 hose->last_busno = pci_hose_scan (hose);
442 /* clear the error in the error status register */
443 immap->im_pci.pci_esr = cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
445 /* unmask master abort machine checks */
446 immap->im_pci.pci_emr |= cpu_to_le32 (PCI_ERROR_PCI_NO_RSP);
449 #endif /* CONFIG_PCI */