3 * Rob Taylor. Flying Pig Systems. robt@flyingpig.com.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/processor.h>
29 #define CFG_BANK0_ROW 0
32 #define CFG_BANK1_ROW 0
35 #define CFG_BANK2_ROW 0
38 #define CFG_BANK3_ROW 0
41 #define CFG_BANK4_ROW 0
44 #define CFG_BANK5_ROW 0
47 #define CFG_BANK6_ROW 0
50 #define CFG_BANK7_ROW 0
52 #ifndef CFG_DBUS_SIZE2
53 #define CFG_DBUS_SIZE2 0
57 * Breath some life into the CPU...
59 * Set up the memory map,
60 * initialize a bunch of registers,
65 /* MOUSSE board is initialized in asm */
66 #if !defined(CONFIG_MOUSSE) && !defined(CONFIG_BMW)
67 register unsigned long val;
68 CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
69 /* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
71 #if defined(CONFIG_MUSENKI) || defined(CONFIG_PN62)
72 /* Why is this here, you ask? Try, just try setting 0x8000
73 * in PCIACR with CONFIG_WRITE_HALFWORD()
74 * this one was a stumper, and we are annoyed
77 #define M_CONFIG_WRITE_HALFWORD( addr, data ) \
78 __asm__ __volatile__(" \
85 : "r" (CONFIG_ADDR), "r" (CONFIG_DATA), \
86 "r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16)) \
89 M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000);
92 CONFIG_WRITE_BYTE(PCLSR, 0x8); /* set PCI cache line size */
95 * Note that although this bit is cleared after a hard reset, it
96 * must be explicitly set and then cleared by software during
97 * initialization in order to guarantee correct operation of the
98 * DLL and the SDRAM_CLK[0:3] signals (if they are used).
100 CONFIG_READ_BYTE (AMBOR, val);
101 CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
102 CONFIG_WRITE_BYTE(AMBOR, val | 0x20);
103 CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
104 #ifdef CONFIG_MPC8245
105 /* silicon bug 28 MPC8245 */
106 CONFIG_READ_BYTE(AMBOR,val);
107 CONFIG_WRITE_BYTE(AMBOR,val|0x1);
109 CONFIG_READ_BYTE(PCMBCR,val);
110 /* in order not to corrupt data which is being read over the PCI bus
111 * with the PPC as master, we need to reduce the number of PCMRBs to 1,
112 * 4.11 in the processor user manual
116 CONFIG_WRITE_BYTE(PCMBCR,(val|0xC0)); /* 1 PCMRB */
118 CONFIG_WRITE_BYTE(PCMBCR,(val|0x80)); /* 2 PCMRBs */
119 CONFIG_WRITE_BYTE(PCMBCR,(val|0x40)); /* 3 PCMRBs */
123 CONFIG_READ_WORD(PICR1, val);
124 #if defined(CONFIG_MPC8240)
125 CONFIG_WRITE_WORD( PICR1,
126 (val & (PICR1_ADDRESS_MAP | PICR1_RCS0)) |
127 PIRC1_MSK | PICR1_PROC_TYPE_603E |
128 PICR1_FLASH_WR_EN | PICR1_MCP_EN |
129 PICR1_CF_DPARK | PICR1_EN_PCS |
131 #elif defined(CONFIG_MPC8245)
132 CONFIG_WRITE_WORD( PICR1,
133 (val & (PICR1_RCS0)) |
134 PICR1_PROC_TYPE_603E |
135 PICR1_FLASH_WR_EN | PICR1_MCP_EN |
136 PICR1_CF_DPARK | PICR1_NO_BUSW_CK |
137 PICR1_DEC| PICR1_CF_APARK | 0x10); /* 8245 UM says bit 4 must be set */
139 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
142 CONFIG_READ_WORD(PICR2, val);
143 val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/
145 val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/
147 CONFIG_WRITE_WORD(PICR2, val);
149 CONFIG_WRITE_WORD(EUMBBAR, CFG_EUMB_ADDR);
151 CONFIG_WRITE_WORD(MCCR1, (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) |
153 (CFG_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) |
154 (CFG_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) |
155 (CFG_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) |
156 (CFG_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) |
157 (CFG_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) |
158 (CFG_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) |
159 (CFG_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) |
160 (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT));
163 #if defined(CFG_ASRISE) && defined(CFG_ASFALL)
164 CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT |
165 CFG_ASRISE << MCCR2_ASRISE_SHIFT |
166 CFG_ASFALL << MCCR2_ASFALL_SHIFT);
168 CONFIG_WRITE_WORD(MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT);
171 #if defined(CONFIG_MPC8240)
172 CONFIG_WRITE_WORD(MCCR3,
173 (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
174 (CFG_REFREC << MCCR3_REFREC_SHIFT) |
175 (CFG_RDLAT << MCCR3_RDLAT_SHIFT));
176 #elif defined(CONFIG_MPC8245)
177 CONFIG_WRITE_WORD(MCCR3,
178 (((CFG_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
179 (CFG_REFREC << MCCR3_REFREC_SHIFT));
181 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
184 /* this is gross. We think these should all be the same, and various boards
185 * should define CFG_ACTORW to 0 if they don't want to set it, or even, if
186 * its not set, we define it to zero in this file
188 #if defined(CONFIG_CU824) || defined(CONFIG_PN62)
189 CONFIG_WRITE_WORD(MCCR4,
190 (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) |
191 (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
193 (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
194 ((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
195 (((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) |
196 CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) |
197 (CFG_ACTORW << MCCR4_ACTTORW_SHIFT) |
198 (((CFG_BSTOPRE & 0x03c0) >> 6) << MCCR4_BSTOPRE6TO9_SHIFT));
199 #elif defined(CONFIG_MPC8240)
200 CONFIG_WRITE_WORD(MCCR4,
201 (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) |
202 (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
204 (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
205 ((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
206 (((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) |
207 (CFG_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) |
208 (((CFG_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
209 #elif defined(CONFIG_MPC8245)
210 CONFIG_READ_WORD(MCCR1, val);
211 val &= MCCR1_DBUS_SIZE0; /* test for 64-bit mem bus */
213 CONFIG_WRITE_WORD(MCCR4,
214 (CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) |
215 (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
216 (CFG_EXTROM ? MCCR4_EXTROM : 0) |
217 (CFG_REGDIMM ? MCCR4_REGDIMM : 0) |
218 (CFG_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
219 ((CFG_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
220 (CFG_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) |
221 (((CFG_SDMODE_CAS_LAT <<4) | (CFG_SDMODE_WRAP <<3) |
222 (val ? 2 : 3)) << MCCR4_SDMODE_SHIFT) |
223 (CFG_ACTORW << MCCR4_ACTTORW_SHIFT) |
224 (((CFG_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
226 #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
229 CONFIG_WRITE_WORD(MSAR1,
230 ( (CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
231 (((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
232 (((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
233 (((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
234 CONFIG_WRITE_WORD(EMSAR1,
235 ( (CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
236 (((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
237 (((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
238 (((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
239 CONFIG_WRITE_WORD(MSAR2,
240 ( (CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
241 (((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
242 (((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
243 (((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
244 CONFIG_WRITE_WORD(EMSAR2,
245 ( (CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
246 (((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
247 (((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
248 (((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
249 CONFIG_WRITE_WORD(MEAR1,
250 ( (CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
251 (((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
252 (((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
253 (((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
254 CONFIG_WRITE_WORD(EMEAR1,
255 ( (CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
256 (((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
257 (((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
258 (((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
259 CONFIG_WRITE_WORD(MEAR2,
260 ( (CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
261 (((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
262 (((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
263 (((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
264 CONFIG_WRITE_WORD(EMEAR2,
265 ( (CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
266 (((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
267 (((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
268 (((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
270 CONFIG_WRITE_BYTE(ODCR, CFG_ODCR);
271 #ifdef CFG_DLL_MAX_DELAY
272 CONFIG_WRITE_BYTE(MIOCR1, CFG_DLL_MAX_DELAY); /* needed to make DLL lock */
274 #if defined(CFG_DLL_EXTEND) && defined(CFG_PCI_HOLD_DEL)
275 CONFIG_WRITE_BYTE(PMCR2, CFG_DLL_EXTEND | CFG_PCI_HOLD_DEL);
277 #if defined(MIOCR2) && defined(CFG_SDRAM_DSCD)
278 CONFIG_WRITE_BYTE(MIOCR2, CFG_SDRAM_DSCD); /* change memory input */
279 #endif /* setup & hold time */
281 CONFIG_WRITE_BYTE(MBER,
283 (CFG_BANK1_ENABLE << 1) |
284 (CFG_BANK2_ENABLE << 2) |
285 (CFG_BANK3_ENABLE << 3) |
286 (CFG_BANK4_ENABLE << 4) |
287 (CFG_BANK5_ENABLE << 5) |
288 (CFG_BANK6_ENABLE << 6) |
289 (CFG_BANK7_ENABLE << 7));
292 CONFIG_WRITE_BYTE(MPMR, CFG_PGMAX);
295 /* ! Wait 200us before initialize other registers */
296 /*FIXME: write a decent udelay wait */
297 __asm__ __volatile__(
303 CONFIG_READ_WORD(MCCR1, val);
304 CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */
305 __asm__ __volatile__("eieio");
307 #endif /* !CONFIG_MOUSSE && !CONFIG_BMW */
312 #ifdef INCLUDE_MPC107_REPORT
317 { BMC_BASE + 0x00, "MPC107 Vendor/Device ID" },
318 { BMC_BASE + 0x04, "MPC107 PCI Command/Status Register" },
319 { BMC_BASE + 0x08, "MPC107 Revision" },
320 { BMC_BASE + 0x0C, "MPC107 Cache Line Size" },
321 { BMC_BASE + 0x10, "MPC107 LMBAR" },
322 { BMC_BASE + 0x14, "MPC824x PCSR" },
323 { BMC_BASE + 0xA8, "MPC824x PICR1" },
324 { BMC_BASE + 0xAC, "MPC824x PICR2" },
325 { BMC_BASE + 0x46, "MPC824x PACR" },
326 { BMC_BASE + 0x310, "MPC824x ITWR" },
327 { BMC_BASE + 0x300, "MPC824x OMBAR" },
328 { BMC_BASE + 0x308, "MPC824x OTWR" },
329 { BMC_BASE + 0x14, "MPC107 Peripheral Control and Status Register" },
330 { BMC_BASE + 0x78, "MPC107 EUMBAR" },
331 { BMC_BASE + 0xC0, "MPC107 Processor Bus Error Status" },
332 { BMC_BASE + 0xC4, "MPC107 PCI Bus Error Status" },
333 { BMC_BASE + 0xC8, "MPC107 Processor/PCI Error Address" },
334 { BMC_BASE + 0xE0, "MPC107 AMBOR Register" },
335 { BMC_BASE + 0xF0, "MPC107 MCCR1 Register" },
336 { BMC_BASE + 0xF4, "MPC107 MCCR2 Register" },
337 { BMC_BASE + 0xF8, "MPC107 MCCR3 Register" },
338 { BMC_BASE + 0xFC, "MPC107 MCCR4 Register" },
340 #define N_MPC107_Regs (sizeof(MPC107Regs)/sizeof(MPC107Regs[0]))
341 #endif /* INCLUDE_MPC107_REPORT */
342 #endif /* CONFIG_MOUSSE */
345 * initialize higher level parts of CPU like time base and timers
347 int cpu_init_r (void)
350 #ifdef INCLUDE_MPC107_REPORT
351 unsigned int tmp = 0, i;
354 * Initialize the EUMBBAR (Embedded Util Mem Block Base Addr Reg).
355 * This is necessary before the EPIC, DMA ctlr, I2C ctlr, etc. can
359 #ifdef CONFIG_MPC8240 /* only on MPC8240 */
360 mpc824x_mpc107_setreg (EUMBBAR, EUMBBAR_VAL);
361 /* MOT/SPS: Issue #10002, PCI (FD Alias enable) */
362 mpc824x_mpc107_setreg (AMBOR, 0x000000C0);
366 #ifdef INCLUDE_MPC107_REPORT
367 /* Check MPC824x PCI Device and Vendor ID */
368 while ((tmp = mpc824x_mpc107_getreg (BMC_BASE)) != 0x31057) {
369 printf (" MPC107: offset=0x%x, val = 0x%x\n",
374 for (i = 0; i < N_MPC107_Regs; i++) {
375 printf (" 0x%x/%s = 0x%x\n",
376 MPC107Regs[i].iobase,
378 mpc824x_mpc107_getreg (MPC107Regs[i].iobase));
381 printf ("IBAT0L = 0x%08X\n", mfspr (IBAT0L));
382 printf ("IBAT0U = 0x%08X\n", mfspr (IBAT0U));
383 printf ("IBAT1L = 0x%08X\n", mfspr (IBAT1L));
384 printf ("IBAT1U = 0x%08X\n", mfspr (IBAT1U));
385 printf ("IBAT2L = 0x%08X\n", mfspr (IBAT2L));
386 printf ("IBAT2U = 0x%08X\n", mfspr (IBAT2U));
387 printf ("IBAT3L = 0x%08X\n", mfspr (IBAT3L));
388 printf ("IBAT3U = 0x%08X\n", mfspr (IBAT3U));
389 printf ("DBAT0L = 0x%08X\n", mfspr (DBAT0L));
390 printf ("DBAT0U = 0x%08X\n", mfspr (DBAT0U));
391 printf ("DBAT1L = 0x%08X\n", mfspr (DBAT1L));
392 printf ("DBAT1U = 0x%08X\n", mfspr (DBAT1U));
393 printf ("DBAT2L = 0x%08X\n", mfspr (DBAT2L));
394 printf ("DBAT2U = 0x%08X\n", mfspr (DBAT2U));
395 printf ("DBAT3L = 0x%08X\n", mfspr (DBAT3L));
396 printf ("DBAT3U = 0x%08X\n", mfspr (DBAT3U));
397 #endif /* INCLUDE_MPC107_REPORT */
398 #endif /* CONFIG_MOUSSE */