2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * This file is based on mpc4200fec.c,
6 * (C) Copyright Motorola, Inc., 2000
17 DECLARE_GLOBAL_DATA_PTR;
19 /* #define DEBUG 0x28 */
21 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
22 defined(CONFIG_MPC5xxx_FEC)
24 #if !(defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII))
25 #error "CONFIG_MII has to be defined!"
29 static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec);
30 static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec);
34 static uint32 local_crc32(char *string, unsigned int crc_value, int len);
38 uint8 data[1500]; /* actual data */
39 int length; /* actual length */
40 int used; /* buffer in use or not */
41 uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
44 int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal);
45 int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
47 /********************************************************************/
49 static void mpc5xxx_fec_phydump (char *devname)
52 uint8 phyAddr = CONFIG_PHY_ADDR;
54 #if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */
55 /* regs to print: 0...7, 16...19, 21, 23, 24 */
56 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
57 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
59 /* regs to print: 0...8, 16...20 */
60 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
61 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
65 for (i = 0; i < 32; i++) {
67 miiphy_read(devname, phyAddr, i, &phyStatus);
68 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
74 /********************************************************************/
75 static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
81 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
83 data = (char *)malloc(FEC_MAX_PKT_SIZE);
85 printf ("RBD INIT FAILED\n");
88 fec->rbdBase[ix].dataPointer = (uint32)data;
90 fec->rbdBase[ix].status = FEC_RBD_EMPTY;
91 fec->rbdBase[ix].dataLength = 0;
96 * have the last RBD to close the ring
98 fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
104 /********************************************************************/
105 static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
109 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
110 fec->tbdBase[ix].status = 0;
114 * Have the last TBD to close the ring
116 fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
119 * Initialize some indices
122 fec->usedTbdIndex = 0;
123 fec->cleanTbdNum = FEC_TBD_NUM;
126 /********************************************************************/
127 static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, volatile FEC_RBD * pRbd)
130 * Reset buffer descriptor as empty
132 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
133 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
135 pRbd->status = FEC_RBD_EMPTY;
137 pRbd->dataLength = 0;
140 * Now, we have an empty RxBD, restart the SmartDMA receive task
142 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
147 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
150 /********************************************************************/
151 static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
153 volatile FEC_TBD *pUsedTbd;
156 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
157 fec->cleanTbdNum, fec->usedTbdIndex);
161 * process all the consumed TBDs
163 while (fec->cleanTbdNum < FEC_TBD_NUM) {
164 pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
165 if (pUsedTbd->status & FEC_TBD_READY) {
167 printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
173 * clean this buffer descriptor
175 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
176 pUsedTbd->status = FEC_TBD_WRAP;
178 pUsedTbd->status = 0;
181 * update some indeces for a correct handling of the TBD ring
184 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
188 /********************************************************************/
189 static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
191 uint8 currByte; /* byte for which to compute the CRC */
192 int byte; /* loop - counter */
193 int bit; /* loop - counter */
194 uint32 crc = 0xffffffff; /* initial value */
197 * The algorithm used is the following:
198 * we loop on each of the six bytes of the provided address,
199 * and we compute the CRC by left-shifting the previous
200 * value by one position, so that each bit in the current
201 * byte of the address may contribute the calculation. If
202 * the latter and the MSB in the CRC are different, then
203 * the CRC value so computed is also ex-ored with the
204 * "polynomium generator". The current byte of the address
205 * is also shifted right by one bit at each iteration.
206 * This is because the CRC generatore in hardware is implemented
207 * as a shift-register with as many ex-ores as the radixes
208 * in the polynomium. This suggests that we represent the
209 * polynomiumm itself as a 32-bit constant.
211 for (byte = 0; byte < 6; byte++) {
212 currByte = mac[byte];
213 for (bit = 0; bit < 8; bit++) {
214 if ((currByte & 0x01) ^ (crc & 0x01)) {
216 crc = crc ^ 0xedb88320;
227 * Set individual hash table register
230 fec->eth->iaddr1 = (1 << (crc - 32));
231 fec->eth->iaddr2 = 0;
233 fec->eth->iaddr1 = 0;
234 fec->eth->iaddr2 = (1 << crc);
238 * Set physical address
240 fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
241 fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
244 /********************************************************************/
245 static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
247 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
248 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
251 printf ("mpc5xxx_fec_init... Begin\n");
255 * Initialize RxBD/TxBD rings
257 mpc5xxx_fec_rbd_init(fec);
258 mpc5xxx_fec_tbd_init(fec);
261 * Clear FEC-Lite interrupt event register(IEVENT)
263 fec->eth->ievent = 0xffffffff;
266 * Set interrupt mask register
268 fec->eth->imask = 0x00000000;
271 * Set FEC-Lite receive control register(R_CNTRL):
273 if (fec->xcv_type == SEVENWIRE) {
275 * Frame length=1518; 7-wire mode
277 fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
280 * Frame length=1518; MII mode;
282 fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
285 fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
286 if (fec->xcv_type != SEVENWIRE) {
288 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
289 * and do not drop the Preamble.
291 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
295 * Set Opcode/Pause Duration Register
297 fec->eth->op_pause = 0x00010020; /*FIXME0xffff0020; */
300 * Set Rx FIFO alarm and granularity value
302 fec->eth->rfifo_cntrl = 0x0c000000
303 | (fec->eth->rfifo_cntrl & ~0x0f000000);
304 fec->eth->rfifo_alarm = 0x0000030c;
306 if (fec->eth->rfifo_status & 0x00700000 ) {
307 printf("mpc5xxx_fec_init() RFIFO error\n");
312 * Set Tx FIFO granularity value
314 fec->eth->tfifo_cntrl = 0x0c000000
315 | (fec->eth->tfifo_cntrl & ~0x0f000000);
317 printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
318 printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
322 * Set transmit fifo watermark register(X_WMRK), default = 64
324 fec->eth->tfifo_alarm = 0x00000080;
325 fec->eth->x_wmrk = 0x2;
328 * Set individual address filter for unicast address
329 * and set physical address registers.
331 mpc5xxx_fec_set_hwaddr(fec, (char *)dev->enetaddr);
334 * Set multicast address filter
336 fec->eth->gaddr1 = 0x00000000;
337 fec->eth->gaddr2 = 0x00000000;
340 * Turn ON cheater FSM: ????
342 fec->eth->xmit_fsm = 0x03000000;
344 #if defined(CONFIG_MPC5200)
346 * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
347 * work w/ the current receive task.
349 sdma->PtdCntrl |= 0x00000001;
353 * Set priority of different initiators
355 sdma->IPR0 = 7; /* always */
356 sdma->IPR3 = 6; /* Eth RX */
357 sdma->IPR4 = 5; /* Eth Tx */
360 * Clear SmartDMA task interrupt pending bits
362 SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
365 * Initialize SmartDMA parameters stored in SRAM
367 *(volatile int *)FEC_TBD_BASE = (int)fec->tbdBase;
368 *(volatile int *)FEC_RBD_BASE = (int)fec->rbdBase;
369 *(volatile int *)FEC_TBD_NEXT = (int)fec->tbdBase;
370 *(volatile int *)FEC_RBD_NEXT = (int)fec->rbdBase;
373 * Enable FEC-Lite controller
375 fec->eth->ecntrl |= 0x00000006;
378 if (fec->xcv_type != SEVENWIRE)
379 mpc5xxx_fec_phydump (dev->name);
383 * Enable SmartDMA receive task
385 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
388 printf("mpc5xxx_fec_init... Done \n");
394 /********************************************************************/
395 static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
397 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
398 const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
401 printf ("mpc5xxx_fec_init_phy... Begin\n");
405 * Initialize GPIO pins
407 if (fec->xcv_type == SEVENWIRE) {
408 /* 10MBit with 7-wire operation */
409 #if defined(CONFIG_TOTAL5200)
410 /* 7-wire and USB2 on Ethernet */
411 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00030000;
412 #else /* !CONFIG_TOTAL5200 */
414 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
415 #endif /* CONFIG_TOTAL5200 */
417 /* 100MBit with MD operation */
418 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
422 * Clear FEC-Lite interrupt event register(IEVENT)
424 fec->eth->ievent = 0xffffffff;
427 * Set interrupt mask register
429 fec->eth->imask = 0x00000000;
432 * In original Promess-provided code PHY initialization is disabled with the
433 * following comment: "Phy initialization is DISABLED for now. There was a
434 * problem with running 100 Mbps on PRO board". Thus we temporarily disable
435 * PHY initialization for the Motion-PRO board, until a proper fix is found.
438 if (fec->xcv_type != SEVENWIRE) {
440 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
441 * and do not drop the Preamble.
443 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
446 if (fec->xcv_type != SEVENWIRE) {
448 * Initialize PHY(LXT971A):
450 * Generally, on power up, the LXT971A reads its configuration
451 * pins to check for forced operation, If not cofigured for
452 * forced operation, it uses auto-negotiation/parallel detection
453 * to automatically determine line operating conditions.
454 * If the PHY device on the other side of the link supports
455 * auto-negotiation, the LXT971A auto-negotiates with it
456 * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
457 * support auto-negotiation, the LXT971A automatically detects
458 * the presence of either link pulses(10Mbps PHY) or Idle
459 * symbols(100Mbps) and sets its operating conditions accordingly.
461 * When auto-negotiation is controlled by software, the following
462 * steps are recommended.
465 * The physical address is dependent on hardware configuration.
472 * Reset PHY, then delay 300ns
474 miiphy_write(dev->name, phyAddr, 0x0, 0x8000);
477 if (fec->xcv_type == MII10) {
479 * Force 10Base-T, FDX operation
482 printf("Forcing 10 Mbps ethernet link... ");
484 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
486 miiphy_write(dev->name, fec, phyAddr, 0x0, 0x0100);
488 miiphy_write(dev->name, phyAddr, 0x0, 0x0180);
491 do { /* wait for link status to go down */
493 if ((timeout--) == 0) {
495 printf("hmmm, should not have waited...");
499 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
503 } while ((phyStatus & 0x0004)); /* !link up */
506 do { /* wait for link status to come back up */
508 if ((timeout--) == 0) {
509 printf("failed. Link is down.\n");
512 miiphy_read(dev->name, phyAddr, 0x1, &phyStatus);
516 } while (!(phyStatus & 0x0004)); /* !link up */
521 } else { /* MII100 */
523 * Set the auto-negotiation advertisement register bits
525 miiphy_write(dev->name, phyAddr, 0x4, 0x01e1);
528 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
530 miiphy_write(dev->name, phyAddr, 0x0, 0x1200);
533 * Wait for AN completion
539 if ((timeout--) == 0) {
541 printf("PHY auto neg 0 failed...\n");
546 if (miiphy_read(dev->name, phyAddr, 0x1, &phyStatus) != 0) {
548 printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
552 } while (!(phyStatus & 0x0004));
555 printf("PHY auto neg complete! \n");
562 if (fec->xcv_type != SEVENWIRE)
563 mpc5xxx_fec_phydump (dev->name);
568 printf("mpc5xxx_fec_init_phy... Done \n");
574 /********************************************************************/
575 static void mpc5xxx_fec_halt(struct eth_device *dev)
577 #if defined(CONFIG_MPC5200)
578 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
580 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
581 int counter = 0xffff;
584 if (fec->xcv_type != SEVENWIRE)
585 mpc5xxx_fec_phydump (dev->name);
589 * mask FEC chip interrupts
594 * issue graceful stop command to the FEC transmitter if necessary
596 fec->eth->x_cntrl |= 0x00000001;
599 * wait for graceful stop to register
601 while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
604 * Disable SmartDMA tasks
606 SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
607 SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
609 #if defined(CONFIG_MPC5200)
611 * Turn on COMM bus prefetch in the MGT5200 BestComm after we're
612 * done. It doesn't work w/ the current receive task.
614 sdma->PtdCntrl &= ~0x00000001;
618 * Disable the Ethernet Controller
620 fec->eth->ecntrl &= 0xfffffffd;
623 * Clear FIFO status registers
625 fec->eth->rfifo_status &= 0x00700000;
626 fec->eth->tfifo_status &= 0x00700000;
628 fec->eth->reset_cntrl = 0x01000000;
631 * Issue a reset command to the FEC chip
633 fec->eth->ecntrl |= 0x1;
636 * wait at least 16 clock cycles
641 printf("Ethernet task stopped\n");
646 /********************************************************************/
648 static void tfifo_print(char *devname, mpc5xxx_fec_priv *fec)
650 uint16 phyAddr = CONFIG_PHY_ADDR;
653 if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
654 || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
656 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
657 printf("\nphyStatus: 0x%04x\n", phyStatus);
658 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
659 printf("ievent: 0x%08x\n", fec->eth->ievent);
660 printf("x_status: 0x%08x\n", fec->eth->x_status);
661 printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
663 printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
664 printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
665 printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
666 printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
667 printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
668 printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
672 static void rfifo_print(char *devname, mpc5xxx_fec_priv *fec)
674 uint16 phyAddr = CONFIG_PHY_ADDR;
677 if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
678 || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
680 miiphy_read(devname, phyAddr, 0x1, &phyStatus);
681 printf("\nphyStatus: 0x%04x\n", phyStatus);
682 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
683 printf("ievent: 0x%08x\n", fec->eth->ievent);
684 printf("x_status: 0x%08x\n", fec->eth->x_status);
685 printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
687 printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
688 printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
689 printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
690 printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
691 printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
692 printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
697 /********************************************************************/
699 static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data,
703 * This routine transmits one frame. This routine only accepts
704 * 6-byte Ethernet addresses.
706 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
707 volatile FEC_TBD *pTbd;
710 printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
711 tfifo_print(dev->name, fec);
715 * Clear Tx BD ring at first
717 mpc5xxx_fec_tbd_scrub(fec);
720 * Check for valid length of data.
722 if ((data_length > 1500) || (data_length <= 0)) {
727 * Check the number of vacant TxBDs.
729 if (fec->cleanTbdNum < 1) {
731 printf("No available TxBDs ...\n");
737 * Get the first TxBD to send the mac header
739 pTbd = &fec->tbdBase[fec->tbdIndex];
740 pTbd->dataLength = data_length;
741 pTbd->dataPointer = (uint32)eth_data;
742 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
743 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
746 printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
752 if (fec->xcv_type != SEVENWIRE) {
754 miiphy_read(dev->name, 0, 0x1, &phyStatus);
758 * Enable SmartDMA transmit task
762 tfifo_print(dev->name, fec);
764 SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
766 tfifo_print(dev->name, fec);
772 fec->cleanTbdNum -= 1;
774 #if (DEBUG & 0x129) && (DEBUG & 0x80000000)
775 printf ("smartDMA ethernet Tx task enabled\n");
778 * wait until frame is sent .
780 while (pTbd->status & FEC_TBD_READY) {
783 printf ("TDB status = %04x\n", pTbd->status);
791 /********************************************************************/
792 static int mpc5xxx_fec_recv(struct eth_device *dev)
795 * This command pulls one frame from the card
797 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
798 volatile FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
799 unsigned long ievent;
800 int frame_length, len = 0;
802 uchar buff[FEC_MAX_PKT_SIZE];
805 printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
812 * Check if any critical events have happened
814 ievent = fec->eth->ievent;
815 fec->eth->ievent = ievent;
816 if (ievent & 0x20060000) {
817 /* BABT, Rx/Tx FIFO errors */
818 mpc5xxx_fec_halt(dev);
819 mpc5xxx_fec_init(dev, NULL);
822 if (ievent & 0x80000000) {
823 /* Heartbeat error */
824 fec->eth->x_cntrl |= 0x00000001;
826 if (ievent & 0x10000000) {
827 /* Graceful stop complete */
828 if (fec->eth->x_cntrl & 0x00000001) {
829 mpc5xxx_fec_halt(dev);
830 fec->eth->x_cntrl &= ~0x00000001;
831 mpc5xxx_fec_init(dev, NULL);
835 if (!(pRbd->status & FEC_RBD_EMPTY)) {
836 if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
837 ((pRbd->dataLength - 4) > 14)) {
840 * Get buffer address and size
842 frame = (NBUF *)pRbd->dataPointer;
843 frame_length = pRbd->dataLength - 4;
848 printf("recv data hdr:");
849 for (i = 0; i < 14; i++)
850 printf("%x ", *(frame->head + i));
855 * Fill the buffer and pass it to upper layers
857 memcpy(buff, frame->head, 14);
858 memcpy(buff + 14, frame->data, frame_length);
859 NetReceive(buff, frame_length);
863 * Reset buffer descriptor as empty
865 mpc5xxx_fec_rbd_clean(fec, pRbd);
867 SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
872 /********************************************************************/
873 int mpc5xxx_fec_initialize(bd_t * bis)
875 mpc5xxx_fec_priv *fec;
876 struct eth_device *dev;
878 char env_enetaddr[6];
881 fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
882 dev = (struct eth_device *)malloc(sizeof(*dev));
883 memset(dev, 0, sizeof *dev);
885 fec->eth = (ethernet_regs *)MPC5XXX_FEC;
886 fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
887 fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
888 #if defined(CONFIG_CANMB) || defined(CONFIG_HMI1001) || \
889 defined(CONFIG_ICECUBE) || defined(CONFIG_INKA4X0) || \
890 defined(CONFIG_MCC200) || defined(CONFIG_MOTIONPRO) || \
891 defined(CONFIG_O2DNT) || defined(CONFIG_PM520) || \
892 defined(CONFIG_TOP5200) || defined(CONFIG_TQM5200) || \
893 defined(CONFIG_UC101) || defined(CONFIG_V38B)
894 # ifndef CONFIG_FEC_10MBIT
895 fec->xcv_type = MII100;
897 fec->xcv_type = MII10;
899 #elif defined(CONFIG_TOTAL5200)
900 fec->xcv_type = SEVENWIRE;
902 #error fec->xcv_type not initialized.
905 dev->priv = (void *)fec;
906 dev->iobase = MPC5XXX_FEC;
907 dev->init = mpc5xxx_fec_init;
908 dev->halt = mpc5xxx_fec_halt;
909 dev->send = mpc5xxx_fec_send;
910 dev->recv = mpc5xxx_fec_recv;
912 sprintf(dev->name, "FEC ETHERNET");
915 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
916 miiphy_register (dev->name,
917 fec5xxx_miiphy_read, fec5xxx_miiphy_write);
921 * Try to set the mac address now. The fec mac address is
922 * a garbage after reset. When not using fec for booting
923 * the Linux fec driver will try to work with this garbage.
925 tmp = getenv("ethaddr");
927 for (i=0; i<6; i++) {
928 env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
930 tmp = (*end) ? end+1 : end;
932 mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
935 mpc5xxx_fec_init_phy(dev, bis);
940 /* MII-interface related functions */
941 /********************************************************************/
942 int fec5xxx_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
944 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
945 uint32 reg; /* convenient holder for the PHY register */
946 uint32 phy; /* convenient holder for the PHY */
947 int timeout = 0xffff;
950 * reading from any PHY's register is done by properly
951 * programming the FEC's MII data register.
953 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
954 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
956 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
959 * wait for the related interrupt
961 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
965 printf ("Read MDIO failed...\n");
971 * clear mii interrupt bit
973 eth->ievent = 0x00800000;
976 * it's now safe to read the PHY's register
978 *retVal = (uint16) eth->mii_data;
983 /********************************************************************/
984 int fec5xxx_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
986 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
987 uint32 reg; /* convenient holder for the PHY register */
988 uint32 phy; /* convenient holder for the PHY */
989 int timeout = 0xffff;
991 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
992 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
994 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
995 FEC_MII_DATA_TA | phy | reg | data);
998 * wait for the MII interrupt
1000 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
1004 printf ("Write MDIO failed...\n");
1010 * clear MII interrupt bit
1012 eth->ievent = 0x00800000;
1018 static uint32 local_crc32(char *string, unsigned int crc_value, int len)
1022 unsigned int crc, count;
1028 * crc = 0xffffffff; * The initialized value should be 0xffffffff
1032 for (i = len; --i >= 0;) {
1034 for (count = 0; count < 8; count++) {
1035 if ((c & 0x01) ^ (crc & 0x01)) {
1037 crc = crc ^ 0xedb88320;
1046 * In big endian system, do byte swaping for crc value
1052 #endif /* CONFIG_MPC5xxx_FEC */