3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * This file is based on mpc4200fec.c,
6 * (C) Copyright Motorola, Inc., 2000
17 /* #define DEBUG 0x28 */
19 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
20 defined(CONFIG_MPC5xxx_FEC)
23 static void tfifo_print(mpc5xxx_fec_priv *fec);
24 static void rfifo_print(mpc5xxx_fec_priv *fec);
28 static uint32 local_crc32(char *string, unsigned int crc_value, int len);
32 uint8 data[1500]; /* actual data */
33 int length; /* actual length */
34 int used; /* buffer in use or not */
35 uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
38 /********************************************************************/
40 static void mpc5xxx_fec_phydump (void)
43 uint8 phyAddr = CONFIG_PHY_ADDR;
45 #if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */
46 /* regs to print: 0...7, 16...19, 21, 23, 24 */
47 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
48 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
50 /* regs to print: 0...8, 16...20 */
51 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
52 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
56 for (i = 0; i < 32; i++) {
58 miiphy_read(phyAddr, i, &phyStatus);
59 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
65 /********************************************************************/
66 static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
72 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
74 data = (char *)malloc(FEC_MAX_PKT_SIZE);
76 printf ("RBD INIT FAILED\n");
79 fec->rbdBase[ix].dataPointer = (uint32)data;
81 fec->rbdBase[ix].status = FEC_RBD_EMPTY;
82 fec->rbdBase[ix].dataLength = 0;
87 * have the last RBD to close the ring
89 fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
95 /********************************************************************/
96 static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
100 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
101 fec->tbdBase[ix].status = 0;
105 * Have the last TBD to close the ring
107 fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
110 * Initialize some indices
113 fec->usedTbdIndex = 0;
114 fec->cleanTbdNum = FEC_TBD_NUM;
117 /********************************************************************/
118 static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, FEC_RBD * pRbd)
121 * Reset buffer descriptor as empty
123 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
124 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
126 pRbd->status = FEC_RBD_EMPTY;
128 pRbd->dataLength = 0;
131 * Now, we have an empty RxBD, restart the SmartDMA receive task
133 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
138 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
141 /********************************************************************/
142 static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
147 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
148 fec->cleanTbdNum, fec->usedTbdIndex);
152 * process all the consumed TBDs
154 while (fec->cleanTbdNum < FEC_TBD_NUM) {
155 pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
156 if (pUsedTbd->status & FEC_TBD_READY) {
158 printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
164 * clean this buffer descriptor
166 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
167 pUsedTbd->status = FEC_TBD_WRAP;
169 pUsedTbd->status = 0;
172 * update some indeces for a correct handling of the TBD ring
175 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
179 /********************************************************************/
180 static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
182 uint8 currByte; /* byte for which to compute the CRC */
183 int byte; /* loop - counter */
184 int bit; /* loop - counter */
185 uint32 crc = 0xffffffff; /* initial value */
188 * The algorithm used is the following:
189 * we loop on each of the six bytes of the provided address,
190 * and we compute the CRC by left-shifting the previous
191 * value by one position, so that each bit in the current
192 * byte of the address may contribute the calculation. If
193 * the latter and the MSB in the CRC are different, then
194 * the CRC value so computed is also ex-ored with the
195 * "polynomium generator". The current byte of the address
196 * is also shifted right by one bit at each iteration.
197 * This is because the CRC generatore in hardware is implemented
198 * as a shift-register with as many ex-ores as the radixes
199 * in the polynomium. This suggests that we represent the
200 * polynomiumm itself as a 32-bit constant.
202 for (byte = 0; byte < 6; byte++) {
203 currByte = mac[byte];
204 for (bit = 0; bit < 8; bit++) {
205 if ((currByte & 0x01) ^ (crc & 0x01)) {
207 crc = crc ^ 0xedb88320;
218 * Set individual hash table register
221 fec->eth->iaddr1 = (1 << (crc - 32));
222 fec->eth->iaddr2 = 0;
224 fec->eth->iaddr1 = 0;
225 fec->eth->iaddr2 = (1 << crc);
229 * Set physical address
231 fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
232 fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
235 /********************************************************************/
236 static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
238 DECLARE_GLOBAL_DATA_PTR;
239 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
240 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
241 const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
244 printf ("mpc5xxx_fec_init... Begin\n");
248 * Initialize RxBD/TxBD rings
250 mpc5xxx_fec_rbd_init(fec);
251 mpc5xxx_fec_tbd_init(fec);
254 * Initialize GPIO pins
256 if (fec->xcv_type == SEVENWIRE) {
257 /* 10MBit with 7-wire operation */
258 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
260 /* 100MBit with MD operation */
261 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
265 * Clear FEC-Lite interrupt event register(IEVENT)
267 fec->eth->ievent = 0xffffffff;
270 * Set interrupt mask register
272 fec->eth->imask = 0x00000000;
275 * Set FEC-Lite receive control register(R_CNTRL):
277 if (fec->xcv_type == SEVENWIRE) {
279 * Frame length=1518; 7-wire mode
281 fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
284 * Frame length=1518; MII mode;
286 fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
289 fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
290 if (fec->xcv_type != SEVENWIRE) {
292 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
293 * and do not drop the Preamble.
295 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
299 * Set Opcode/Pause Duration Register
301 fec->eth->op_pause = 0x00010020; /*FIXME0xffff0020; */
304 * Set Rx FIFO alarm and granularity value
306 fec->eth->rfifo_cntrl = 0x0c000000;
307 fec->eth->rfifo_alarm = 0x0000030c;
309 if (fec->eth->rfifo_status & 0x00700000 ) {
310 printf("mpc5xxx_fec_init() RFIFO error\n");
315 * Set Tx FIFO granularity value
317 fec->eth->tfifo_cntrl = 0x0c000000;
319 printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
320 printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
324 * Set transmit fifo watermark register(X_WMRK), default = 64
326 fec->eth->tfifo_alarm = 0x00000080;
327 fec->eth->x_wmrk = 0x2;
330 * Set individual address filter for unicast address
331 * and set physical address registers.
333 mpc5xxx_fec_set_hwaddr(fec, dev->enetaddr);
336 * Set multicast address filter
338 fec->eth->gaddr1 = 0x00000000;
339 fec->eth->gaddr2 = 0x00000000;
342 * Turn ON cheater FSM: ????
344 fec->eth->xmit_fsm = 0x03000000;
346 #if defined(CONFIG_MPC5200)
348 * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
349 * work w/ the current receive task.
351 sdma->PtdCntrl |= 0x00000001;
355 * Set priority of different initiators
357 sdma->IPR0 = 7; /* always */
358 sdma->IPR3 = 6; /* Eth RX */
359 sdma->IPR4 = 5; /* Eth Tx */
362 * Clear SmartDMA task interrupt pending bits
364 SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
367 * Initialize SmartDMA parameters stored in SRAM
369 *(int *)FEC_TBD_BASE = (int)fec->tbdBase;
370 *(int *)FEC_RBD_BASE = (int)fec->rbdBase;
371 *(int *)FEC_TBD_NEXT = (int)fec->tbdBase;
372 *(int *)FEC_RBD_NEXT = (int)fec->rbdBase;
374 if (fec->xcv_type != SEVENWIRE) {
376 * Initialize PHY(LXT971A):
378 * Generally, on power up, the LXT971A reads its configuration
379 * pins to check for forced operation, If not cofigured for
380 * forced operation, it uses auto-negotiation/parallel detection
381 * to automatically determine line operating conditions.
382 * If the PHY device on the other side of the link supports
383 * auto-negotiation, the LXT971A auto-negotiates with it
384 * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
385 * support auto-negotiation, the LXT971A automatically detects
386 * the presence of either link pulses(10Mbps PHY) or Idle
387 * symbols(100Mbps) and sets its operating conditions accordingly.
389 * When auto-negotiation is controlled by software, the following
390 * steps are recommended.
393 * The physical address is dependent on hardware configuration.
400 * Reset PHY, then delay 300ns
402 miiphy_write(phyAddr, 0x0, 0x8000);
405 if (fec->xcv_type == MII10) {
407 * Force 10Base-T, FDX operation
410 printf("Forcing 10 Mbps ethernet link... ");
412 miiphy_read(phyAddr, 0x1, &phyStatus);
414 miiphy_write(fec, phyAddr, 0x0, 0x0100);
416 miiphy_write(phyAddr, 0x0, 0x0180);
419 do { /* wait for link status to go down */
421 if ((timeout--) == 0) {
423 printf("hmmm, should not have waited...");
427 miiphy_read(phyAddr, 0x1, &phyStatus);
431 } while ((phyStatus & 0x0004)); /* !link up */
434 do { /* wait for link status to come back up */
436 if ((timeout--) == 0) {
437 printf("failed. Link is down.\n");
440 miiphy_read(phyAddr, 0x1, &phyStatus);
444 } while (!(phyStatus & 0x0004)); /* !link up */
449 } else { /* MII100 */
451 * Set the auto-negotiation advertisement register bits
453 miiphy_write(phyAddr, 0x4, 0x01e1);
456 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
458 miiphy_write(phyAddr, 0x0, 0x1200);
461 * Wait for AN completion
467 if ((timeout--) == 0) {
469 printf("PHY auto neg 0 failed...\n");
474 if (miiphy_read(phyAddr, 0x1, &phyStatus) != 0) {
476 printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
480 } while (!(phyStatus & 0x0004));
483 printf("PHY auto neg complete! \n");
490 * Enable FEC-Lite controller
492 fec->eth->ecntrl |= 0x00000006;
495 if (fec->xcv_type != SEVENWIRE)
496 mpc5xxx_fec_phydump ();
500 * Enable SmartDMA receive task
502 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
505 printf("mpc5xxx_fec_init... Done \n");
511 /********************************************************************/
512 static void mpc5xxx_fec_halt(struct eth_device *dev)
514 #if defined(CONFIG_MPC5200)
515 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
517 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
518 int counter = 0xffff;
521 if (fec->xcv_type != SEVENWIRE)
522 mpc5xxx_fec_phydump ();
526 * mask FEC chip interrupts
531 * issue graceful stop command to the FEC transmitter if necessary
533 fec->eth->x_cntrl |= 0x00000001;
536 * wait for graceful stop to register
538 while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
541 * Disable SmartDMA tasks
543 SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
544 SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
546 #if defined(CONFIG_MPC5200)
548 * Turn on COMM bus prefetch in the MGT5200 BestComm after we're
549 * done. It doesn't work w/ the current receive task.
551 sdma->PtdCntrl &= ~0x00000001;
555 * Disable the Ethernet Controller
557 fec->eth->ecntrl &= 0xfffffffd;
560 * Clear FIFO status registers
562 fec->eth->rfifo_status &= 0x00700000;
563 fec->eth->tfifo_status &= 0x00700000;
565 fec->eth->reset_cntrl = 0x01000000;
568 * Issue a reset command to the FEC chip
570 fec->eth->ecntrl |= 0x1;
573 * wait at least 16 clock cycles
578 printf("Ethernet task stopped\n");
583 /********************************************************************/
585 static void tfifo_print(mpc5xxx_fec_priv *fec)
587 uint16 phyAddr = CONFIG_PHY_ADDR;
590 if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
591 || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
593 miiphy_read(phyAddr, 0x1, &phyStatus);
594 printf("\nphyStatus: 0x%04x\n", phyStatus);
595 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
596 printf("ievent: 0x%08x\n", fec->eth->ievent);
597 printf("x_status: 0x%08x\n", fec->eth->x_status);
598 printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
600 printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
601 printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
602 printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
603 printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
604 printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
605 printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
609 static void rfifo_print(mpc5xxx_fec_priv *fec)
611 uint16 phyAddr = CONFIG_PHY_ADDR;
614 if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
615 || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
617 miiphy_read(phyAddr, 0x1, &phyStatus);
618 printf("\nphyStatus: 0x%04x\n", phyStatus);
619 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
620 printf("ievent: 0x%08x\n", fec->eth->ievent);
621 printf("x_status: 0x%08x\n", fec->eth->x_status);
622 printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
624 printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
625 printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
626 printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
627 printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
628 printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
629 printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
634 /********************************************************************/
636 static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data,
640 * This routine transmits one frame. This routine only accepts
641 * 6-byte Ethernet addresses.
643 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
647 printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
652 * Clear Tx BD ring at first
654 mpc5xxx_fec_tbd_scrub(fec);
657 * Check for valid length of data.
659 if ((data_length > 1500) || (data_length <= 0)) {
664 * Check the number of vacant TxBDs.
666 if (fec->cleanTbdNum < 1) {
668 printf("No available TxBDs ...\n");
674 * Get the first TxBD to send the mac header
676 pTbd = &fec->tbdBase[fec->tbdIndex];
677 pTbd->dataLength = data_length;
678 pTbd->dataPointer = (uint32)eth_data;
679 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
680 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
683 printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
689 if (fec->xcv_type != SEVENWIRE) {
691 miiphy_read(0, 0x1, &phyStatus);
695 * Enable SmartDMA transmit task
701 SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
709 fec->cleanTbdNum -= 1;
711 #if (DEBUG & 0x129) && (DEBUG & 0x80000000)
712 printf ("smartDMA ethernet Tx task enabled\n");
715 * wait until frame is sent .
717 while (pTbd->status & FEC_TBD_READY) {
720 printf ("TDB status = %04x\n", pTbd->status);
728 /********************************************************************/
729 static int mpc5xxx_fec_recv(struct eth_device *dev)
732 * This command pulls one frame from the card
734 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
735 FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
736 unsigned long ievent;
737 int frame_length, len = 0;
739 char buff[FEC_MAX_PKT_SIZE];
742 printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
749 * Check if any critical events have happened
751 ievent = fec->eth->ievent;
752 fec->eth->ievent = ievent;
753 if (ievent & 0x20060000) {
754 /* BABT, Rx/Tx FIFO errors */
755 mpc5xxx_fec_halt(dev);
756 mpc5xxx_fec_init(dev, NULL);
759 if (ievent & 0x80000000) {
760 /* Heartbeat error */
761 fec->eth->x_cntrl |= 0x00000001;
763 if (ievent & 0x10000000) {
764 /* Graceful stop complete */
765 if (fec->eth->x_cntrl & 0x00000001) {
766 mpc5xxx_fec_halt(dev);
767 fec->eth->x_cntrl &= ~0x00000001;
768 mpc5xxx_fec_init(dev, NULL);
772 if (!(pRbd->status & FEC_RBD_EMPTY)) {
773 if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
774 ((pRbd->dataLength - 4) > 14)) {
777 * Get buffer address and size
779 frame = (NBUF *)pRbd->dataPointer;
780 frame_length = pRbd->dataLength - 4;
785 printf("recv data hdr:");
786 for (i = 0; i < 14; i++)
787 printf("%x ", *(frame->head + i));
792 * Fill the buffer and pass it to upper layers
794 memcpy(buff, frame->head, 14);
795 memcpy(buff + 14, frame->data, frame_length);
796 NetReceive(buff, frame_length);
800 * Reset buffer descriptor as empty
802 mpc5xxx_fec_rbd_clean(fec, pRbd);
804 SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
809 /********************************************************************/
810 int mpc5xxx_fec_initialize(bd_t * bis)
812 mpc5xxx_fec_priv *fec;
813 struct eth_device *dev;
815 char env_enetaddr[6];
818 fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
819 dev = (struct eth_device *)malloc(sizeof(*dev));
820 memset(dev, 0, sizeof *dev);
822 fec->eth = (ethernet_regs *)MPC5XXX_FEC;
823 fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
824 fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
825 #if defined(CONFIG_ICECUBE) || \
826 defined(CONFIG_PM520) || \
827 defined(CONFIG_TOP5200)
828 # ifndef CONFIG_FEC_10MBIT
829 fec->xcv_type = MII100;
831 fec->xcv_type = MII10;
834 #error fec->xcv_type not initialized.
837 dev->priv = (void *)fec;
838 dev->iobase = MPC5XXX_FEC;
839 dev->init = mpc5xxx_fec_init;
840 dev->halt = mpc5xxx_fec_halt;
841 dev->send = mpc5xxx_fec_send;
842 dev->recv = mpc5xxx_fec_recv;
844 sprintf(dev->name, "FEC ETHERNET");
848 * Try to set the mac address now. The fec mac address is
849 * a garbage after reset. When not using fec for booting
850 * the Linux fec driver will try to work with this garbage.
852 tmp = getenv("ethaddr");
854 for (i=0; i<6; i++) {
855 env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
857 tmp = (*end) ? end+1 : end;
859 mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
865 /* MII-interface related functions */
866 /********************************************************************/
867 int miiphy_read(uint8 phyAddr, uint8 regAddr, uint16 * retVal)
869 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
870 uint32 reg; /* convenient holder for the PHY register */
871 uint32 phy; /* convenient holder for the PHY */
872 int timeout = 0xffff;
875 * reading from any PHY's register is done by properly
876 * programming the FEC's MII data register.
878 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
879 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
881 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
884 * wait for the related interrupt
886 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
890 printf ("Read MDIO failed...\n");
896 * clear mii interrupt bit
898 eth->ievent = 0x00800000;
901 * it's now safe to read the PHY's register
903 *retVal = (uint16) eth->mii_data;
908 /********************************************************************/
909 int miiphy_write(uint8 phyAddr, uint8 regAddr, uint16 data)
911 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
912 uint32 reg; /* convenient holder for the PHY register */
913 uint32 phy; /* convenient holder for the PHY */
914 int timeout = 0xffff;
916 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
917 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
919 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
920 FEC_MII_DATA_TA | phy | reg | data);
923 * wait for the MII interrupt
925 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
929 printf ("Write MDIO failed...\n");
935 * clear MII interrupt bit
937 eth->ievent = 0x00800000;
943 static uint32 local_crc32(char *string, unsigned int crc_value, int len)
947 unsigned int crc, count;
953 * crc = 0xffffffff; * The initialized value should be 0xffffffff
957 for (i = len; --i >= 0;) {
959 for (count = 0; count < 8; count++) {
960 if ((c & 0x01) ^ (crc & 0x01)) {
962 crc = crc ^ 0xedb88320;
971 * In big endian system, do byte swaping for crc value
977 #endif /* CONFIG_MPC5xxx_FEC */