3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * This file is based on mpc4200fec.c,
6 * (C) Copyright Motorola, Inc., 2000
17 /* #define DEBUG 0x28 */
19 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
20 defined(CONFIG_MPC5xxx_FEC)
23 static void tfifo_print(mpc5xxx_fec_priv *fec);
24 static void rfifo_print(mpc5xxx_fec_priv *fec);
28 static uint32 local_crc32(char *string, unsigned int crc_value, int len);
32 uint8 data[1500]; /* actual data */
33 int length; /* actual length */
34 int used; /* buffer in use or not */
35 uint8 head[16]; /* MAC header(6 + 6 + 2) + 2(aligned) */
38 /********************************************************************/
40 static void mpc5xxx_fec_phydump (void)
43 uint8 phyAddr = CONFIG_PHY_ADDR;
45 #if CONFIG_PHY_TYPE == 0x79c874 /* AMD Am79C874 */
46 /* regs to print: 0...7, 16...19, 21, 23, 24 */
47 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0,
48 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0,
50 /* regs to print: 0...8, 16...20 */
51 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
52 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
56 for (i = 0; i < 32; i++) {
58 miiphy_read(phyAddr, i, &phyStatus);
59 printf("Mii reg %d: 0x%04x\n", i, phyStatus);
65 /********************************************************************/
66 static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
72 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
74 data = (char *)malloc(FEC_MAX_PKT_SIZE);
76 printf ("RBD INIT FAILED\n");
79 fec->rbdBase[ix].dataPointer = (uint32)data;
81 fec->rbdBase[ix].status = FEC_RBD_EMPTY;
82 fec->rbdBase[ix].dataLength = 0;
87 * have the last RBD to close the ring
89 fec->rbdBase[ix - 1].status |= FEC_RBD_WRAP;
95 /********************************************************************/
96 static void mpc5xxx_fec_tbd_init(mpc5xxx_fec_priv *fec)
100 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
101 fec->tbdBase[ix].status = 0;
105 * Have the last TBD to close the ring
107 fec->tbdBase[ix - 1].status |= FEC_TBD_WRAP;
110 * Initialize some indices
113 fec->usedTbdIndex = 0;
114 fec->cleanTbdNum = FEC_TBD_NUM;
117 /********************************************************************/
118 static void mpc5xxx_fec_rbd_clean(mpc5xxx_fec_priv *fec, FEC_RBD * pRbd)
121 * Reset buffer descriptor as empty
123 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
124 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
126 pRbd->status = FEC_RBD_EMPTY;
128 pRbd->dataLength = 0;
131 * Now, we have an empty RxBD, restart the SmartDMA receive task
133 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
138 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
141 /********************************************************************/
142 static void mpc5xxx_fec_tbd_scrub(mpc5xxx_fec_priv *fec)
147 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
148 fec->cleanTbdNum, fec->usedTbdIndex);
152 * process all the consumed TBDs
154 while (fec->cleanTbdNum < FEC_TBD_NUM) {
155 pUsedTbd = &fec->tbdBase[fec->usedTbdIndex];
156 if (pUsedTbd->status & FEC_TBD_READY) {
158 printf("Cannot clean TBD %d, in use\n", fec->cleanTbdNum);
164 * clean this buffer descriptor
166 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
167 pUsedTbd->status = FEC_TBD_WRAP;
169 pUsedTbd->status = 0;
172 * update some indeces for a correct handling of the TBD ring
175 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
179 /********************************************************************/
180 static void mpc5xxx_fec_set_hwaddr(mpc5xxx_fec_priv *fec, char *mac)
182 uint8 currByte; /* byte for which to compute the CRC */
183 int byte; /* loop - counter */
184 int bit; /* loop - counter */
185 uint32 crc = 0xffffffff; /* initial value */
188 * The algorithm used is the following:
189 * we loop on each of the six bytes of the provided address,
190 * and we compute the CRC by left-shifting the previous
191 * value by one position, so that each bit in the current
192 * byte of the address may contribute the calculation. If
193 * the latter and the MSB in the CRC are different, then
194 * the CRC value so computed is also ex-ored with the
195 * "polynomium generator". The current byte of the address
196 * is also shifted right by one bit at each iteration.
197 * This is because the CRC generatore in hardware is implemented
198 * as a shift-register with as many ex-ores as the radixes
199 * in the polynomium. This suggests that we represent the
200 * polynomiumm itself as a 32-bit constant.
202 for (byte = 0; byte < 6; byte++) {
203 currByte = mac[byte];
204 for (bit = 0; bit < 8; bit++) {
205 if ((currByte & 0x01) ^ (crc & 0x01)) {
207 crc = crc ^ 0xedb88320;
218 * Set individual hash table register
221 fec->eth->iaddr1 = (1 << (crc - 32));
222 fec->eth->iaddr2 = 0;
224 fec->eth->iaddr1 = 0;
225 fec->eth->iaddr2 = (1 << crc);
229 * Set physical address
231 fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
232 fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
235 /********************************************************************/
236 static int mpc5xxx_fec_init(struct eth_device *dev, bd_t * bis)
238 DECLARE_GLOBAL_DATA_PTR;
239 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
240 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
243 printf ("mpc5xxx_fec_init... Begin\n");
247 * Initialize RxBD/TxBD rings
249 mpc5xxx_fec_rbd_init(fec);
250 mpc5xxx_fec_tbd_init(fec);
253 * Clear FEC-Lite interrupt event register(IEVENT)
255 fec->eth->ievent = 0xffffffff;
258 * Set interrupt mask register
260 fec->eth->imask = 0x00000000;
263 * Set FEC-Lite receive control register(R_CNTRL):
265 if (fec->xcv_type == SEVENWIRE) {
267 * Frame length=1518; 7-wire mode
269 fec->eth->r_cntrl = 0x05ee0020; /*0x05ee0000;FIXME */
272 * Frame length=1518; MII mode;
274 fec->eth->r_cntrl = 0x05ee0024; /*0x05ee0004;FIXME */
277 fec->eth->x_cntrl = 0x00000000; /* half-duplex, heartbeat disabled */
278 if (fec->xcv_type != SEVENWIRE) {
280 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
281 * and do not drop the Preamble.
283 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
287 * Set Opcode/Pause Duration Register
289 fec->eth->op_pause = 0x00010020; /*FIXME0xffff0020; */
292 * Set Rx FIFO alarm and granularity value
294 fec->eth->rfifo_cntrl = 0x0c000000;
295 fec->eth->rfifo_alarm = 0x0000030c;
297 if (fec->eth->rfifo_status & 0x00700000 ) {
298 printf("mpc5xxx_fec_init() RFIFO error\n");
303 * Set Tx FIFO granularity value
305 fec->eth->tfifo_cntrl = 0x0c000000;
307 printf("tfifo_status: 0x%08x\n", fec->eth->tfifo_status);
308 printf("tfifo_alarm: 0x%08x\n", fec->eth->tfifo_alarm);
312 * Set transmit fifo watermark register(X_WMRK), default = 64
314 fec->eth->tfifo_alarm = 0x00000080;
315 fec->eth->x_wmrk = 0x2;
318 * Set individual address filter for unicast address
319 * and set physical address registers.
321 mpc5xxx_fec_set_hwaddr(fec, dev->enetaddr);
324 * Set multicast address filter
326 fec->eth->gaddr1 = 0x00000000;
327 fec->eth->gaddr2 = 0x00000000;
330 * Turn ON cheater FSM: ????
332 fec->eth->xmit_fsm = 0x03000000;
334 #if defined(CONFIG_MPC5200)
336 * Turn off COMM bus prefetch in the MGT5200 BestComm. It doesn't
337 * work w/ the current receive task.
339 sdma->PtdCntrl |= 0x00000001;
343 * Set priority of different initiators
345 sdma->IPR0 = 7; /* always */
346 sdma->IPR3 = 6; /* Eth RX */
347 sdma->IPR4 = 5; /* Eth Tx */
350 * Clear SmartDMA task interrupt pending bits
352 SDMA_CLEAR_IEVENT(FEC_RECV_TASK_NO);
355 * Initialize SmartDMA parameters stored in SRAM
357 *(int *)FEC_TBD_BASE = (int)fec->tbdBase;
358 *(int *)FEC_RBD_BASE = (int)fec->rbdBase;
359 *(int *)FEC_TBD_NEXT = (int)fec->tbdBase;
360 *(int *)FEC_RBD_NEXT = (int)fec->rbdBase;
363 * Enable FEC-Lite controller
365 fec->eth->ecntrl |= 0x00000006;
368 if (fec->xcv_type != SEVENWIRE)
369 mpc5xxx_fec_phydump ();
373 * Enable SmartDMA receive task
375 SDMA_TASK_ENABLE(FEC_RECV_TASK_NO);
378 printf("mpc5xxx_fec_init... Done \n");
384 /********************************************************************/
385 static int mpc5xxx_fec_init_phy(struct eth_device *dev, bd_t * bis)
387 DECLARE_GLOBAL_DATA_PTR;
388 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
389 const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
392 printf ("mpc5xxx_fec_init_phy... Begin\n");
396 * Initialize GPIO pins
398 if (fec->xcv_type == SEVENWIRE) {
399 /* 10MBit with 7-wire operation */
400 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00020000;
402 /* 100MBit with MD operation */
403 *(vu_long *)MPC5XXX_GPS_PORT_CONFIG |= 0x00050000;
407 * Clear FEC-Lite interrupt event register(IEVENT)
409 fec->eth->ievent = 0xffffffff;
412 * Set interrupt mask register
414 fec->eth->imask = 0x00000000;
416 if (fec->xcv_type != SEVENWIRE) {
418 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
419 * and do not drop the Preamble.
421 fec->eth->mii_speed = (((gd->ipb_clk >> 20) / 5) << 1); /* No MII for 7-wire mode */
424 if (fec->xcv_type != SEVENWIRE) {
426 * Initialize PHY(LXT971A):
428 * Generally, on power up, the LXT971A reads its configuration
429 * pins to check for forced operation, If not cofigured for
430 * forced operation, it uses auto-negotiation/parallel detection
431 * to automatically determine line operating conditions.
432 * If the PHY device on the other side of the link supports
433 * auto-negotiation, the LXT971A auto-negotiates with it
434 * using Fast Link Pulse(FLP) Bursts. If the PHY partner does not
435 * support auto-negotiation, the LXT971A automatically detects
436 * the presence of either link pulses(10Mbps PHY) or Idle
437 * symbols(100Mbps) and sets its operating conditions accordingly.
439 * When auto-negotiation is controlled by software, the following
440 * steps are recommended.
443 * The physical address is dependent on hardware configuration.
450 * Reset PHY, then delay 300ns
452 miiphy_write(phyAddr, 0x0, 0x8000);
455 if (fec->xcv_type == MII10) {
457 * Force 10Base-T, FDX operation
460 printf("Forcing 10 Mbps ethernet link... ");
462 miiphy_read(phyAddr, 0x1, &phyStatus);
464 miiphy_write(fec, phyAddr, 0x0, 0x0100);
466 miiphy_write(phyAddr, 0x0, 0x0180);
469 do { /* wait for link status to go down */
471 if ((timeout--) == 0) {
473 printf("hmmm, should not have waited...");
477 miiphy_read(phyAddr, 0x1, &phyStatus);
481 } while ((phyStatus & 0x0004)); /* !link up */
484 do { /* wait for link status to come back up */
486 if ((timeout--) == 0) {
487 printf("failed. Link is down.\n");
490 miiphy_read(phyAddr, 0x1, &phyStatus);
494 } while (!(phyStatus & 0x0004)); /* !link up */
499 } else { /* MII100 */
501 * Set the auto-negotiation advertisement register bits
503 miiphy_write(phyAddr, 0x4, 0x01e1);
506 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
508 miiphy_write(phyAddr, 0x0, 0x1200);
511 * Wait for AN completion
517 if ((timeout--) == 0) {
519 printf("PHY auto neg 0 failed...\n");
524 if (miiphy_read(phyAddr, 0x1, &phyStatus) != 0) {
526 printf("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
530 } while (!(phyStatus & 0x0004));
533 printf("PHY auto neg complete! \n");
540 if (fec->xcv_type != SEVENWIRE)
541 mpc5xxx_fec_phydump ();
546 printf("mpc5xxx_fec_init_phy... Done \n");
552 /********************************************************************/
553 static void mpc5xxx_fec_halt(struct eth_device *dev)
555 #if defined(CONFIG_MPC5200)
556 struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
558 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
559 int counter = 0xffff;
562 if (fec->xcv_type != SEVENWIRE)
563 mpc5xxx_fec_phydump ();
567 * mask FEC chip interrupts
572 * issue graceful stop command to the FEC transmitter if necessary
574 fec->eth->x_cntrl |= 0x00000001;
577 * wait for graceful stop to register
579 while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
582 * Disable SmartDMA tasks
584 SDMA_TASK_DISABLE (FEC_XMIT_TASK_NO);
585 SDMA_TASK_DISABLE (FEC_RECV_TASK_NO);
587 #if defined(CONFIG_MPC5200)
589 * Turn on COMM bus prefetch in the MGT5200 BestComm after we're
590 * done. It doesn't work w/ the current receive task.
592 sdma->PtdCntrl &= ~0x00000001;
596 * Disable the Ethernet Controller
598 fec->eth->ecntrl &= 0xfffffffd;
601 * Clear FIFO status registers
603 fec->eth->rfifo_status &= 0x00700000;
604 fec->eth->tfifo_status &= 0x00700000;
606 fec->eth->reset_cntrl = 0x01000000;
609 * Issue a reset command to the FEC chip
611 fec->eth->ecntrl |= 0x1;
614 * wait at least 16 clock cycles
619 printf("Ethernet task stopped\n");
624 /********************************************************************/
626 static void tfifo_print(mpc5xxx_fec_priv *fec)
628 uint16 phyAddr = CONFIG_PHY_ADDR;
631 if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
632 || (fec->eth->tfifo_rdptr != fec->eth->tfifo_wrptr)) {
634 miiphy_read(phyAddr, 0x1, &phyStatus);
635 printf("\nphyStatus: 0x%04x\n", phyStatus);
636 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
637 printf("ievent: 0x%08x\n", fec->eth->ievent);
638 printf("x_status: 0x%08x\n", fec->eth->x_status);
639 printf("tfifo: status 0x%08x\n", fec->eth->tfifo_status);
641 printf(" control 0x%08x\n", fec->eth->tfifo_cntrl);
642 printf(" lrfp 0x%08x\n", fec->eth->tfifo_lrf_ptr);
643 printf(" lwfp 0x%08x\n", fec->eth->tfifo_lwf_ptr);
644 printf(" alarm 0x%08x\n", fec->eth->tfifo_alarm);
645 printf(" readptr 0x%08x\n", fec->eth->tfifo_rdptr);
646 printf(" writptr 0x%08x\n", fec->eth->tfifo_wrptr);
650 static void rfifo_print(mpc5xxx_fec_priv *fec)
652 uint16 phyAddr = CONFIG_PHY_ADDR;
655 if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
656 || (fec->eth->rfifo_rdptr != fec->eth->rfifo_wrptr)) {
658 miiphy_read(phyAddr, 0x1, &phyStatus);
659 printf("\nphyStatus: 0x%04x\n", phyStatus);
660 printf("ecntrl: 0x%08x\n", fec->eth->ecntrl);
661 printf("ievent: 0x%08x\n", fec->eth->ievent);
662 printf("x_status: 0x%08x\n", fec->eth->x_status);
663 printf("rfifo: status 0x%08x\n", fec->eth->rfifo_status);
665 printf(" control 0x%08x\n", fec->eth->rfifo_cntrl);
666 printf(" lrfp 0x%08x\n", fec->eth->rfifo_lrf_ptr);
667 printf(" lwfp 0x%08x\n", fec->eth->rfifo_lwf_ptr);
668 printf(" alarm 0x%08x\n", fec->eth->rfifo_alarm);
669 printf(" readptr 0x%08x\n", fec->eth->rfifo_rdptr);
670 printf(" writptr 0x%08x\n", fec->eth->rfifo_wrptr);
675 /********************************************************************/
677 static int mpc5xxx_fec_send(struct eth_device *dev, volatile void *eth_data,
681 * This routine transmits one frame. This routine only accepts
682 * 6-byte Ethernet addresses.
684 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
688 printf("tbd status: 0x%04x\n", fec->tbdBase[0].status);
693 * Clear Tx BD ring at first
695 mpc5xxx_fec_tbd_scrub(fec);
698 * Check for valid length of data.
700 if ((data_length > 1500) || (data_length <= 0)) {
705 * Check the number of vacant TxBDs.
707 if (fec->cleanTbdNum < 1) {
709 printf("No available TxBDs ...\n");
715 * Get the first TxBD to send the mac header
717 pTbd = &fec->tbdBase[fec->tbdIndex];
718 pTbd->dataLength = data_length;
719 pTbd->dataPointer = (uint32)eth_data;
720 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
721 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
724 printf("SDMA_TASK_ENABLE, fec->tbdIndex = %d \n", fec->tbdIndex);
730 if (fec->xcv_type != SEVENWIRE) {
732 miiphy_read(0, 0x1, &phyStatus);
736 * Enable SmartDMA transmit task
742 SDMA_TASK_ENABLE (FEC_XMIT_TASK_NO);
750 fec->cleanTbdNum -= 1;
752 #if (DEBUG & 0x129) && (DEBUG & 0x80000000)
753 printf ("smartDMA ethernet Tx task enabled\n");
756 * wait until frame is sent .
758 while (pTbd->status & FEC_TBD_READY) {
761 printf ("TDB status = %04x\n", pTbd->status);
769 /********************************************************************/
770 static int mpc5xxx_fec_recv(struct eth_device *dev)
773 * This command pulls one frame from the card
775 mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
776 FEC_RBD *pRbd = &fec->rbdBase[fec->rbdIndex];
777 unsigned long ievent;
778 int frame_length, len = 0;
780 char buff[FEC_MAX_PKT_SIZE];
783 printf ("mpc5xxx_fec_recv %d Start...\n", fec->rbdIndex);
790 * Check if any critical events have happened
792 ievent = fec->eth->ievent;
793 fec->eth->ievent = ievent;
794 if (ievent & 0x20060000) {
795 /* BABT, Rx/Tx FIFO errors */
796 mpc5xxx_fec_halt(dev);
797 mpc5xxx_fec_init(dev, NULL);
800 if (ievent & 0x80000000) {
801 /* Heartbeat error */
802 fec->eth->x_cntrl |= 0x00000001;
804 if (ievent & 0x10000000) {
805 /* Graceful stop complete */
806 if (fec->eth->x_cntrl & 0x00000001) {
807 mpc5xxx_fec_halt(dev);
808 fec->eth->x_cntrl &= ~0x00000001;
809 mpc5xxx_fec_init(dev, NULL);
813 if (!(pRbd->status & FEC_RBD_EMPTY)) {
814 if ((pRbd->status & FEC_RBD_LAST) && !(pRbd->status & FEC_RBD_ERR) &&
815 ((pRbd->dataLength - 4) > 14)) {
818 * Get buffer address and size
820 frame = (NBUF *)pRbd->dataPointer;
821 frame_length = pRbd->dataLength - 4;
826 printf("recv data hdr:");
827 for (i = 0; i < 14; i++)
828 printf("%x ", *(frame->head + i));
833 * Fill the buffer and pass it to upper layers
835 memcpy(buff, frame->head, 14);
836 memcpy(buff + 14, frame->data, frame_length);
837 NetReceive(buff, frame_length);
841 * Reset buffer descriptor as empty
843 mpc5xxx_fec_rbd_clean(fec, pRbd);
845 SDMA_CLEAR_IEVENT (FEC_RECV_TASK_NO);
850 /********************************************************************/
851 int mpc5xxx_fec_initialize(bd_t * bis)
853 mpc5xxx_fec_priv *fec;
854 struct eth_device *dev;
856 char env_enetaddr[6];
859 fec = (mpc5xxx_fec_priv *)malloc(sizeof(*fec));
860 dev = (struct eth_device *)malloc(sizeof(*dev));
861 memset(dev, 0, sizeof *dev);
863 fec->eth = (ethernet_regs *)MPC5XXX_FEC;
864 fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
865 fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
866 #if defined(CONFIG_ICECUBE) || defined(CONFIG_PM520) || \
867 defined(CONFIG_TOP5200) || defined(CONFIG_TQM5200)
868 # ifndef CONFIG_FEC_10MBIT
869 fec->xcv_type = MII100;
871 fec->xcv_type = MII10;
874 #error fec->xcv_type not initialized.
877 dev->priv = (void *)fec;
878 dev->iobase = MPC5XXX_FEC;
879 dev->init = mpc5xxx_fec_init;
880 dev->halt = mpc5xxx_fec_halt;
881 dev->send = mpc5xxx_fec_send;
882 dev->recv = mpc5xxx_fec_recv;
884 sprintf(dev->name, "FEC ETHERNET");
888 * Try to set the mac address now. The fec mac address is
889 * a garbage after reset. When not using fec for booting
890 * the Linux fec driver will try to work with this garbage.
892 tmp = getenv("ethaddr");
894 for (i=0; i<6; i++) {
895 env_enetaddr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
897 tmp = (*end) ? end+1 : end;
899 mpc5xxx_fec_set_hwaddr(fec, env_enetaddr);
902 mpc5xxx_fec_init_phy(dev, bis);
906 /* MII-interface related functions */
907 /********************************************************************/
908 int miiphy_read(uint8 phyAddr, uint8 regAddr, uint16 * retVal)
910 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
911 uint32 reg; /* convenient holder for the PHY register */
912 uint32 phy; /* convenient holder for the PHY */
913 int timeout = 0xffff;
916 * reading from any PHY's register is done by properly
917 * programming the FEC's MII data register.
919 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
920 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
922 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
925 * wait for the related interrupt
927 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
931 printf ("Read MDIO failed...\n");
937 * clear mii interrupt bit
939 eth->ievent = 0x00800000;
942 * it's now safe to read the PHY's register
944 *retVal = (uint16) eth->mii_data;
949 /********************************************************************/
950 int miiphy_write(uint8 phyAddr, uint8 regAddr, uint16 data)
952 ethernet_regs *eth = (ethernet_regs *)MPC5XXX_FEC;
953 uint32 reg; /* convenient holder for the PHY register */
954 uint32 phy; /* convenient holder for the PHY */
955 int timeout = 0xffff;
957 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
958 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
960 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
961 FEC_MII_DATA_TA | phy | reg | data);
964 * wait for the MII interrupt
966 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
970 printf ("Write MDIO failed...\n");
976 * clear MII interrupt bit
978 eth->ievent = 0x00800000;
984 static uint32 local_crc32(char *string, unsigned int crc_value, int len)
988 unsigned int crc, count;
994 * crc = 0xffffffff; * The initialized value should be 0xffffffff
998 for (i = len; --i >= 0;) {
1000 for (count = 0; count < 8; count++) {
1001 if ((c & 0x01) ^ (crc & 0x01)) {
1003 crc = crc ^ 0xedb88320;
1012 * In big endian system, do byte swaping for crc value
1018 #endif /* CONFIG_MPC5xxx_FEC */