2 * (C) Copyright 2000-2009
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 DECLARE_GLOBAL_DATA_PTR;
31 * Breath some life into the CPU...
33 * Set up the memory map,
34 * initialize a bunch of registers.
36 void cpu_init_f (void)
38 volatile struct mpc5xxx_mmap_ctl *mm =
39 (struct mpc5xxx_mmap_ctl *) CONFIG_SYS_MBAR;
40 volatile struct mpc5xxx_lpb *lpb =
41 (struct mpc5xxx_lpb *) MPC5XXX_LPB;
42 volatile struct mpc5xxx_cdm *cdm =
43 (struct mpc5xxx_cdm *) MPC5XXX_CDM;
44 volatile struct mpc5xxx_gpio *gpio =
45 (struct mpc5xxx_gpio *) MPC5XXX_GPIO;
46 volatile struct mpc5xxx_xlb *xlb =
47 (struct mpc5xxx_xlb *) MPC5XXX_XLBARB;
48 unsigned long addecr = (1 << 25); /* Boot_CS */
49 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_MGT5100)
50 addecr |= (1 << 22); /* SDRAM enable */
52 /* Pointer is writable since we allocated a register for it */
53 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
55 /* Clear initial global data */
56 memset ((void *) gd, 0, sizeof (gd_t));
59 * Memory Controller: configure chip selects and enable them
61 #if defined(CONFIG_SYS_BOOTCS_START) && defined(CONFIG_SYS_BOOTCS_SIZE)
62 out_be32(&mm->boot_start, START_REG(CONFIG_SYS_BOOTCS_START));
63 out_be32(&mm->boot_stop, STOP_REG(CONFIG_SYS_BOOTCS_START,
64 CONFIG_SYS_BOOTCS_SIZE));
66 #if defined(CONFIG_SYS_BOOTCS_CFG)
67 out_be32(&lpb->cs0_cfg, CONFIG_SYS_BOOTCS_CFG);
70 #if defined(CONFIG_SYS_CS0_START) && defined(CONFIG_SYS_CS0_SIZE)
71 out_be32(&mm->cs0_start, START_REG(CONFIG_SYS_CS0_START));
72 out_be32(&mm->cs0_stop, STOP_REG(CONFIG_SYS_CS0_START,
73 CONFIG_SYS_CS0_SIZE));
74 /* CS0 and BOOT_CS cannot be enabled at once. */
75 /* addecr |= (1 << 16); */
77 #if defined(CONFIG_SYS_CS0_CFG)
78 out_be32(&lpb->cs0_cfg, CONFIG_SYS_CS0_CFG);
81 #if defined(CONFIG_SYS_CS1_START) && defined(CONFIG_SYS_CS1_SIZE)
82 out_be32(&mm->cs1_start, START_REG(CONFIG_SYS_CS1_START));
83 out_be32(&mm->cs1_stop, STOP_REG(CONFIG_SYS_CS1_START,
84 CONFIG_SYS_CS1_SIZE));
87 #if defined(CONFIG_SYS_CS1_CFG)
88 out_be32(&lpb->cs1_cfg, CONFIG_SYS_CS1_CFG);
91 #if defined(CONFIG_SYS_CS2_START) && defined(CONFIG_SYS_CS2_SIZE)
92 out_be32(&mm->cs2_start, START_REG(CONFIG_SYS_CS2_START));
93 out_be32(&mm->cs2_stop, STOP_REG(CONFIG_SYS_CS2_START,
94 CONFIG_SYS_CS2_SIZE));
97 #if defined(CONFIG_SYS_CS2_CFG)
98 out_be32(&lpb->cs2_cfg, CONFIG_SYS_CS2_CFG);
101 #if defined(CONFIG_SYS_CS3_START) && defined(CONFIG_SYS_CS3_SIZE)
102 out_be32(&mm->cs3_start, START_REG(CONFIG_SYS_CS3_START));
103 out_be32(&mm->cs3_stop, STOP_REG(CONFIG_SYS_CS3_START,
104 CONFIG_SYS_CS3_SIZE));
107 #if defined(CONFIG_SYS_CS3_CFG)
108 out_be32(&lpb->cs3_cfg, CONFIG_SYS_CS3_CFG);
111 #if defined(CONFIG_SYS_CS4_START) && defined(CONFIG_SYS_CS4_SIZE)
112 out_be32(&mm->cs4_start, START_REG(CONFIG_SYS_CS4_START));
113 out_be32(&mm->cs4_stop, STOP_REG(CONFIG_SYS_CS4_START,
114 CONFIG_SYS_CS4_SIZE));
117 #if defined(CONFIG_SYS_CS4_CFG)
118 out_be32(&lpb->cs4_cfg, CONFIG_SYS_CS4_CFG);
121 #if defined(CONFIG_SYS_CS5_START) && defined(CONFIG_SYS_CS5_SIZE)
122 out_be32(&mm->cs5_start, START_REG(CONFIG_SYS_CS5_START));
123 out_be32(&mm->cs5_stop, STOP_REG(CONFIG_SYS_CS5_START,
124 CONFIG_SYS_CS5_SIZE));
127 #if defined(CONFIG_SYS_CS5_CFG)
128 out_be32(&lpb->cs5_cfg, CONFIG_SYS_CS5_CFG);
131 #if defined(CONFIG_MPC5200)
133 #if defined(CONFIG_SYS_CS6_START) && defined(CONFIG_SYS_CS6_SIZE)
134 out_be32(&mm->cs6_start, START_REG(CONFIG_SYS_CS6_START));
135 out_be32(&mm->cs6_stop, STOP_REG(CONFIG_SYS_CS6_START,
136 CONFIG_SYS_CS6_SIZE));
139 #if defined(CONFIG_SYS_CS6_CFG)
140 out_be32(&lpb->cs6_cfg, CONFIG_SYS_CS6_CFG);
143 #if defined(CONFIG_SYS_CS7_START) && defined(CONFIG_SYS_CS7_SIZE)
144 out_be32(&mm->cs7_start, START_REG(CONFIG_SYS_CS7_START));
145 out_be32(&mm->cs7_stop, STOP_REG(CONFIG_SYS_CS7_START,
146 CONFIG_SYS_CS7_SIZE));
149 #if defined(CONFIG_SYS_CS7_CFG)
150 out_be32(&lpb->cs7_cfg, CONFIG_SYS_CS7_CFG);
153 #if defined(CONFIG_SYS_CS_BURST)
154 out_be32(&lpb->cs_burst, CONFIG_SYS_CS_BURST);
156 #if defined(CONFIG_SYS_CS_DEADCYCLE)
157 out_be32(&lpb->cs_deadcycle, CONFIG_SYS_CS_DEADCYCLE);
159 #endif /* CONFIG_MPC5200 */
161 /* Enable chip selects */
162 #if defined(CONFIG_MGT5100)
163 out_be32(&mm->addecr, addecr);
164 #elif defined(CONFIG_MPC5200)
165 out_be32(&mm->ipbi_ws_ctrl, addecr);
167 out_be32(&lpb->cs_ctrl, (1 << 24));
169 /* Setup pin multiplexing */
170 #if defined(CONFIG_SYS_GPS_PORT_CONFIG)
171 out_be32(&gpio->port_config, CONFIG_SYS_GPS_PORT_CONFIG);
174 #if defined(CONFIG_MPC5200)
175 /* enable timebase */
176 setbits_be32(&xlb->config, (1 << 13));
178 /* Enable snooping for RAM */
179 setbits_be32(&xlb->config, (1 << 15));
180 out_be32(&xlb->snoop_window, CONFIG_SYS_SDRAM_BASE | 0x1d);
182 # if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
183 /* Motorola reports IPB should better run at 133 MHz. */
184 #if defined(CONFIG_MGT5100)
185 setbits_be32(&mm->addecr, 1);
186 #elif defined(CONFIG_MPC5200)
187 setbits_be32(&mm->ipbi_ws_ctrl, 1);
189 /* pci_clk_sel = 0x02, ipb_clk_sel = 0x00; */
190 addecr = in_be32(&cdm->cfg);
192 # if defined(CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2)
193 /* pci_clk_sel = 0x01 -> IPB_CLK/2 */
196 /* pci_clk_sel = 0x02 -> XLB_CLK/4 = IPB_CLK/4 */
198 # endif /* CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 */
199 out_be32(&cdm->cfg, addecr);
200 # endif /* CONFIG_SYS_IPBCLK_EQUALS_XLBCLK */
201 /* Configure the XLB Arbiter */
202 out_be32(&xlb->master_pri_enable, 0xff);
203 out_be32(&xlb->master_priority, 0x11111111);
205 # if defined(CONFIG_SYS_XLB_PIPELINING)
206 /* Enable piplining */
207 clrbits_be32(&xlb->config, (1 << 31));
209 #endif /* CONFIG_MPC5200 */
213 * initialize higher level parts of CPU like time base and timers
215 int cpu_init_r (void)
217 volatile struct mpc5xxx_intr *intr =
218 (struct mpc5xxx_intr *) MPC5XXX_ICTL;
220 /* mask all interrupts */
221 #if defined(CONFIG_MGT5100)
222 out_be32(&intr->per_mask, 0xfffffc00);
223 #elif defined(CONFIG_MPC5200)
224 out_be32(&intr->per_mask, 0xffffff00);
226 setbits_be32(&intr->main_mask, 0x0001ffff);
227 clrbits_be32(&intr->ctrl, 0x00000f00);
228 /* route critical ints to normal ints */
229 setbits_be32(&intr->ctrl, 0x00000001);
231 #if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC5xxx_FEC)
232 /* load FEC microcode */