2 * (C) Copyright 2003-2007
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Derived from the MPC8xx FEC driver.
6 * Adapted for MPC512x by Grzegorz Bernacki <gjb@semihalf.com>
16 DECLARE_GLOBAL_DATA_PTR;
20 #if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
21 defined(CONFIG_MPC512x_FEC)
23 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
24 #error "CONFIG_MII has to be defined!"
28 static uint32 local_crc32(char *string, unsigned int crc_value, int len);
31 int fec512x_miiphy_read(char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal);
32 int fec512x_miiphy_write(char *devname, uint8 phyAddr, uint8 regAddr, uint16 data);
33 int mpc512x_fec_init_phy(struct eth_device *dev, bd_t * bis);
35 static uchar rx_buff[FEC_BUFFER_SIZE];
36 static int rx_buff_idx = 0;
38 /********************************************************************/
40 static void mpc512x_fec_phydump (char *devname)
43 uint8 phyAddr = CONFIG_PHY_ADDR;
45 /* regs to print: 0...8, 21,27,31 */
46 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0,
47 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1,
50 for (i = 0; i < 32; i++) {
52 miiphy_read (devname, phyAddr, i, &phyStatus);
53 printf ("Mii reg %d: 0x%04x\n", i, phyStatus);
59 /********************************************************************/
60 static int mpc512x_fec_bd_init (mpc512x_fec_priv *fec)
67 for (ix = 0; ix < FEC_RBD_NUM; ix++) {
68 fec->bdBase->rbd[ix].dataPointer = (uint32)&fec->bdBase->recv_frames[ix];
69 fec->bdBase->rbd[ix].status = FEC_RBD_EMPTY;
70 fec->bdBase->rbd[ix].dataLength = 0;
74 * have the last RBD to close the ring
76 fec->bdBase->rbd[ix - 1].status |= FEC_RBD_WRAP;
82 for (ix = 0; ix < FEC_TBD_NUM; ix++) {
83 fec->bdBase->tbd[ix].status = 0;
87 * Have the last TBD to close the ring
89 fec->bdBase->tbd[ix - 1].status |= FEC_TBD_WRAP;
92 * Initialize some indices
95 fec->usedTbdIndex = 0;
96 fec->cleanTbdNum = FEC_TBD_NUM;
101 /********************************************************************/
102 static void mpc512x_fec_rbd_clean (mpc512x_fec_priv *fec, volatile FEC_RBD * pRbd)
105 * Reset buffer descriptor as empty
107 if ((fec->rbdIndex) == (FEC_RBD_NUM - 1))
108 pRbd->status = (FEC_RBD_WRAP | FEC_RBD_EMPTY);
110 pRbd->status = FEC_RBD_EMPTY;
112 pRbd->dataLength = 0;
117 fec->rbdIndex = (fec->rbdIndex + 1) % FEC_RBD_NUM;
120 * Now, we have an empty RxBD, notify FEC
122 fec->eth->r_des_active = 0x01000000; /* Descriptor polling active */
125 /********************************************************************/
126 static void mpc512x_fec_tbd_scrub (mpc512x_fec_priv *fec)
128 volatile FEC_TBD *pUsedTbd;
131 printf ("tbd_scrub: fec->cleanTbdNum = %d, fec->usedTbdIndex = %d\n",
132 fec->cleanTbdNum, fec->usedTbdIndex);
136 * process all the consumed TBDs
138 while (fec->cleanTbdNum < FEC_TBD_NUM) {
139 pUsedTbd = &fec->bdBase->tbd[fec->usedTbdIndex];
140 if (pUsedTbd->status & FEC_TBD_READY) {
142 printf ("Cannot clean TBD %d, in use\n", fec->usedTbdIndex);
148 * clean this buffer descriptor
150 if (fec->usedTbdIndex == (FEC_TBD_NUM - 1))
151 pUsedTbd->status = FEC_TBD_WRAP;
153 pUsedTbd->status = 0;
156 * update some indeces for a correct handling of the TBD ring
159 fec->usedTbdIndex = (fec->usedTbdIndex + 1) % FEC_TBD_NUM;
163 /********************************************************************/
164 static void mpc512x_fec_set_hwaddr (mpc512x_fec_priv *fec, char *mac)
166 uint8 currByte; /* byte for which to compute the CRC */
167 int byte; /* loop - counter */
168 int bit; /* loop - counter */
169 uint32 crc = 0xffffffff; /* initial value */
172 * The algorithm used is the following:
173 * we loop on each of the six bytes of the provided address,
174 * and we compute the CRC by left-shifting the previous
175 * value by one position, so that each bit in the current
176 * byte of the address may contribute the calculation. If
177 * the latter and the MSB in the CRC are different, then
178 * the CRC value so computed is also ex-ored with the
179 * "polynomium generator". The current byte of the address
180 * is also shifted right by one bit at each iteration.
181 * This is because the CRC generatore in hardware is implemented
182 * as a shift-register with as many ex-ores as the radixes
183 * in the polynomium. This suggests that we represent the
184 * polynomiumm itself as a 32-bit constant.
186 for (byte = 0; byte < 6; byte++) {
187 currByte = mac[byte];
188 for (bit = 0; bit < 8; bit++) {
189 if ((currByte & 0x01) ^ (crc & 0x01)) {
191 crc = crc ^ 0xedb88320;
202 * Set individual hash table register
205 fec->eth->iaddr1 = (1 << (crc - 32));
206 fec->eth->iaddr2 = 0;
208 fec->eth->iaddr1 = 0;
209 fec->eth->iaddr2 = (1 << crc);
213 * Set physical address
215 fec->eth->paddr1 = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3];
216 fec->eth->paddr2 = (mac[4] << 24) + (mac[5] << 16) + 0x8808;
219 /********************************************************************/
220 static int mpc512x_fec_init (struct eth_device *dev, bd_t * bis)
222 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
225 printf ("mpc512x_fec_init... Begin\n");
228 /* Set interrupt mask register */
229 fec->eth->imask = 0x00000000;
231 /* Clear FEC-Lite interrupt event register(IEVENT) */
232 fec->eth->ievent = 0xffffffff;
234 /* Set transmit fifo watermark register(X_WMRK), default = 64 */
235 fec->eth->x_wmrk = 0x0;
237 /* Set Opcode/Pause Duration Register */
238 fec->eth->op_pause = 0x00010020;
240 /* Frame length=1522; MII mode */
241 fec->eth->r_cntrl = (FEC_MAX_FRAME_LEN << 16) | 0x24;
243 /* Half-duplex, heartbeat disabled */
244 fec->eth->x_cntrl = 0x00000000;
246 /* Enable MIB counters */
247 fec->eth->mib_control = 0x0;
249 /* Setup recv fifo start and buff size */
250 fec->eth->r_fstart = 0x500;
251 fec->eth->r_buff_size = FEC_BUFFER_SIZE;
253 /* Setup BD base addresses */
254 fec->eth->r_des_start = (uint32)fec->bdBase->rbd;
255 fec->eth->x_des_start = (uint32)fec->bdBase->tbd;
258 fec->eth->dma_control = 0xc0000000;
261 fec->eth->ecntrl |= 0x00000006;
263 /* Initilize addresses and status words of BDs */
264 mpc512x_fec_bd_init (fec);
266 /* Descriptor polling active */
267 fec->eth->r_des_active = 0x01000000;
270 printf("mpc512x_fec_init... Done \n");
275 /********************************************************************/
276 int mpc512x_fec_init_phy (struct eth_device *dev, bd_t * bis)
278 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
279 const uint8 phyAddr = CONFIG_PHY_ADDR; /* Only one PHY */
284 printf ("mpc512x_fec_init_phy... Begin\n");
288 * Clear FEC-Lite interrupt event register(IEVENT)
290 fec->eth->ievent = 0xffffffff;
293 * Set interrupt mask register
295 fec->eth->imask = 0x00000000;
297 if (fec->xcv_type != SEVENWIRE) {
299 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
300 * and do not drop the Preamble.
302 fec->eth->mii_speed = (((gd->ipb_clk / 1000000) / 5) + 1) << 1;
305 * Reset PHY, then delay 300ns
307 miiphy_write (dev->name, phyAddr, 0x0, 0x8000);
310 if (fec->xcv_type == MII10) {
312 * Force 10Base-T, FDX operation
315 printf ("Forcing 10 Mbps ethernet link... ");
317 miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
319 miiphy_write (dev->name, phyAddr, 0x0, 0x0180);
322 do { /* wait for link status to go down */
324 if ((timeout--) == 0) {
326 printf ("hmmm, should not have waited...");
330 miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
334 } while ((phyStatus & 0x0004)); /* !link up */
337 do { /* wait for link status to come back up */
339 if ((timeout--) == 0) {
340 printf ("failed. Link is down.\n");
343 miiphy_read (dev->name, phyAddr, 0x1, &phyStatus);
347 } while (!(phyStatus & 0x0004)); /* !link up */
352 } else { /* MII100 */
354 * Set the auto-negotiation advertisement register bits
356 miiphy_write (dev->name, phyAddr, 0x4, 0x01e1);
359 * Set MDIO bit 0.12 = 1(&& bit 0.9=1?) to enable auto-negotiation
361 miiphy_write (dev->name, phyAddr, 0x0, 0x1200);
364 * Wait for AN completion
370 if ((timeout--) == 0) {
372 printf ("PHY auto neg 0 failed...\n");
377 if (miiphy_read (dev->name, phyAddr, 0x1, &phyStatus) != 0) {
379 printf ("PHY auto neg 1 failed 0x%04x...\n", phyStatus);
383 } while (!(phyStatus & 0x0004));
386 printf ("PHY auto neg complete! \n");
392 if (fec->xcv_type != SEVENWIRE)
393 mpc512x_fec_phydump (dev->name);
397 printf ("mpc512x_fec_init_phy... Done \n");
402 /********************************************************************/
403 static void mpc512x_fec_halt (struct eth_device *dev)
405 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
406 int counter = 0xffff;
409 if (fec->xcv_type != SEVENWIRE)
410 mpc512x_fec_phydump (dev->name);
414 * mask FEC chip interrupts
419 * issue graceful stop command to the FEC transmitter if necessary
421 fec->eth->x_cntrl |= 0x00000001;
424 * wait for graceful stop to register
426 while ((counter--) && (!(fec->eth->ievent & 0x10000000))) ;
429 * Disable the Ethernet Controller
431 fec->eth->ecntrl &= 0xfffffffd;
434 * Issue a reset command to the FEC chip
436 fec->eth->ecntrl |= 0x1;
439 * wait at least 16 clock cycles
443 printf ("Ethernet task stopped\n");
447 /********************************************************************/
449 static int mpc512x_fec_send (struct eth_device *dev, volatile void *eth_data,
453 * This routine transmits one frame. This routine only accepts
454 * 6-byte Ethernet addresses.
456 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
457 volatile FEC_TBD *pTbd;
460 printf("tbd status: 0x%04x\n", fec->tbdBase[fec->tbdIndex].status);
464 * Clear Tx BD ring at first
466 mpc512x_fec_tbd_scrub (fec);
469 * Check for valid length of data.
471 if ((data_length > 1500) || (data_length <= 0)) {
476 * Check the number of vacant TxBDs.
478 if (fec->cleanTbdNum < 1) {
480 printf ("No available TxBDs ...\n");
486 * Get the first TxBD to send the mac header
488 pTbd = &fec->bdBase->tbd[fec->tbdIndex];
489 pTbd->dataLength = data_length;
490 pTbd->dataPointer = (uint32)eth_data;
491 pTbd->status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
492 fec->tbdIndex = (fec->tbdIndex + 1) % FEC_TBD_NUM;
494 /* Activate transmit Buffer Descriptor polling */
495 fec->eth->x_des_active = 0x01000000; /* Descriptor polling active */
501 fec->cleanTbdNum -= 1;
504 * wait until frame is sent .
506 while (pTbd->status & FEC_TBD_READY) {
509 printf ("TDB status = %04x\n", pTbd->status);
517 /********************************************************************/
518 static int mpc512x_fec_recv (struct eth_device *dev)
521 * This command pulls one frame from the card
523 mpc512x_fec_priv *fec = (mpc512x_fec_priv *)dev->priv;
524 volatile FEC_RBD *pRbd = &fec->bdBase->rbd[fec->rbdIndex];
525 unsigned long ievent;
526 int frame_length = 0;
529 printf ("mpc512x_fec_recv %d Start...\n", fec->rbdIndex);
536 * Check if any critical events have happened
538 ievent = fec->eth->ievent;
539 fec->eth->ievent = ievent;
540 if (ievent & 0x20060000) {
541 /* BABT, Rx/Tx FIFO errors */
542 mpc512x_fec_halt (dev);
543 mpc512x_fec_init (dev, NULL);
546 if (ievent & 0x80000000) {
547 /* Heartbeat error */
548 fec->eth->x_cntrl |= 0x00000001;
550 if (ievent & 0x10000000) {
551 /* Graceful stop complete */
552 if (fec->eth->x_cntrl & 0x00000001) {
553 mpc512x_fec_halt (dev);
554 fec->eth->x_cntrl &= ~0x00000001;
555 mpc512x_fec_init (dev, NULL);
559 if (!(pRbd->status & FEC_RBD_EMPTY)) {
560 if (!(pRbd->status & FEC_RBD_ERR) &&
561 ((pRbd->dataLength - 4) > 14)) {
566 if (pRbd->status & FEC_RBD_LAST)
567 frame_length = pRbd->dataLength - 4;
569 frame_length = pRbd->dataLength;
573 printf ("recv data length 0x%08x data hdr: ",
575 for (i = 0; i < 14; i++)
576 printf ("%x ", *((uint8*)pRbd->dataPointer + i));
581 * Fill the buffer and pass it to upper layers
583 memcpy (&rx_buff[rx_buff_idx], (void*)pRbd->dataPointer,
584 frame_length - rx_buff_idx);
585 rx_buff_idx = frame_length;
587 if (pRbd->status & FEC_RBD_LAST) {
588 NetReceive ((uchar*)rx_buff, frame_length);
594 * Reset buffer descriptor as empty
596 mpc512x_fec_rbd_clean (fec, pRbd);
599 /* Try to fill Buffer Descriptors */
600 fec->eth->r_des_active = 0x01000000; /* Descriptor polling active */
604 /********************************************************************/
605 int mpc512x_fec_initialize (bd_t * bis)
608 immap_t *im = (immap_t*) CFG_IMMR;
609 mpc512x_fec_priv *fec;
610 struct eth_device *dev;
612 char *tmp, *end, env_enetaddr[6];
616 fec = (mpc512x_fec_priv *) malloc (sizeof(*fec));
617 dev = (struct eth_device *) malloc (sizeof(*dev));
618 memset (dev, 0, sizeof *dev);
620 fec->eth = (ethernet_regs *) MPC512X_FEC;
622 # ifndef CONFIG_FEC_10MBIT
623 fec->xcv_type = MII100;
625 fec->xcv_type = MII10;
627 dev->priv = (void *)fec;
628 dev->iobase = MPC512X_FEC;
629 dev->init = mpc512x_fec_init;
630 dev->halt = mpc512x_fec_halt;
631 dev->send = mpc512x_fec_send;
632 dev->recv = mpc512x_fec_recv;
634 sprintf (dev->name, "FEC ETHERNET");
637 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
638 miiphy_register (dev->name,
639 fec512x_miiphy_read, fec512x_miiphy_write);
643 * Initialize I\O pins
645 reg = (uint32 *) &(im->io_ctrl.regs[PSC0_0_IDX]);
647 for (i = 0; i < 15; i++)
648 reg[i] = IOCTRL_MUX_FEC | 0x00000001;
650 im->io_ctrl.regs[SPDIF_TXCLOCK_IDX] = IOCTRL_MUX_FEC | 0x00000001;
651 im->io_ctrl.regs[SPDIF_TX_IDX] = IOCTRL_MUX_FEC | 0x00000001;
652 im->io_ctrl.regs[SPDIF_RX_IDX] = IOCTRL_MUX_FEC | 0x00000001;
654 /* Clean up space FEC's MIB and FIFO RAM ...*/
655 memset ((void *) MPC512X_FEC + 0x200, 0x00, 0x400);
658 * Malloc space for BDs (must be quad word-aligned)
659 * this pointer is lost, so cannot be freed
661 bd = malloc (sizeof(mpc512x_buff_descs) + 0x1f);
662 fec->bdBase = (mpc512x_buff_descs*)((uint32)bd & 0xfffffff0);
663 memset ((void *) bd, 0x00, sizeof(mpc512x_buff_descs) + 0x1f);
666 * Set interrupt mask register
668 fec->eth->imask = 0x00000000;
671 * Clear FEC-Lite interrupt event register(IEVENT)
673 fec->eth->ievent = 0xffffffff;
676 * Try to set the mac address now. The fec mac address is
677 * a garbage after reset. When not using fec for booting
678 * the Linux fec driver will try to work with this garbage.
680 tmp = getenv ("ethaddr");
682 for (i=0; i<6; i++) {
683 env_enetaddr[i] = tmp ? simple_strtoul (tmp, &end, 16) : 0;
685 tmp = (*end) ? end+1 : end;
687 mpc512x_fec_set_hwaddr (fec, env_enetaddr);
688 fec->eth->gaddr1 = 0x00000000;
689 fec->eth->gaddr2 = 0x00000000;
692 mpc512x_fec_init_phy (dev, bis);
697 /* MII-interface related functions */
698 /********************************************************************/
699 int fec512x_miiphy_read (char *devname, uint8 phyAddr, uint8 regAddr, uint16 * retVal)
701 ethernet_regs *eth = (ethernet_regs *) MPC512X_FEC;
702 uint32 reg; /* convenient holder for the PHY register */
703 uint32 phy; /* convenient holder for the PHY */
704 int timeout = 0xffff;
707 * reading from any PHY's register is done by properly
708 * programming the FEC's MII data register.
710 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
711 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
713 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA | phy | reg);
716 * wait for the related interrupt
718 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
722 printf ("Read MDIO failed...\n");
728 * clear mii interrupt bit
730 eth->ievent = 0x00800000;
733 * it's now safe to read the PHY's register
735 *retVal = (uint16) eth->mii_data;
740 /********************************************************************/
741 int fec512x_miiphy_write (char *devname, uint8 phyAddr, uint8 regAddr, uint16 data)
743 ethernet_regs *eth = (ethernet_regs *) MPC512X_FEC;
744 uint32 reg; /* convenient holder for the PHY register */
745 uint32 phy; /* convenient holder for the PHY */
746 int timeout = 0xffff;
748 reg = regAddr << FEC_MII_DATA_RA_SHIFT;
749 phy = phyAddr << FEC_MII_DATA_PA_SHIFT;
751 eth->mii_data = (FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
752 FEC_MII_DATA_TA | phy | reg | data);
755 * wait for the MII interrupt
757 while ((timeout--) && (!(eth->ievent & 0x00800000))) ;
761 printf ("Write MDIO failed...\n");
767 * clear MII interrupt bit
769 eth->ievent = 0x00800000;
775 static uint32 local_crc32 (char *string, unsigned int crc_value, int len)
779 unsigned int crc, count;
785 * crc = 0xffffffff; * The initialized value should be 0xffffffff
789 for (i = len; --i >= 0;) {
791 for (count = 0; count < 8; count++) {
792 if ((c & 0x01) ^ (crc & 0x01)) {
794 crc = crc ^ 0xedb88320;
803 * In big endian system, do byte swaping for crc value
809 #endif /* CONFIG_MPC512x_FEC */