2 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
3 * (C) Copyright 2007 DENX Software Engineering
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * CPU specific code for the MPC512x family.
27 * Derived from the MPC83xx code.
33 #include <asm/processor.h>
35 #if defined(CONFIG_OF_LIBFDT)
36 #include <fdt_support.h>
39 DECLARE_GLOBAL_DATA_PTR;
43 volatile immap_t *immr = (immap_t *) CFG_IMMR;
44 ulong clock = gd->cpu_clk;
46 u32 spridr = immr->sysconf.spridr;
51 switch (spridr & 0xffff0000) {
56 printf ("Unknown part ID %08x ", spridr & 0xffff0000);
58 printf ("rev. %d.%d, Core ", SVR_MJREV (spridr), SVR_MNREV (spridr));
60 switch (pvr & 0xffff0000) {
67 printf ("at %s MHz, CSB at %3d MHz\n", strmhz(buf, clock),
68 gd->csb_clk / 1000000);
74 do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
77 volatile immap_t *immap = (immap_t *) CFG_IMMR;
79 /* Interrupts and MMU off */
80 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
82 msr &= ~( MSR_EE | MSR_IR | MSR_DR);
83 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
86 * Enable Reset Control Reg - "RSTE" is the magic word that let us go
88 immap->reset.rpr = 0x52535445;
90 /* Verify Reset Control Reg is enabled */
91 while (!((immap->reset.rcer) & RCER_CRE))
94 printf ("Resetting the board.\n");
98 immap->reset.rcr = RCR_SWHR;
106 * Get timebase clock frequency (like cpu_clk in Hz)
108 unsigned long get_tbclk (void)
112 tbclk = (gd->bus_clk + 3L) / 4L;
118 #if defined(CONFIG_WATCHDOG)
119 void watchdog_reset (void)
121 int re_enable = disable_interrupts ();
124 volatile immap_t *immr = (immap_t *) CFG_IMMR;
125 immr->wdt.swsrr = 0x556c;
126 immr->wdt.swsrr = 0xaa39;
129 enable_interrupts ();
133 #ifdef CONFIG_OF_LIBFDT
134 void ft_cpu_setup(void *blob, bd_t *bd)
136 char * cpu_path = "/cpus/" OF_CPU;
137 char * eth_path = "/" OF_SOC "/ethernet@2800";
139 do_fixup_by_path_u32(blob, cpu_path, "timebase-frequency", OF_TBCLK, 1);
140 do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1);
141 do_fixup_by_path_u32(blob, cpu_path, "clock-frequency", bd->bi_intfreq, 1);
142 do_fixup_by_path_u32(blob, "/" OF_SOC, "bus-frequency", bd->bi_ipsfreq, 1);
143 do_fixup_by_path(blob, eth_path, "local-mac-address", bd->bi_enetaddr, 6, 0);
145 /* this is so old kernels with old device trees will boot */
146 do_fixup_by_path_u32(blob, "/" OF_SOC_OLD, "bus-frequency", bd->bi_ipsfreq, 0);